V3 schematics review, January 2018
Reviewers:* T.Wlostowski, M. Rizzi, J.Gill
Commit:*
490f3b2f
Motivation for changes between v2.0 and v3.0
Migrating the RFoWR demo to uRISCV mockturtle architecture has highlighed a few issues with this design and this is an opportunity to address some of the issues, namely:
- Anti-aliasing filter placed between the ADF4002 and the ADC. The details are listed here, https://www.ohwr.org/project/fmc-dac-600m-12b-1cha-dds/work_packages/1250/activity.
- RF input impedance mismatch as detailed here, https://www.ohwr.org/project/fmc-dac-600m-12b-1cha-dds/work_packages/1279/activity.
- Impossible to use pulse output without using VCXO PLL, https://www.ohwr.org/project/fmc-dac-600m-12b-1cha-dds/work_packages/1261/activity
- Replacing the 9510 + VCXO with 9516, https://www.ohwr.org/project/fmc-dac-600m-12b-1cha-dds/work_packages/1191/activity
Schematics received from Creotech, scheduled review for 10/12/2018.