V3 schematics review, December 2018
Reviewers:* T.Wlostowski, M. Rizzi, J.Gill
Commit:*
490f3b2f
Motivation for changes between v2.0 and v3.0
Migrating the RFoWR demo to uRISCV mockturtle architecture has highlighed a few issues with this design and this is an opportunity to address some of the issues, namely:
- Anti-aliasing filter placed between the ADF4002 and the ADC. The details are listed here, https://www.ohwr.org/project/fmc-dac-600m-12b-1cha-dds/work_packages/1250/activity.
- RF input impedance mismatch as detailed here, https://www.ohwr.org/project/fmc-dac-600m-12b-1cha-dds/work_packages/1279/activity.
- Impossible to use pulse output without using VCXO PLL, https://www.ohwr.org/project/fmc-dac-600m-12b-1cha-dds/work_packages/1261/activity
- Replacing the 9510 + VCXO with 9516, https://www.ohwr.org/project/fmc-dac-600m-12b-1cha-dds/work_packages/1191/activity
Schematics received from Creotech, scheduled review for 10/12/2018.
Schematic Review, Agenda EDA-03010-V2-0, 14/12/2018.
Primarily this review is concerned with the differences between EDA-03010-V1-0 and EDA-03010-V2-0, and with respect to the functional issues documented above.
Overview of Review
* Background
* Global stuff
* Comments and diffs
Background to changes and aims
The aim of these changes to the schematic is to resolve four outstanding issues detailed on OHWR:
* B1: Improve testability of the DAC.
- A1: Added a U.FL connector at the DAC output (see page 4).
* B2: AD9510 requires use of external VCXO and reduces flexibility.
- A2: AD9510 + VCXO replaced with AD9516 (see page 5).
* B3: 500 MHz input impedance mismatch.
- A3: Removed R76 (see page 1).
* B4: Filter between the phase frequency detector (ADF4002) and the ADC AD7980.
- A4: New filter designed (see page 6). Voltage for AD7980 left at 2.5V, whilst filter is at 3.3V?
* B5: The FMC-DAC600m can fail to lock to the incoming RF without active cooling.
- A5: NOT ADDRESSED - TBD
General points
There's a few things that don't comply with the schematic review
checklist.
* Copyright: notice remains at 2012, should be updated to 2018?
* License: should be CERN OHL v1.2 not v1.1
* Page sizes: 1, 4 and 9 are A3, rest are A4
Comments - Page by Page
Page 1 - FMC-DDS
- RF IN change, removed R76.
- Cleaner_PLL was VXCO_PLL, now has additional PLL_RESET_N
- CleanerPLL block to FMC, new signal (see page 9) Cleaner_PLL_CLK_Sel.
- Name change: From U_Clocking to FMC_SchDoc
WAS: CLKIOUT_P, CLKIOUT_N
NOW: FMC_CLK_LA0CC_P, FMC_CLK_LA0CC_N
Page 2 - Power Supply regulators
* Name changes on the power regulators LT1763, for P2V5 and P3V3_DAC supplies
Page 3 - Trigger input
* Z50R on TRIG_I, What and Why?
Page 4 - DAC + Filter
* DAC test point added, via J11 and U.FL connector + R54
Page 5 - PLL and Clock distribution
* IC change - 9510 replaced with 9516, as detailed in B2
* name change IC26: CLK_DELAY_P/N was CLK_P/N
* name change IC26: FMC_CLK_P/N Was CLK2OUT_P/N
* CP Circuit different: Mount option removed.
* Decoupling on the P3V3_AD9516B + P3V3D line?
Page 6 - Phase Detector
* Contains redesigned filter between the ADF4002 (PFD) and the AD7980
(ADC).
* Originally components not mounted (EDA-03010-V1-0), in this redesign
they are (EDA-03010-V2-0).
* C135 Undefined 0603
* C136 Undefined 0603
Page 7 - adc page
* No change, should the ADC be operated at 3.3V or 2.5V? See B1 above.
Page 8 - VCXO & PLL, WR Clock
* No change
Page 9 - FMC connector
* Output FPGA->FMC, C14, Cleaner_PLL_CLK_Sel
* Decoupled? P12V0 and P3V3, c35+37+c39
* Additional Signal, Cleaner_PLL_CLK_Sel, see page1
* EEPROM changed from 24AA64T to M24C02
page 10 - Fine delay, output buffers
* Signal name change: Was: CLK_P/N, Now: CLK_DELAY_P/N
Action Items + Clarifications - 14/12/2018 - attendees TW, MR, DL, JS, EVB, JG
Functional issues addressed with this schematic:
* B1: U.FL looks fine - no action
* B2: Discussion about using 9516 as a PLL and CLK fanout - no action
* B3: RF Input impedance
- A3.1 - clarification required about pin 2 on the Balloon, left dangling.
* B4: Points regarding the ADC filter
- A4.1 - Undefined capacitors should have "Mounted: No", boxes.
- A4.2 - Include note that C10 should be placed ACAP to CP pin on ADF4002.
- A4.3 - P3V3_PD requires extra decoupling, with inductor (220R@100MHz) and capacitor (100nF) - like P3V3_DAC.
- A4.4 - ADC - AD7980, REF voltage should be changed to P3V3_PD with decoupling as above. We aim to have the same voltage for the filter and ADC REF voltage.
- A4.5 - Place a low-drift opamp before the ADC input, the phase detector filter has a slight high impedance output.
General issues with this schematic:
* G1: Copyright notice - every page
- A5.1 Update copyright notice to 2018
* G2: License update - every page
- A6.1 Update CERN OHL from v1.1 to v1.2
Discussion items raised in schematic review:
* D1: Temperature. FMC-DAC600M runs hot, close to 70 degrees. Consider
cooling when used with SPEC carrier, minimal airflow in some PCs.
- A7.1 Can you reccommend a solution to provide cooling?
* D2: FMC Power connections (page 9)
- A8.1 Ensure P12V0 and P3V3 on J5A, along with P3V3AUX and P3V3 on J5B are closely decoupled close to the connector.
* D3: EEPROM: (page 9) GA1 should connect to A0, GA0 should connect to A1 (Observation 5.22 ANSI/VITA 57.1 spec - CERN only), see schematic checklist.
- A9.1 Add note to explain
* D4: EEPROM: (page 9) Dangly wire, hanging from VSS to ground.
- A10.1 Please clarify this wire.
* D5: Name of design: Is this design really the second revision of this card? Discussion about whether this schematic is actually the third revision
- A11.1 Please clarify whether this schematic is EDA-03010-V2-0 or EDA-03010-V3-0.
* D6: Digital return currents:
- A12.1 Please add decoupling capacitors to prevent digital return currents on all appropriate power rails.