The cleaner PLL can be operated in two modes:

• Distribute the recovered clock from the DAC
• Multiply the recovered clock from the DAC In this second mode, when the cleaner PLL is actually using the internal VCO, the phase of the output signal wrt the input reference (from the DAC) cannot be guaranteed.

This non-deterministic phase on the AD9516 appears to be derived from the VCO divider (not channel dividers). See https://www.analog.com/media/en/technical-documentation/data-sheets/AD9516-0.pdf

Page 47, figure 57.

After SYNC goes high, it takes 14 or 15 clock cycles (post-vco divider) + 1 cycle of the VCO clock cycle (i.e. pre-vco divider).

So it's non-deterministic...

I experimented with changing the timing relationship between SYNC signal and the input reference clock. I swept through ODELAY circuits to change the timing relationship, trying to recover deterministic phase between the clock input and clock output. Unfortunately, I didn't find any delay that provided a deterministic phase.

We should consider using this PLL for future revisions of the board: https://www.analog.com/media/en/technical-documentation/data-sheets/ltc6952.pdf

I have also considered implementing a phase measuring circuit, and continually resetting the PLL until I recover an expected (golden) phase difference. However, in experimenting I have discovered that the phase difference is not sufficiently evenly distributed to guarantee that the required/golden phase difference can be obtained...

I contacted Analog Devices regarding this issue and they confirmed my findings. AD9517_4_tests_20191022.pdf