FMC DAC 600M 12b 1cha DDS issueshttps://ohwr.org/project/fmc-dac-600m-12b-1cha-dds/issues2020-03-10T09:57:17Zhttps://ohwr.org/project/fmc-dac-600m-12b-1cha-dds/issues/17Noise peak between 8-10 kHz on AD9516 system PLL2020-03-10T09:57:17ZJohn GillNoise peak between 8-10 kHz on AD9516 system PLLThe AD9516 system PLL (IC9) suffers from phase noise in the 8-10 kHz range. This noise is different on each reboot/restart of the system.
Measured using the U.FL connector (j5 or j6) and the phase noise analyser. The phase noise typically observed on the 125 MHz WR reference clock is ~2 ps RMS jitter from 10 Hz to 5 MHz. However, its performance can degrade significantly and may exhibit noise up to 10 ps RMS jitter.
To remedy this situation, it is proposed that we replace the AD9516 with an LTC6950.
It should also be noted that version 2 of this FMC-DAC-600m-12b-1cha-dds also suffered from this issue.https://ohwr.org/project/fmc-dac-600m-12b-1cha-dds/issues/16The phase difference between the output and input reference signals is non-de...2020-01-28T08:37:22ZJohn GillThe phase difference between the output and input reference signals is non-deterministic for the AD9516 (cleaner PLL)The cleaner PLL can be operated in two modes:
* Distribute the recovered clock from the DAC
* Multiply the recovered clock from the DAC
In this second mode, when the cleaner PLL is actually using the internal VCO, the phase of the output signal wrt the input reference (from the DAC) cannot be guaranteed.
This non-deterministic phase on the AD9516 appears to be derived from the VCO divider (not channel dividers). See
https://www.analog.com/media/en/technical-documentation/data-sheets/AD9516-0.pdf
Page 47, figure 57.
After SYNC goes high, it takes 14 or 15 clock cycles (post-vco divider) + 1 cycle of the VCO clock cycle (i.e. pre-vco divider).
So it's non-deterministic...
I experimented with changing the timing relationship between SYNC signal and the input reference clock. I swept through ODELAY circuits to change the timing relationship, trying to recover deterministic phase between the clock input and clock output. Unfortunately, I didn't find any delay that provided a deterministic phase.
We should consider using this PLL for future revisions of the board:
https://www.analog.com/media/en/technical-documentation/data-sheets/ltc6952.pdf
I have also considered implementing a phase measuring circuit, and continually resetting the PLL until I recover an expected (golden) phase difference. However, in experimenting I have discovered that the phase difference is not sufficiently evenly distributed to guarantee that the required/golden phase difference can be obtained...
I contacted Analog Devices regarding this issue and they confirmed my findings.
[AD9517_4_tests_20191022.pdf](/uploads/0b1d11a4d4d4a2b2747717eb75a024c8/AD9517_4_tests_20191022.pdf)John GillJohn Gillhttps://ohwr.org/project/fmc-dac-600m-12b-1cha-dds/issues/15PD filter bandwidth2019-06-11T08:44:01ZMarek GumińskiPD filter bandwidthIt seems that PD filter (C3, C8, R81, L13) bandwidth is different than stated in the note above (10 kHz).
The bandwidth of the existing filter is around 225 kHz.
Can you take a look @twlostow @jgill ?https://ohwr.org/project/fmc-dac-600m-12b-1cha-dds/issues/14Osicllations on IC30 output2019-06-11T09:02:21ZMarek GumińskiOsicllations on IC30 outputDuring the testing of FmcDac600mDDS I have found a problem with IC30 (operational amplifier).
# Description fo the problem
I connect synchronous clocks to phase detector (IC29) inputs. The phase offset between input clocks may differ. I expect to measure a constant voltage on the ADC (IC19). Voltage depends on the input clock phase offset.
It turns out that if the phase offset is "low" I measure a sine wave. Sine amplitude is around 300 mV P-P and its DC offset roughly correspond to an expected constant voltage. A sine wave is generated if DC offset is below ~2.2V. Above 2.2V the output is constant as expected. Please note that output sine frequency is different than the input sawtooth frequency.
It turns out that the problem is caused by IC30 OpAmp. It generates sine wave even though its input voltage is constant (checked with the oscilloscope) - PD filter seems to work.
I'm attaching oscillograms:
PD filter input:
![0_filter_input](/uploads/a8c35b417da3a40855c664ed145983aa/0_filter_input.png)
PD filter output:
![1_adc_input](/uploads/f21bc174fbf35c304780326d6f0f754e/1_adc_input.png)
OpAmp output:
![2_adc_output](/uploads/8a34c0ebd8de459085f53464dabbe266/2_adc_output.png)
# Temporary solution
The problem seems to be caused by OpAmp output capacitance C108. Removing it causes the oscillations to stop. I have verified that the correct capacitor was mounted on the tested boards.
Can you take a look @twlostow @jgill ?