Project Description
The B-Train integrator is a 2 differential channel 2MSPS 18 bit ADC AD7986 card in FMC (FPGA Mezzanine Card) format. it uses an LPC VITA57 connector. The gain can be set by hardware (default = 1). A gain & offset self-calibrating function is also implemented. This function use a 1ppm 20-Bit DAC AD5791 as a reference and can be also programmed as a differential voltage source. The card also include a 8 input/output LVDS pairs and a 10-bit port digital IO with each single-bit port can be configured individually as input or output. The I/Os that are on micro-HDMI connectors are TTL or LVDS compatible.
Main features
Parameter | Value |
---|---|
Max. ADC sample rate | 2MSPS |
Analog Bandwidth | 1MHz DC-Coupled |
Bits/sample | 18 bits |
DAQ channel | 2 |
Input range | +/-10V differential (completely floating) |
Input impedance | 2MOhm or 1.5GOhm hardware selectable |
Gain : | Set by hardware (one resistor) for full scale : Gain=1 (default) |
Gain & Offset self-calibration | Enabled by internal/external trigger |
DAC resolution | 20 bits |
DAC output | +/-10V differential |
Max. DAC update rate | 500KSPS |
Digital interface | TTL 10-Bit I/O and 8 LVDS I/O |
Connectors | 3 x LEMO serie B size 00 for analog signals, 2 x micro-HDMI for digital signals |
FMC to carrier interface | FMC low pin count connector |
ADC/DAC interface | Isolated SPI interface |
Clock source | Internal:from 80MHz ultra low phase noise oscillator |
CCHD-575 |
Project Documents
- Official production documentation: EDMS EDA-02512
- CERN PS Equipment name : B-Train
Releases
FMCADC2M18b2chDAC500k20b1ch
Contacts
- Giloteaux David, CERN
Status
Date | Event |
---|---|
01-01-2012 | Start working on project |
06-03-2017 | Project functional. Documentation will follow later |
6 March 2017