Clock generator SI5394A
All clocks are generated by the clock generator SI5394A from Silicon labs. The clock inputs of the device can be used for synchronization of the outputs to an external clock source. Clock synchronization is mandatory for all ADC performance tests!
The output and inputs settings of the device U5 are shown in tab. 1
Tab. 1 Clock settings of the SI5394A
| Direction | Frequency | IO Standard | Description |
|---|---|---|---|
| IN0 | 10 MHz | Single-ended 3.3 V, AC-coupled | clock input for external sync with SMA connector on frontpanel, highest priority |
| IN2 | 25 MHz | Single-ended 3.3 V, AC-coupled | clock input for external sync with SMA connector on frontpanel, highest priority |
| OUT0 | 500 MHz | LVDS 1.8 V, AC coupled | GBT clock for the FPGA transceivers |
| OUT1 | N.A. | LVDS 1.8 V, AC coupled | General purpose clock output, disabled by default |
| OUT2 | 1.0467 MHz | LVDS 1.8 V, AC coupled | SYSREF clock output for JESD204B interface, exact value: f = 500 MHz / 32 / 15 |
| OUT3 | 500 MHz | LVDS 1.8 V, AC coupled | Sampling clock for the ADC ADS54J54, output has lowest jitter |
A working configuration with the frequency settings shown in tab. 1 is already written in the non-volatile memory of the device.
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