ADC ADS54J54
The ADC ADS54J54 from Texas Instruments needs an initial configuration over SPI. Unfortunately the device has no non-volatile memory for the configuration, thus it must be reprogrammed after each power-up cycle or hardware reset. All details about device configuration can be found in the ADS54J54 datasheet sec. 7.3.11 Device configuration and in the following chapters of the datasheet.
To transfer the configuration recommended by IAM Electronic GmbH (see tab. 1), several serial register writes have to be performed. The internal register of the ADS54J54 can be programmed following these steps (rewritten from sec. 7.5.1 Serial Register Write of the ADS54J54 datasheet):
- Drive SPI_CS0 (SDENb pin of ADC) LOW
- Set the R/W bit to 0 (bit A7 of the 8 bit address).
- Initiate a serial interface cycle specifying the address of the register (A6 to A0) whose content has to be written.
- Write 16-bit data which is latched on the rising edge of SCLK.
- Drive SPI_CS0 (SDENb pin of ADC) LOW
The timing diagram of a complete write cycle is shown in fig. 1.
Figure 1: Serial register write timing of the ADC ADS54J54, copied from the ADS54J54 datasheet Table 8 and Figure 70.
Table 1: Required register write sequence for the configuration of the ADC ADS54J54. The sequence must be strictly adhered to!
| Address | Value |
|---|---|
| x00 | x8000 |
| x0D | x0000 |
| x0D | x0202 |
| x0D | x0303 |
| x01 | xAF7A |
| x02 | x0000 |
| x03 | x4040 |
| x04 | x000F |
| x05 | x0000 |
| x06 | xFFFF |
| x07 | x0144 |
| x08 | x0144 |
| x0C | x31E4 |
| x0E | x00FF |
| x0F | x0001 |
| x10 | x03E3 |
| x13 | x0020 |
| x16 | x0001 |
| x17 | x03E3 |
| x1A | x0020 |
| x1D | x0000 |
| x1E | x0000 |
| x1F | xFFFF |
| x20 | x0000 |
| x21 | x2000 |
| x44 | x0074 |
| x47 | x0074 |
| x4C | x4000 |
| x50 | x0800 |
| x51 | x0074 |
| x54 | x0074 |
| x59 | x4000 |
| x5D | x0800 |
| x0D | x0202 |
| x0D | x0303 |
| wait for two SYSREF cylces | |
| x0D | 0x0101 |
By using the configuration shown in tab. 1, the JESD204B interface is configured as follows (tab. 2):
Table 2: JESD204B configuration of the ADC ADS54J54
| no. of octets | no. of converters | no. of frames | no. of lanes | |
|---|---|---|---|---|
| CHANNEL AB | F=1 | M=2 | K=32 | L=4 |
| CHANNEL CD | F=1 | M=2 | K=32 | L=4 |
Each lane runs at: 500 MHz x 10 / 8 x16 bit x 0.5 = 5 Gb/s
The output data format is shown in fig.2 (copied from sec. 7.3.3.3 JESD204B Frame Assembly of the ADC ADS54J54 datasheet)
Figure 2: Output data format of the JESD204B interface. In total there are 8 lanes (L), 4 converters (M=4), 1 octet per frame (F=1), and 1 sample per frame (S)
Debugging JESD204B Interface
For debugging the JESD204B interface, we recommend to verify the predefined patterns of the ADC. By writing the value 0x0060 to register address x1D, the ramp pattern is enabled. A 0x1555,0x2AAA checkerboard pattern is enabled by writing the value 0x0068. ADC data is visible again by writing 0x0000 to that register address x1D.
** Related documents for the ADC ADS54J54 **