Prepare a ISE project
Dowload from Git repository
Generate wb files with wbgen2 tool (see ohwr wbgen2 project)
xserra@pc208:/project/em2/FPGA/fmc-adc-400k18b4cha/hdl/adc/wb_gen>/project/wbgen2/wbgen2 --lang=vhdl --vo=fmc_adc_18b_400ks_csr.vhd --doco=fmc_adc_18b_400ks_csr.htm ./fmc_adc_18b_400ks_csr.wb
Fetch the needed files:
xserra@pc208:~/projects> cd
~/project/em2/FPGA/fmc-adc-400k18b4cha/hdl/spec/syn/
xserra@pc208:~/project/em2/FPGA/fmc-adc-400k18b4cha/hdl/spec/syn>
hdlmake -f
INFO: Fetching needed modules.
------------------
INFO: Fetching module:
git:https://www.ohwr.org/hdl-core-lib/gn4124-core.git [parent:
/home/xserra/project/em2/FPGA/fmc-adc-400k18b4cha/hdl/spec/syn]
INFO: [git] Fetching to
/home/xserra/project/em2/FPGA/fmc-adc-400k18b4cha/hdl/ip_cores
Cloning into gn4124-core...
remote: Counting objects: 3432, done.
remote: Compressing objects: 100% (1587/1587), done.
remote: Total 3432 (delta 1850), reused 3193 (delta 1718)
Receiving objects: 100% (3432/3432), 14.49 MiB | 8.27 MiB/s, done.
Resolving deltas: 100% (1850/1850), done.
------------------
INFO: Fetching module:
git:https://www.ohwr.org/hdl-core-lib/ddr3-sp6-core.git [parent:
/home/xserra/project/em2/FPGA/fmc-adc-400k18b4cha/hdl/spec/syn]
INFO: [git] Fetching to
/home/xserra/project/em2/FPGA/fmc-adc-400k18b4cha/hdl/ip_cores
Cloning into ddr3-sp6-core...
remote: Counting objects: 1971, done.
remote: Compressing objects: 100% (654/654), done.
remote: Total 1971 (delta 1358), reused 1837 (delta 1264)
Receiving objects: 100% (1971/1971), 6.61 MiB | 2.78 MiB/s, done.
Resolving deltas: 100% (1358/1358), done.
------------------
INFO: Fetching module:
git:https://www.ohwr.org/hdl-core-lib/general-cores.git [parent:
/home/xserra/project/em2/FPGA/fmc-adc-400k18b4cha/hdl/spec/syn]
INFO: [git] Fetching to
/home/xserra/project/em2/FPGA/fmc-adc-400k18b4cha/hdl/ip_cores
Cloning into general-cores...
remote: Counting objects: 3982, done.
remote: Compressing objects: 100% (2714/2714), done.
remote: Total 3982 (delta 2514), reused 2036 (delta 1188)
Receiving objects: 100% (3982/3982), 9.81 MiB | 3.93 MiB/s, done.
Resolving deltas: 100% (2514/2514), done.
Generate ise project:
Before generating ise project, it has to be checked if the next command:
xserra@pc208:~> which xst
/homelocal/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xst
It should answer some thing like the previous example Xilinx/"version"/ISE_DS/.... .If this is the case jump to "And finally the ise project can be created:".
If not, this should be fixed. her we explain how to solve in 2 cases:
1st Your enviorement PATH variable do not include de xst path, so:
xserra@pc208:~/project/em2/FPGA/fmc-adc-400k18b4cha/hdl/spec/syn> echo
$PATH
PATH=/homelocal/sicilia/archiving/bin:/homelocal/sicilia/bin:/homelocal/sicilia/ds:/homelocal/sicilia/bin:/homelocal/sicilia/local/bin:/homelocal/sicilia/blissadm/bin:/homelocal/sicilia/blissadm/local/bin:/usr/NX/bin:/usr/lib64/mpi/gcc/openmpi/bin:/usr/local/bin:/usr/bin:/bin:/usr/bin/X11:/usr/X11R6/bin:/usr/games:/usr/lib/mit/bin:/usr/lib/mit/sbin
If they are not included, they must be be added:
xserra@pc208:~/project/em2/FPGA/fmc-adc-400k18b4cha/hdl/spec/syn>
PATH=$PATH:/homelocal/Xilinx//14.7/ISE_DS/ISE/bin/lin64/:/homelocal/Xilinx//14.7/ISE_DS/ISE/bin/lin64/
xserra@pc208:~/project/em2/FPGA/fmc-adc-400k18b4cha/hdl/spec/syn>
export PATH
xserra@pc208:~/project/em2/FPGA/fmc-adc-400k18b4cha/hdl/spec/syn> echo
$PATH
PATH=/homelocal/sicilia/archiving/bin:/homelocal/sicilia/bin:/homelocal/sicilia/ds:/homelocal/sicilia/bin:/homelocal/sicilia/local/bin:/homelocal/sicilia/blissadm/bin:/homelocal/sicilia/blissadm/local/bin:/usr/NX/bin:/usr/lib64/mpi/gcc/openmpi/bin:/usr/local/bin:/usr/bin:/bin:/usr/bin/X11:/usr/X11R6/bin:/usr/games:/usr/lib/mit/bin:/usr/lib/mit/sbin:/homelocal/Xilinx//14.7/ISE_DS/ISE/bin/lin64/:/homelocal/Xilinx//14.7/ISE_DS/ISE/bin/lin64/
A second possibility is that you are using CygWin and ISE is not installed in CygWin, what you can do is a "chapuza":
xserra@PC207 ~
$ mkdir Xilinx
xserra@PC207 ~
$ mkdir Xilinx/14.7
xserra@PC207 ~
$ mkdir Xilinx/14.7/ISE_DS
xserra@PC207 ~
$ mkdir Xilinx/14.7/ISE_DS/bin
xserra@PC207 ~
$ export PATH=$PATH:~/Xilinx/14.7/ISE_DS/ISE/bin/
xserra@PC207 ~
$ touch Xilinx/14.7/ISE_DS/ISE/bin/xst
xserra@PC207 ~
$ chmod 511 Xilinx/14.7/ISE_DS/ISE/bin/xst
Where 14.7 should be changed for the version of your ISE. Warning: Do not do this if you have installed the ISE.
Now the answer to which should be:
xserra@PC207 ~
$ which xst
/home/xserra/Xilinx/14.7/ISE_DS/ISE/bin/xst
And finally the ise project can be created:
xserra@pc208:~/project/em2/FPGA/fmc-adc-400k18b4cha/hdl/spec/syn>
hdlmake --ise-proj
INFO: Generating/updating ISE
projectbin:/usr/bin/X11:/usr/X11R6/bin:/usr/games:/usr/lib/mit/bin:/usr/lib/mit/sbin:/homelocal/Xilinx//14.7/ISE_DS/ISE/bin/lin64/:/homelocal/Xilinx//14.7/ISE_DS/ISE/bin/lin64/
My Personal setting on ISE (version 14.7):
with a mouse right botton click on the project structure, uncheck Manual
Compilation
Order.
Set the proper top module:
Do a mouse right botton click on file spec_top_fmc_18b400ks.vhd in
design tree of the project. Then click on set as Top Module, and accept
the
warning.
Set to generate bin file:
Select the top file and in the processes subwindow select Generate
Programing File. Do a mouse right botton and click on Process
Properties...
,
Then check the option -g Binary: and click OK.
Compile the project.
Select the top file and in the processes subwindow select Generate Programing File and do a double click.