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FMC ADC 400k 18b 4cha iso - Gateware
Commit 59ab53cf authored by Manuel Broseta's avatar Manuel Broseta
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adc/rtl/AD7608_CRTL.vhd 0 → 100755
View file @ 59ab53cf
----------------------------------------------------------------------------------
-- Company: ALBA-CELLS (Barcelona)
-- Engineer: Xevi Serra-Gallifa
--
-- Create Date: 09:15:19 04/19/2013
-- Design Name:
-- Module Name: AD7608_CRTL - Behavioral
-- Project Name: ALBA Electrometer 2 (Em#)
-- Target Devices: Version 2.0 modified to be used in FMC_ADC_ISO_400k_18b_4ch V2.0 connected to SPECS v4 board
-- Tool versions: ISE 14.7
-- Description:
-- 2.0 ( modification for big delays of isoltors)
--
-- The signal Trig con not be set '1' if convst(0) is '1'
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 1.0 - Developed to be use with spartan3 demo board (xc3s500e-fg320-4) with ADC7608 demo board. Release for BL22 tests 11/19/2013
-- Revision 2.0 - Modification to effort the big delays of digital isolator of FMC_ADC_ISO_400k_18b_4ch board.
-- Additional Comments:
--
-- Actual delays have to be checked with ociloscope the teoric ones works perfect, remember that data is kept with CLK-cycle delay.
-- #Remember to put the following in the constraints file to keep data integrity
-- INST "LA_N(19)" TNM = "DATA_IN"; #LA_N(19) & LA_P(19)
-- INST "LA_P(19)" TNM = "DATA_IN";
-- INST "LA_P(15)" TNM = "ADC_SCLK";
-- INST "LA_N(7)" TNM = "ADC_nCS";
-- #rising edge coment
-- TIMEGRP "DATA_IN" OFFSET = IN 30 ns VALID 30 ns BEFORE "adc_clk_in" TIMEGRP "ADC_SCLK" RISING;
-- TIMEGRP "DATA_IN" OFFSET = IN 30 ns VALID 30 ns BEFORE "adc_clk_in" TIMEGRP "ADC_nCS" FALLING;
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use ieee.std_logic_unsigned.all;
entity AD7608_CRTL is
Generic(
CLK_To_5us : INTEGER := 100; -- Tconversion/ Tclk = 5us/50ns = 100clock cycles. (20MHz clk => 50ns)
DISABLE_CLK : BOOLEAN := TRUE -- Disables Clock when is not needed. It should reduce noise.
);
Port ( n_reset : in STD_LOGIC;
clk : in STD_LOGIC;
SCLK : out STD_LOGIC;
Din : in STD_LOGIC_VECTOR (1 downto 0); --Registered input, to avoid meta-inestabilities
Trig : in STD_LOGIC; --Registered input, to avoid meta-inestabilities
n_DblRateInput: in STD_LOGIC; --Recomended to do a reset after a change
ReadInConv: in STD_LOGIC; -- becareful when 1 with n_DblRateInput --Recomended to do a reset after a change
ADC_BUSY: in STD_LOGIC;
ADC_RESET : out STD_LOGIC;
nCS : out STD_LOGIC;
CONVST: out STD_LOGIC_VECTOR ( 1 downto 0);
ADC_OUT_A : out STD_LOGIC_VECTOR (17 downto 0);
ADC_OUT_B : out STD_LOGIC_VECTOR (17 downto 0);
ADC_num : out STD_LOGIC_VECTOR (1 downto 0);
DATA_READY : out STD_LOGIC;
FSMstate : out STD_LOGIC_VECTOR ( 2 downto 0)
);
end AD7608_CRTL;
architecture Behavioral of AD7608_CRTL is
type state_type is (ADC_RST, idle, inConversion, wait_1clk_before_reading, reading);
signal state, next_state : state_type := ADC_RST;
signal counter : STD_LOGIC_VECTOR (7 downto 0):=
conv_std_logic_vector(CLK_To_5us + 1, 8);
signal en_counter : STD_LOGIC :='0';
signal bit_count : STD_LOGIC_VECTOR(4 downto 0);
signal DATA_READY_i : STD_LOGIC;
signal ADC_num_r : STD_LOGIC_VECTOR (ADC_num'range);
signal reading_end : STD_LOGIC;
signal nCS_i : STD_LOGIC;
signal Din_r : STD_LOGIC_VECTOR (1 downto 0);
signal ADC_OUT_A_t : STD_LOGIC_VECTOR (17 downto 0);
signal ADC_OUT_B_t : STD_LOGIC_VECTOR (17 downto 0);
signal FSMstate_s : STD_LOGIC_VECTOR ( 2 downto 0);
signal n_DblRateInput_r : STD_LOGIC_VECTOR ( 1 downto 0);
signal n_reset_r : STD_LOGIC_VECTOR ( 1 downto 0);
signal Trig_r : STD_LOGIC_VECTOR ( 1 downto 0);
signal ADC_BUSY_r : STD_LOGIC;
begin
nCS<= nCS_i;
DIS_CLK: if DISABLE_CLK
generate
SCLK<= clk when nCS_i= '0' else '1';
end generate DIS_CLK;
EN_CLK: if not DISABLE_CLK
generate
SCLK<= clk;
end generate EN_CLK;
procX:process(clk)
begin
if rising_edge(clk) then
n_reset_r(0) <= n_reset;
n_reset_r(1) <= n_reset_r(0);
Trig_r(0)<= trig;
Trig_r(1)<= Trig_r(0);
n_DblRateInput_r(0) <= n_DblRateInput;
n_DblRateInput_r(1) <= n_DblRateInput_r(0);
if n_reset_r(1) = '0' then
state <= ADC_RST;
Trig_r <= (others => '0');
else
state <= next_state;
ADC_BUSY_r <= ADC_BUSY;
FSMstate <= FSMstate_s;
end if;
end if;
end process;
process(state, ADC_BUSY_r, DATA_READY_i, ADC_num_r)
begin
case state is
when ADC_RST =>
-- typicaly 1 CLK is more than the 25ns necessary for a ADC reset
next_state <= idle;
ADC_RESET <= '1';
nCS_i <= '1';
FSMstate_s <="000";
when idle =>
ADC_RESET<= '0';
nCS_i<= '1';
if ADC_BUSY_r = '1' then
next_state <= inConversion;
else
next_state <= idle;
end if;
FSMstate_s <="001";
when inConversion =>
ADC_RESET<= '0';
if ADC_BUSY_r = '0' then
next_state <= wait_1clk_before_reading;
nCS_i<= '0';
else
next_state <= inConversion;
nCS_i<= '1';
end if;
FSMstate_s <="010";
when wait_1clk_before_reading => -- This is to compensate signal delay
ADC_RESET<= '0';
nCS_i<= '0';
next_state <= reading;
FSMstate_s <="011";
when reading =>
ADC_RESET<= '0';
nCS_i<= '0';
if ADC_num_r = "00" and DATA_READY_i= '1' then
next_state <= idle;
else
next_state <= reading;
end if;
FSMstate_s <="100";
when others =>
next_state <= ADC_RST;
FSMstate_s <="111";
end case;
end process;
process(clk)
begin
if rising_edge(clk) then
Din_r<= Din; --to have registered the input and avoid meta-inestabilities
if state = reading then
ADC_OUT_A_t(conv_integer(bit_count))<= Din_r(0);
ADC_OUT_B_t(conv_integer(bit_count))<= Din_r(1);
if bit_count = 0 then
bit_count<= conv_std_logic_vector(17, bit_count'LENGTH);
ADC_OUT_A<= ADC_OUT_A_t(17 downto 1) & Din_r(0); --to have registered the output and avoid meta-inestabilities
ADC_OUT_B<= ADC_OUT_B_t(17 downto 1) & Din_r(1); --to have registered the output and avoid meta-inestabilities
ADC_num<= ADC_num_r;
ADC_num_r<= ADC_num_r + 1;
DATA_READY_i <= '1';
else
DATA_READY_i <= '0';
bit_count<= bit_count - 1;
end if;
else
bit_count<= conv_std_logic_vector(17, bit_count'LENGTH);
DATA_READY_i <= '0';
ADC_num_r<= "00";
end if;
DATA_READY<= DATA_READY_i; --to have registered the output and avoid meta-inestabilities
end if;
end process;
--DATA_READY<= DATA_READY_i; -- It works, but I have doubts
--ADC_OUT_A<= ADC_OUT_A_t; -- It works, but I have doubts
--ADC_OUT_B<= ADC_OUT_B_t; -- It works, but I have doubts
process(clk) --, trig, ADC_BUSY_r
begin
if rising_edge(clk) then
if en_counter = '0' then
if Trig_r(1) = '1' then
counter <= (Others => '0');
en_counter<= '1';
CONVST(0) <= '1'; --CONVSTA
CONVST(1) <= n_DblRateInput_r(1); --CONVSTB
end if;
else
counter<= counter + 1;
if counter = conv_std_logic_vector(CLK_To_5us/2, counter'LENGTH)then
-- Tconversion/ Tclk = 5us/60ns = 83clock cycles
CONVST(0) <= '1'; --CONVSTA
CONVST(1) <= '1';
elsif counter >= conv_std_logic_vector(CLK_To_5us-1, counter'LENGTH) and
ADC_BUSY_r = '0' then
-- This should happen after 5us of start.
counter<= counter;
if (ReadInConv = '1') or (next_state = idle) then
en_counter<= '0';
CONVST(0) <= '0';
CONVST(1) <= '0';
else
CONVST(0) <= '1'; --CONVSTA
CONVST(1) <= '1'; --CONVSTB
end if;
end if;
end if;
end if;
end process;
end Behavioral;
adc/rtl/AD79X0_CRTL.vhd 0 → 100755
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--------------------------------------------------------------------------------
-- ALBA-CELLS (Computing Division, Electronics Section)
-- FMC ADC 400kSs/s core
-- http://www.ohwr.org/projects/fmc-adc-400k18b4cha
--------------------------------------------------------------------------------
--
-- unit name: AD79X0_CRTL (AD79X0_CRTL.vhd)
--
-- author: Xevi Serra-Gallifa (xserra@cells.es)
--
-- date: 07-07-2015
--
-- description: FMC ADC 400ks/s 18bits core.
--
-- dependencies:
--
-- references:
--
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see git log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
-- Additional Comments:
--------------------------------------------------------------------------------
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use ieee.std_logic_unsigned.all;
library work;
use work.utils_pkg.all;
entity AD79X0_CRTL is
Generic(
ADC_bits : INTEGER := 10; -- (AD7910 --> 10, AD7920 --> 12)
CLk_ticks_to_SPI : INTEGER := 30
);
Port ( reset : in STD_LOGIC;
clk : in STD_LOGIC;
SCLK : out STD_LOGIC;
SDATA : in STD_LOGIC; --Registered input, to avoid meta-inestabilities
nCS : out STD_LOGIC;
ADC_OUT : out STD_LOGIC_VECTOR (ADC_bits - 1 downto 0);
DATA_READY : out STD_LOGIC
);
end AD79X0_CRTL;
architecture Behavioral of AD79X0_CRTL is
constant half_CLk_ticks_int : integer := CLk_ticks_to_SPI/2;
constant half_CLk_ticks : STD_LOGIC_VECTOR := conv_std_logic_vector(half_CLk_ticks_int, log2_ceil(half_CLk_ticks_int));
--type state_type is (ADC_RST, idle, inConversion, wait_1clk_before_reading, reading);
--signal state, next_state : state_type := ADC_RST;
signal ADC_OUT_r : STD_LOGIC_VECTOR (ADC_bits - 1 downto 0);
signal counter_clk : STD_LOGIC_VECTOR (log2_ceil(half_CLk_ticks_int)-1 downto 0);
signal bits_red_cnt : STD_LOGIC_VECTOR (log2_ceil(ADC_bits + 3) downto 0);
signal Din_r : STD_LOGIC;
signal nCS_s : STD_LOGIC;
signal SCLK_s : STD_LOGIC;
begin
--SDATA <= 'Z';
nCS <= nCS_s;
SCLK <= SCLK_s;
assert CLk_ticks_to_SPI < 40
report "nCS could be smaller than 10ns hight. Please modify the code to ensure the comunication"
severity failure;
process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
DATA_READY <= '0';
nCS_s <= '1';
else
if bits_red_cnt = ADC_bits + 4 then
DATA_READY <= '1';
nCS_s <= '1';
ADC_OUT <= ADC_OUT_r; -- necessary to register again?? Maybe not!
else
DATA_READY <= '0';
nCS_s <= '0'; -- 2 clk cycles = 16ns(>10ns) it is enough in this case
end if;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if nCS_s = '1' then
counter_clk <= (others => '0');
bits_red_cnt <= (others => '0');
SCLK_s <= '1';
else
Din_r <= SDATA; --to have registered the input and avoid meta-inestabilities
if counter_clk = half_CLk_ticks then
if SCLK_s = '0' then
SCLK_s <= '1';
else
SCLK_s <= '0';
--if nCS_s = '0' then
ADC_OUT_r <= ADC_OUT_r(ADC_OUT_r'high -1 downto ADC_OUT_r'low) & Din_r;
bits_red_cnt <= bits_red_cnt + 1;
--end if;
end if;
counter_clk <= (others => '0');
else
counter_clk <= counter_clk + 1;
end if;
end if;
end if;
end process;
end Behavioral;
\ No newline at end of file
adc/rtl/FV_SIM_TB.vhd 0 → 100755
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:07:37 05/28/2015
-- Design Name:
-- Module Name: CounterNb_TB - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- To test the AD79X0_CRTL.vhd Floating voltage ADC
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.utils_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SPI_SIM2_TB is
end SPI_SIM2_TB;
architecture Behavioral of SPI_SIM2_TB is
component AD79X0_CRTL is
Generic(
ADC_bits : INTEGER := 10; -- (AD7910 --> 10, AD7920 --> 12)
CLk_ticks_to_SPI : INTEGER := 10
);
Port ( reset : in STD_LOGIC;
clk : in STD_LOGIC;
SCLK : out STD_LOGIC;
SDATA : in STD_LOGIC; --Registered input, to avoid meta-inestabilities
nCS : out STD_LOGIC;
ADC_OUT : out STD_LOGIC_VECTOR (ADC_bits - 1 downto 0);
DATA_READY : out STD_LOGIC
);
end component AD79X0_CRTL;
constant adc_t4 : time := 40 ns;
constant adc_t7 : time := 10 ns;
constant clk_period : time := 8 ns;
constant ADC_bits : integer := 10;
------------------------------SPI------------------------------
signal CLK : STD_LOGIC;
signal RESET : STD_LOGIC;
signal SPI_CLK : STD_LOGIC;
signal SDATA : STD_LOGIC; --Registered input, to avoid meta-inestabilities
signal nCS : STD_LOGIC;
signal ADC_OUT : STD_LOGIC_VECTOR (ADC_bits - 1 downto 0);
signal DATA_READY : STD_LOGIC;
------------------------------/SPI------------------------------
constant data : STD_LOGIC_VECTOR := "0000101101110111111";
signal counter: STD_LOGIC_VECTOR(log2_ceil(data'length) downto 0);
begin
COMP0 : AD79X0_CRTL
-- Generic map(
-- ADC_bits => ADC_bits, -- (AD7910 --> 10, AD7920 --> 12)
-- CLk_ticks_to_SPI => 10
-- )
Port map ( reset => RESET,
clk => CLK,
SCLK => SPI_CLK,
SDATA => SDATA,
nCS => nCS,
ADC_OUT => ADC_OUT,
DATA_READY => DATA_READY
);
-- CLOCK PROCESS
process
begin
clock_loop: loop
CLK <= '0';
wait for clk_period * 0.5;
CLK <= '1';
wait for clk_period * 0.5;
end loop clock_loop;
end process;
process(SPI_CLK,nCS)
begin
if nCS = '1' then
counter<= (others => '0');
elsif falling_edge(SPI_CLK) then
counter<= counter + 1;
end if;
end process;
process
begin
wait on SPI_CLK;
if SPI_CLK = '0' then
wait for adc_t7;
SDATA <= 'U';
wait for adc_t4 - adc_t7;
SDATA <= data(conv_integer(counter));
end if;
end process;
-- Behavioral Simulation process;
process
begin
--Initialization
RESET <='0';
--Reset
wait for 100 ns;
RESET <= '1';
wait for 50 ns;
RESET <= '0';
wait for 200000 ns;
end process;
end Behavioral;
adc/rtl/FV_control.vhd 0 → 100755
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adc/rtl/Manifest.py 0 → 100755
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files = [
"fmc_adc_mezzanine.vhd",
"fmc_adc_mezzanine_pkg.vhd",
"fmc_adc_18b_400ks_core.vhd",
"fmc_adc_18b_400ks_pkg.vhd",
"FV_control.vhd",
"AD79X0_CRTL.vhd",
"../wb_gen/fmc_adc_18b_FV_Ctrl_csr.vhd",
"../wb_gen/fmc_adc_18b_400ks_csr.vhd",
"AD7608_CRTL.vhd"]
adc/rtl/fmc_adc_18b_400ks_core.vhd 0 → 100755
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adc/rtl/fmc_adc_18b_400ks_pkg.vhd 0 → 100755
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--------------------------------------------------------------------------------
-- ALBA-CELLS (Computing Division, Electronics Section)
-- FMC ADC 400kSs/s core
-- http://www.ohwr.org/projects/fmc-adc-400k18b4cha
--------------------------------------------------------------------------------
--
-- unit name: fmc_adc_18b_400ks_pkg (fmc_adc_18b_400ks_pkg.vhd)
--
-- author: Xevi Serra-Gallifa (xserra@cells.es)
--
-- date: 07-07-2015
--
-- description: FMC FV ADC utils package.
--
-- dependencies:
--
-- references:
--
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see git log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
-- Additional Comments:
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
--=============================================================================
--! Package declaration for fmc_adc_18b_400ks_pkg
--=============================================================================
package fmc_adc_18b_400ks_pkg is
-- Constants
Constant MaxVolt : integer := 1000;
Constant MinVolt : integer := -1000;
-- Functions
function volt_to_adc(voltage : integer) return STD_LOGIC_VECTOR;
end fmc_adc_18b_400ks_pkg;
--=============================================================================
--! Body declaration for utils_pkg
--=============================================================================
package body fmc_adc_18b_400ks_pkg is
--*****************************************************************************
--! Function : Returns the STD_LOGIC_VECTOR equivalent to a given voltage
--*****************************************************************************
function volt_to_adc(voltage : integer) return STD_LOGIC_VECTOR is
constant ADC_bits : integer := 10;
variable temp3 : SIGNED(ADC_bits - 1 downto 0);
variable temp4 : STD_LOGIC_VECTOR(ADC_bits - 1 downto 0);
begin
-- return conv_std_logic_vector(1024/1001*(voltage/2.5 + 500), ADC_bits);
temp3:= to_signed((409*voltage + 511489)/1000, ADC_bits);
temp4(ADC_bits - 1 downto 0):= std_logic_vector(temp3);
return temp4;
end;
end fmc_adc_18b_400ks_pkg;
adc/rtl/fmc_adc_mezzanine.vhd 0 → 100755
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adc/rtl/fmc_adc_mezzanine_pkg.vhd 0 → 100755
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--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- FMC ADC mezzanine package
-- http://www.ohwr.org/projects/fmc-adc-100m14b4cha
--------------------------------------------------------------------------------
--
-- unit name: fmc_adc_mezzanine_pkg (fmc_adc_mezzanine_pkg.vhd)
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 03-07-2013
--
-- version: 1.0
--
-- description: Package for FMC ADC mezzanine
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see svn log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
package fmc_adc_mezzanine_pkg is
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component fmc_adc_mezzanine
generic(
g_multishot_ram_size : natural := 2048;
g_carrier_type : string := "SPEC"
);
port (
-- Clock, reset
sys_clk_i : in std_logic;
sys_rst_n_i : in std_logic;
adc_clk_i : in std_logic;
-- CSR wishbone interface
wb_csr_adr_i : in std_logic_vector(31 downto 0);
wb_csr_dat_i : in std_logic_vector(31 downto 0);
wb_csr_dat_o : out std_logic_vector(31 downto 0);
wb_csr_cyc_i : in std_logic;
wb_csr_sel_i : in std_logic_vector(3 downto 0);
wb_csr_stb_i : in std_logic;
wb_csr_we_i : in std_logic;
wb_csr_ack_o : out std_logic;
wb_csr_stall_o : out std_logic;
-- FMC interface
LA_P : inout std_logic_vector(33 downto 0);
LA_N : inout std_logic_vector(33 downto 0);
sys_scl_b : inout std_logic; -- Mezzanine system I2C clock (EEPROM)
sys_sda_b : inout std_logic -- Mezzanine system I2C data (EEPROM)
);
end component fmc_adc_mezzanine;
end fmc_adc_mezzanine_pkg;
package body fmc_adc_mezzanine_pkg is
end fmc_adc_mezzanine_pkg;
adc/wb_gen/Makefile 0 → 100755
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WBGEN2=~/projects/wbgen2/wbgen2
RTL=../rtl/
TEX=../../../documentation/manuals/firmware/
fmc_adc_18b_FV_Ctrl_csr:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
fmc_adc_18b_400ks_csr:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
adc/wb_gen/fmc_adc_18b_400ks_csr.htm 0 → 100755
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adc/wb_gen/fmc_adc_18b_400ks_csr.vhd 0 → 100755
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adc/wb_gen/fmc_adc_18b_400ks_csr.wb 0 → 100755
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peripheral {
name = "FMC ADC 18bits 400kS/s core registers";
description = "Wishbone slave for FMC ADC 18bits 400kS/s core";
hdl_entity = "fmc_adc_18b_400ks_csr";
prefix = "fmc_adc_core";
reg {
name = "Control register";
prefix = "ctl";
field {
name = "State machine commands (ignore on read)";
description = "1: ACQ_START (start acquisition, only when FSM is idle)\n2: ACQ_STOP (stop acquisition, anytime)";
prefix = "fsm_cmd";
type = SLV;
size = 2;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Range";
description = "ADC voltage range:\n0: +/-5V\n1: +/-10V (default)";
prefix = "adc_volt_rage";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Oversampling Mode";
description = "0: No oversampling\n1: 2\n2: 4\n3: 8\n4: 16\n5: 32\n6: 64\n7: Invalid";
prefix = "adc_os";
type = SLV;
size = 3;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "not Double Rate Input";
description = "Sampling of adc (use only with adc_os=0 ==> adc_dbl_rate=1)\n1: Sampling at 200kS/s\n0: Sampling at 400kS/s";
prefix = "adc_n_dbl_rate";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "adc_clk_i";
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 25;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Status register";
prefix = "sta";
field {
name = "State machine status";
description = "States:\n0: illegal\n1: IDLE\n2: PRE_TRIG\n3: WAIT_TRIG\n4: POST_TRIG\n5: TRIG_TAG\n6: DECR_SHOT\n7: illegal";
prefix = "fsm";
type = SLV;
size = 3;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "ADC State machine status";
description = "States:\n0: ADC_RST\n1: IDLE\n2: inConversion\n3: reading\n4: illegal\n5: illegal\n6: illegal\n7: illegal";
prefix = "adc_fsm";
type = SLV;
size = 3;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
clock = "adc_clk_i";
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 26;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "ADC Chanel 1";
prefix = "adc_ch1";
field {
name = "ADC Chanel1";
description = "Reading of channel 1 of 18bit ADC AD7806";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "ADC Chanel 2";
prefix = "adc_ch2";
field {
name = "ADC Chanel2";
description = "Reading of channel 1 of 18bit ADC AD7806";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "ADC Chanel 3";
prefix = "adc_ch3";
field {
name = "ADC Chanel3";
description = "Reading of channel 1 of 18bit ADC AD7806";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "ADC Chanel 4";
prefix = "adc_ch4";
field {
name = "ADC Chanel4";
description = "Reading of channel 1 of 18bit ADC AD7806";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "ADC Chanel 5";
prefix = "adc_ch5";
field {
name = "ADC Chanel5";
description = "Reading of channel 5 of 18bit ADC AD7806";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "ADC Chanel 6";
prefix = "adc_ch6";
field {
name = "ADC Chanel6";
description = "Reading of channel 6 of 18bit ADC AD7806";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "ADC Chanel 7";
prefix = "adc_ch7";
field {
name = "ADC Chanel7";
description = "Reading of channel 7 of 18bit ADC AD7806";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "ADC Chanel 8";
prefix = "adc_ch8";
field {
name = "ADC Chanel8";
description = "Reading of channel 8 of 18bit ADC AD7806";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Samples counter";
prefix = "samples_cnt";
field {
name = "Samples counter";
description = "Counts the number of samples.\n It is reset on START and then counts the number of pre-trigger + post-trigger samples";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
adc/wb_gen/fmc_adc_18b_FV_Ctrl_csr.htm 0 → 100755
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adc/wb_gen/fmc_adc_18b_FV_Ctrl_csr.vhd 0 → 100755
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---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for FMC ADC 18bits 400kS/s FV control registers
---------------------------------------------------------------------------------------
-- File : fmc_adc_18b_FV_Ctrl_csr.vhd
-- Author : auto-generated by wbgen2 from ./fmc_adc_18b_FV_Ctrl_csr.wb
-- Created : Thu Jul 30 09:32:36 2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ./fmc_adc_18b_FV_Ctrl_csr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fmc_adc_18b_FV_Ctrl_csr is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(0 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Ports for BIT field: 'FV_relay_sta' in reg: 'Control and Status'
fmc_fv_ctrl_ctrl_sta_relay_o : out std_logic;
fmc_fv_ctrl_ctrl_sta_relay_i : in std_logic;
fmc_fv_ctrl_ctrl_sta_relay_load_o : out std_logic;
-- Port for std_logic_vector field: 'FV_Led_sta' in reg: 'Control and Status'
fmc_fv_ctrl_ctrl_sta_led_i : in std_logic_vector(2 downto 0);
-- Port for std_logic_vector field: 'Reading_mode' in reg: 'Control and Status'
fmc_fv_ctrl_ctrl_sta_read_mode_o : out std_logic_vector(1 downto 0);
-- Port for BIT field: 'Spare Led' in reg: 'Control and Status'
fmc_fv_ctrl_ctrl_sta_sp1_o : out std_logic;
-- Port for std_logic_vector field: 'Floating ground Voltage' in reg: 'Control and Status'
fmc_fv_ctrl_ctrl_sta_fv_i : in std_logic_vector(9 downto 0);
-- Port for std_logic_vector field: 'Maximum Voltage' in reg: 'range of voltage voltages'
fmc_fv_ctrl_lim_max_o : out std_logic_vector(9 downto 0);
fmc_fv_ctrl_lim_max_i : in std_logic_vector(9 downto 0);
fmc_fv_ctrl_lim_max_load_o : out std_logic;
-- Port for std_logic_vector field: 'Minimum voltage' in reg: 'range of voltage voltages'
fmc_fv_ctrl_lim_min_o : out std_logic_vector(9 downto 0);
fmc_fv_ctrl_lim_min_i : in std_logic_vector(9 downto 0);
fmc_fv_ctrl_lim_min_load_o : out std_logic
);
end fmc_adc_18b_FV_Ctrl_csr;
architecture syn of fmc_adc_18b_FV_Ctrl_csr is
signal fmc_fv_ctrl_ctrl_sta_read_mode_int : std_logic_vector(1 downto 0);
signal fmc_fv_ctrl_ctrl_sta_sp1_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(0 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
fmc_fv_ctrl_ctrl_sta_relay_load_o <= '0';
fmc_fv_ctrl_ctrl_sta_read_mode_int <= "00";
fmc_fv_ctrl_ctrl_sta_sp1_int <= '0';
fmc_fv_ctrl_lim_max_load_o <= '0';
fmc_fv_ctrl_lim_min_load_o <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
fmc_fv_ctrl_ctrl_sta_relay_load_o <= '0';
fmc_fv_ctrl_lim_max_load_o <= '0';
fmc_fv_ctrl_lim_min_load_o <= '0';
ack_in_progress <= '0';
else
fmc_fv_ctrl_ctrl_sta_relay_load_o <= '0';
fmc_fv_ctrl_lim_max_load_o <= '0';
fmc_fv_ctrl_lim_min_load_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(0) is
when '0' =>
if (wb_we_i = '1') then
fmc_fv_ctrl_ctrl_sta_relay_load_o <= '1';
fmc_fv_ctrl_ctrl_sta_read_mode_int <= wrdata_reg(5 downto 4);
fmc_fv_ctrl_ctrl_sta_sp1_int <= wrdata_reg(6);
end if;
rddata_reg(0) <= fmc_fv_ctrl_ctrl_sta_relay_i;
rddata_reg(3 downto 1) <= fmc_fv_ctrl_ctrl_sta_led_i;
rddata_reg(5 downto 4) <= fmc_fv_ctrl_ctrl_sta_read_mode_int;
rddata_reg(6) <= fmc_fv_ctrl_ctrl_sta_sp1_int;
rddata_reg(25 downto 16) <= fmc_fv_ctrl_ctrl_sta_fv_i;
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when '1' =>
if (wb_we_i = '1') then
fmc_fv_ctrl_lim_max_load_o <= '1';
fmc_fv_ctrl_lim_min_load_o <= '1';
end if;
rddata_reg(9 downto 0) <= fmc_fv_ctrl_lim_max_i;
rddata_reg(25 downto 16) <= fmc_fv_ctrl_lim_min_i;
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- FV_relay_sta
fmc_fv_ctrl_ctrl_sta_relay_o <= wrdata_reg(0);
-- FV_Led_sta
-- Reading_mode
fmc_fv_ctrl_ctrl_sta_read_mode_o <= fmc_fv_ctrl_ctrl_sta_read_mode_int;
-- Spare Led
fmc_fv_ctrl_ctrl_sta_sp1_o <= fmc_fv_ctrl_ctrl_sta_sp1_int;
-- Floating ground Voltage
-- Maximum Voltage
fmc_fv_ctrl_lim_max_o <= wrdata_reg(9 downto 0);
-- Minimum voltage
fmc_fv_ctrl_lim_min_o <= wrdata_reg(25 downto 16);
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
adc/wb_gen/fmc_adc_18b_FV_Ctrl_csr.wb 0 → 100755
View file @ 59ab53cf
peripheral {
name = "FMC ADC 18bits 400kS/s FV control registers";
description = "Wishbone slave for FMC ADC 18bits 400kS/s FV control registers";
hdl_entity = "fmc_adc_18b_FV_Ctrl_csr";
prefix = "fmc_FV_Ctrl";
reg {
name = "Control and Status";
prefix = "ctrl_sta";
field {
name = "FV_relay_sta";
description = "On reading the state of the FV relay. 1 - FV on.\n On write changes the state of FV relay if FV Voltage is in the correct range.";
prefix = "relay";
type = BIT;
size = 1;
load= LOAD_EXT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
field {
name = "FV_Led_sta";
description = "The state of FV_led 0 means Led is off.";
prefix = "led";
type = SLV;
size = 3;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Reading_mode";
description = "The Reading mode of Floating voltage.\n 1. Reading of instantaneus voltage.\n 2. Reading of minimum voltage since last reading.\n 3. Reading of minimum voltage since last reading.\n 4. Reading of average voltage of 256 samples.";
prefix = "Read_mode";
type = SLV;
size = 2;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Spare Led";
description = "Sets or gets the spare led. 1 -> Led on";
prefix = "SP1";
type = BIT;
size = 1;
load= LOAD_EXT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Floating ground Voltage";
description = "The floating voltage is: 2.5*(1001*FV/1024 - 500) ";
prefix = "FV";
type = SLV;
size = 10;
align = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "range of voltage voltages";
prefix = "lim";
field {
name = "Maximum Voltage";
description = "The maximum voltage before switching off the FV_Relay signal\n The voltage follows the following formula V=2.5*(1001*Max/1024 - 500)";
prefix = "Max";
type = SLV;
size = 10;
align = 16;
load= LOAD_EXT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
field {
name = "Minimum voltage";
description = "The minimum voltage before switching off the FV_Relay signal\n The voltage follows the following formula V=2.5*(1001*Min/1024 - 500)";
prefix = "Min";
type = SLV;
size = 10;
align = 16;
load= LOAD_EXT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
};
};
ip_cores/multishot_dpram.ngc 0 → 100755
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ip_cores/utils/utils_pkg.vhd 0 → 100755
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--=============================================================================
-- @file utils_pkg.vhd
--=============================================================================
--! Standard library
library IEEE;
--library unisim;
--! Standard packages
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
--use unisim.vcomponents.all;
--! Specific packages
-------------------------------------------------------------------------------
-- --
-- CERN, BE-CO-HT,
-- --
-------------------------------------------------------------------------------
--
-- Unit name:
--
--! @brief
--!
--
--! @author Matthieu Cattin (matthieu dot cattin at cern dot ch)
--
--! @date 22\10\2009
--
--! @version v.0.1
--
--! @details
--!
--! <b>Dependencies:</b>\n
--! None
--!
--! <b>References:</b>\n
--!
--!
--! <b>Modified by:</b>\n
--! Author:
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
--! 22.10.2009 mcattin Creation
--! 07.03.2011 mcattin Fix bug in log2_ceil function
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
--! @todo
--
-------------------------------------------------------------------------------
--=============================================================================
--! Package declaration for utils_pkg
--=============================================================================
package utils_pkg is
-- Functions
function log2_ceil(N : natural) return positive;
end utils_pkg;
--=============================================================================
--! Body declaration for utils_pkg
--=============================================================================
package body utils_pkg is
--*****************************************************************************
--! Function : Returns log of 2 of a natural number
--*****************************************************************************
function log2_ceil(N : natural) return positive is
begin
if N <= 2 then
return 1;
elsif N mod 2 = 0 then
return 1 + log2_ceil(N/2);
else
return 1 + log2_ceil((N+1)/2);
end if;
end;
end utils_pkg;
ip_cores/wb_ddr_fifo.ngc 0 → 100755
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spec/rtl/Manifest.py 0 → 100755
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files = [
"spec_top_fmc_adc_400k18b4cha_iso.vhd",
"carrier_csr.vhd",
"dma_eic.vhd",
"sdb_meta_pkg.vhd"]
spec/rtl/carrier_csr.vhd 0 → 100755
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---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Carrier control and status registers
---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Tue Jan 14 11:45:49 2014
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity carrier_csr is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'PCB revision' in reg: 'Carrier type and PCB version'
carrier_csr_carrier_pcb_rev_i : in std_logic_vector(3 downto 0);
-- Port for std_logic_vector field: 'Reserved register' in reg: 'Carrier type and PCB version'
carrier_csr_carrier_reserved_i : in std_logic_vector(11 downto 0);
-- Port for std_logic_vector field: 'Carrier type' in reg: 'Carrier type and PCB version'
carrier_csr_carrier_type_i : in std_logic_vector(15 downto 0);
-- Port for BIT field: 'FMC presence' in reg: 'Status'
carrier_csr_stat_fmc_pres_i : in std_logic;
-- Port for BIT field: 'GN4142 core P2L PLL status' in reg: 'Status'
carrier_csr_stat_p2l_pll_lck_i : in std_logic;
-- Port for BIT field: 'System clock PLL status' in reg: 'Status'
carrier_csr_stat_sys_pll_lck_i : in std_logic;
-- Port for BIT field: 'DDR3 calibration status' in reg: 'Status'
carrier_csr_stat_ddr3_cal_done_i : in std_logic;
-- Port for std_logic_vector field: 'Reserved' in reg: 'Status'
carrier_csr_stat_reserved_i : in std_logic_vector(27 downto 0);
-- Port for BIT field: 'Green LED' in reg: 'Control'
carrier_csr_ctrl_led_green_o : out std_logic;
-- Port for BIT field: 'Red LED' in reg: 'Control'
carrier_csr_ctrl_led_red_o : out std_logic;
-- Port for BIT field: 'DAC clear' in reg: 'Control'
carrier_csr_ctrl_dac_clr_n_o : out std_logic;
-- Port for std_logic_vector field: 'Reserved' in reg: 'Control'
carrier_csr_ctrl_reserved_o : out std_logic_vector(28 downto 0);
-- Ports for BIT field: 'State of the reset line' in reg: 'Reset Register'
carrier_csr_rst_fmc0_n_o : out std_logic;
carrier_csr_rst_fmc0_n_i : in std_logic;
carrier_csr_rst_fmc0_n_load_o : out std_logic;
-- Port for std_logic_vector field: 'Reserved' in reg: 'Reset Register'
carrier_csr_rst_reserved_o : out std_logic_vector(30 downto 0)
);
end carrier_csr;
architecture syn of carrier_csr is
signal carrier_csr_ctrl_led_green_int : std_logic ;
signal carrier_csr_ctrl_led_red_int : std_logic ;
signal carrier_csr_ctrl_dac_clr_n_int : std_logic ;
signal carrier_csr_ctrl_reserved_int : std_logic_vector(28 downto 0);
signal carrier_csr_rst_reserved_int : std_logic_vector(30 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
carrier_csr_ctrl_led_green_int <= '0';
carrier_csr_ctrl_led_red_int <= '0';
carrier_csr_ctrl_dac_clr_n_int <= '0';
carrier_csr_ctrl_reserved_int <= "00000000000000000000000000000";
carrier_csr_rst_fmc0_n_load_o <= '0';
carrier_csr_rst_reserved_int <= "0000000000000000000000000000000";
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
carrier_csr_rst_fmc0_n_load_o <= '0';
ack_in_progress <= '0';
else
carrier_csr_rst_fmc0_n_load_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
end if;
rddata_reg(3 downto 0) <= carrier_csr_carrier_pcb_rev_i;
rddata_reg(15 downto 4) <= carrier_csr_carrier_reserved_i;
rddata_reg(31 downto 16) <= carrier_csr_carrier_type_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= carrier_csr_stat_fmc_pres_i;
rddata_reg(1) <= carrier_csr_stat_p2l_pll_lck_i;
rddata_reg(2) <= carrier_csr_stat_sys_pll_lck_i;
rddata_reg(3) <= carrier_csr_stat_ddr3_cal_done_i;
rddata_reg(31 downto 4) <= carrier_csr_stat_reserved_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
carrier_csr_ctrl_led_green_int <= wrdata_reg(0);
carrier_csr_ctrl_led_red_int <= wrdata_reg(1);
carrier_csr_ctrl_dac_clr_n_int <= wrdata_reg(2);
carrier_csr_ctrl_reserved_int <= wrdata_reg(31 downto 3);
end if;
rddata_reg(0) <= carrier_csr_ctrl_led_green_int;
rddata_reg(1) <= carrier_csr_ctrl_led_red_int;
rddata_reg(2) <= carrier_csr_ctrl_dac_clr_n_int;
rddata_reg(31 downto 3) <= carrier_csr_ctrl_reserved_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11" =>
if (wb_we_i = '1') then
carrier_csr_rst_fmc0_n_load_o <= '1';
carrier_csr_rst_reserved_int <= wrdata_reg(31 downto 1);
end if;
rddata_reg(0) <= carrier_csr_rst_fmc0_n_i;
rddata_reg(31 downto 1) <= carrier_csr_rst_reserved_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- PCB revision
-- Reserved register
-- Carrier type
-- FMC presence
-- GN4142 core P2L PLL status
-- System clock PLL status
-- DDR3 calibration status
-- Reserved
-- Green LED
carrier_csr_ctrl_led_green_o <= carrier_csr_ctrl_led_green_int;
-- Red LED
carrier_csr_ctrl_led_red_o <= carrier_csr_ctrl_led_red_int;
-- DAC clear
carrier_csr_ctrl_dac_clr_n_o <= carrier_csr_ctrl_dac_clr_n_int;
-- Reserved
carrier_csr_ctrl_reserved_o <= carrier_csr_ctrl_reserved_int;
-- State of the reset line
carrier_csr_rst_fmc0_n_o <= wrdata_reg(0);
-- Reserved
carrier_csr_rst_reserved_o <= carrier_csr_rst_reserved_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
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spec/rtl/sdb_meta_pkg.vhd 0 → 100755
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--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- FMC ADC 400ks/s 18bits core
-- http://www.ohwr.org/projects/fmc-adc-400k18b4cha
--------------------------------------------------------------------------------
--
-- unit name: sdb_meta_pkg (sdb_meta_pkg.vhd)
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
-- Modified by: Xevi Serra (xserra@cells.es)
--
-- date: 11-03-2013
--
-- description: Sdb meta-information for the FMC ADC 400ks/s 18b design for SPEC.
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see git log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
package sdb_meta_pkg is
------------------------------------------------------------------------------
-- Meta-information sdb records
------------------------------------------------------------------------------
-- Top module repository url
constant c_repo_url_sdb : t_sdb_repo_url := (
-- url (string, 63 char)
repo_url => "https://gitcomputing.cells.es/electronics/em2.git ");
-- Synthesis informations
constant c_synthesis_sdb : t_sdb_synthesis := (
-- Top module name (string, 16 char)
syn_module_name => "spec_top_fmc_adc",
-- Commit ID (hex string, 128-bit = 32 char)
-- git log -1 --format="%H" | cut -c1-32
syn_commit_id => "697546304b7a1890aba8d6effd935a0f",
-- Synthesis tool name (string, 8 char)
syn_tool_name => "ISE ",
-- Synthesis tool version (bcd encoded, 32-bit)
syn_tool_version => x"00000133",
-- Synthesis date (bcd encoded, 32-bit, yyyymmdd)
syn_date => x"20150714",
-- Synthesised by (string, 15 char)
syn_username => "xserra ");
-- Integration record
constant c_integration_sdb : t_sdb_integration := (
product => (
vendor_id => x"000000000000a1ba", -- CERN
device_id => x"f0884024", -- echo "spec_fmc-adc-400k18b4cha" | md5sum | cut -c1-8
version => x"00030000", -- bcd encoded, [31:16] = major, [15:0] = minor
date => x"20140116", -- yyyymmdd
name => "spec_fmcadc400k18b "));
end sdb_meta_pkg;
package body sdb_meta_pkg is
end sdb_meta_pkg;
spec/rtl/spec_top_fmc_adc_400k18b4cha_iso.vhd 0 → 100755
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spec/syn/Manifest.py 0 → 100755
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target = "xilinx"
action = "synthesis"
syn_device = "xc6slx100t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "spec_top_fmc_adc_400k18b4cha_iso"
syn_project = "spec_fmc_adc_400k18b4cha_iso.xise"
files = [
"../spec_top_fmc_adc_400k18b4cha_iso.ucf",
"../../ip_cores/multishot_dpram.ngc",
"../../ip_cores/wb_ddr_fifo.ngc",
"../../ip_cores/utils/utils_pkg.vhd"]
modules = { "local" : ["../rtl",
"../../adc/rtl"],
"git" : ["git://ohwr.org/hdl-core-lib/general-cores.git::proposed_master",
"git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git::spec_bank3_64b_32b",
"git://ohwr.org/hdl-core-lib/gn4124-core.git::master"]}
fetchto="../../ip_cores"
spec/wb_gen/Makefile 0 → 100755
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WBGEN2=~/projects/wbgen2/wbgen2
RTL=../rtl/
TEX=../../../documentation/manuals/firmware/spec/
carrier_csr:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
dma_eic:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
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spec/wb_gen/dma_eic.wb 0 → 100755
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peripheral {
name = "GN4124 DMA enhanced interrupt controller";
description = "Enhanced interrrupt controller for GN4124 DMA.";
hdl_entity = "dma_eic";
prefix = "dma_eic";
irq {
name = "DMA done interrupt";
description = "DMA done interrupt line (rising edge sensitive).";
prefix = "dma_done";
trigger = EDGE_RISING;
};
irq {
name = "DMA error interrupt";
description = "DMA error interrupt line (rising edge sensitive).";
prefix = "dma_error";
trigger = EDGE_RISING;
};
};
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