fmc_adc_18b_400ks_csr

FMC ADC 18bits 400kS/s core registers

Wishbone slave for FMC ADC 18bits 400kS/s core

1. Memory map summary

H/W Address	Type	Name	VHDL/Verilog prefix	C prefix
0x0	REG	Control register	fmc_adc_core_ctl	CTL
0x1	REG	Status register	fmc_adc_core_sta	STA
0x2	REG	ADC Chanel 1	fmc_adc_core_adc_ch1	ADC_CH1
0x3	REG	ADC Chanel 2	fmc_adc_core_adc_ch2	ADC_CH2
0x4	REG	ADC Chanel 3	fmc_adc_core_adc_ch3	ADC_CH3
0x5	REG	ADC Chanel 4	fmc_adc_core_adc_ch4	ADC_CH4
0x6	REG	ADC Chanel 5	fmc_adc_core_adc_ch5	ADC_CH5
0x7	REG	ADC Chanel 6	fmc_adc_core_adc_ch6	ADC_CH6
0x8	REG	ADC Chanel 7	fmc_adc_core_adc_ch7	ADC_CH7
0x9	REG	ADC Chanel 8	fmc_adc_core_adc_ch8	ADC_CH8
0xa	REG	Samples counter	fmc_adc_core_samples_cnt	SAMPLES_CNT

2. HDL symbol

→	rst_n_i	Control register:
→	clk_sys_i	fmc_adc_core_ctl_fsm_cmd_o[1:0]	⇒
⇒	wb_adr_i[3:0]	fmc_adc_core_ctl_adc_volt_rage_o	→
⇒	wb_dat_i[31:0]	fmc_adc_core_ctl_adc_os_o[2:0]	⇒
⇐	wb_dat_o[31:0]	fmc_adc_core_ctl_adc_n_dbl_rate_o	→
→	wb_cyc_i	fmc_adc_core_ctl_reserved_i[24:0]	⇐
⇒	wb_sel_i[3:0]
→	wb_stb_i	Status register:
→	wb_we_i	fmc_adc_core_sta_fsm_i[2:0]	⇐
←	wb_ack_o	fmc_adc_core_sta_adc_fsm_i[2:0]	⇐
←	wb_stall_o	fmc_adc_core_sta_reserved_i[25:0]	⇐

		ADC Chanel 1:
		fmc_adc_core_adc_ch1_i[31:0]	⇐

		ADC Chanel 2:
		fmc_adc_core_adc_ch2_i[31:0]	⇐

		ADC Chanel 3:
		fmc_adc_core_adc_ch3_i[31:0]	⇐

		ADC Chanel 4:
		fmc_adc_core_adc_ch4_i[31:0]	⇐

		ADC Chanel 5:
		fmc_adc_core_adc_ch5_i[31:0]	⇐

		ADC Chanel 6:
		fmc_adc_core_adc_ch6_i[31:0]	⇐

		ADC Chanel 7:
		fmc_adc_core_adc_ch7_i[31:0]	⇐

		ADC Chanel 8:
		fmc_adc_core_adc_ch8_i[31:0]	⇐

		Samples counter:
		fmc_adc_core_samples_cnt_i[31:0]	⇐

3. Register description

3.1. Control register

HW prefix:	fmc_adc_core_ctl
HW address:	0x0
C prefix:	CTL
C offset:	0x0

31	30	29	28	27	26	25	24
RESERVED[24:17]

23	22	21	20	19	18	17	16
RESERVED[16:9]

15	14	13	12	11	10	9	8
RESERVED[8:1]

7	6	5	4	3	2	1	0
RESERVED[0:0]	ADC_N_DBL_RATE	ADC_OS[2:0]			ADC_VOLT_RAGE	FSM_CMD[1:0]

FSM_CMD [read/write]: State machine commands (ignore on read)
1: ACQ_START (start acquisition, only when FSM is idle)
2: ACQ_STOP (stop acquisition, anytime)
ADC_VOLT_RAGE [read/write]: Range
ADC voltage range:
0: +/-5V
1: +/-10V (default)
ADC_OS [read/write]: Oversampling Mode
0: No oversampling
1: 2
2: 4
3: 8
4: 16
5: 32
6: 64
7: Invalid
ADC_N_DBL_RATE [read/write]: not Double Rate Input
Sampling of adc (use only with adc_os=0 ==> adc_dbl_rate=1)
1: Sampling at 200kS/s
0: Sampling at 400kS/s
RESERVED [read-only]: Reserved
Ignore on read, write with 0's

3.2. Status register

HW prefix:	fmc_adc_core_sta
HW address:	0x1
C prefix:	STA
C offset:	0x4

31	30	29	28	27	26	25	24
RESERVED[25:18]

23	22	21	20	19	18	17	16
RESERVED[17:10]

15	14	13	12	11	10	9	8
RESERVED[9:2]

7	6	5	4	3	2	1	0
RESERVED[1:0]		ADC_FSM[2:0]			FSM[2:0]

FSM [read-only]: State machine status
States:
0: illegal
1: IDLE
2: PRE_TRIG
3: WAIT_TRIG
4: POST_TRIG
5: TRIG_TAG
6: DECR_SHOT
7: illegal
ADC_FSM [read-only]: ADC State machine status
States:
0: ADC_RST
1: IDLE
2: inConversion
3: reading
4: illegal
5: illegal
6: illegal
7: illegal
RESERVED [read-only]: Reserved
Ignore on read, write with 0's

3.3. ADC Chanel 1

HW prefix:	fmc_adc_core_adc_ch1
HW address:	0x2
C prefix:	ADC_CH1
C offset:	0x8

31	30	29	28	27	26	25	24
ADC_CH1[31:24]

23	22	21	20	19	18	17	16
ADC_CH1[23:16]

15	14	13	12	11	10	9	8
ADC_CH1[15:8]

7	6	5	4	3	2	1	0
ADC_CH1[7:0]

ADC_CH1 [read-only]: ADC Chanel1
Reading of channel 1 of 18bit ADC AD7806

3.4. ADC Chanel 2

HW prefix:	fmc_adc_core_adc_ch2
HW address:	0x3
C prefix:	ADC_CH2
C offset:	0xc

31	30	29	28	27	26	25	24
ADC_CH2[31:24]

23	22	21	20	19	18	17	16
ADC_CH2[23:16]

15	14	13	12	11	10	9	8
ADC_CH2[15:8]

7	6	5	4	3	2	1	0
ADC_CH2[7:0]

ADC_CH2 [read-only]: ADC Chanel2
Reading of channel 1 of 18bit ADC AD7806

3.5. ADC Chanel 3

HW prefix:	fmc_adc_core_adc_ch3
HW address:	0x4
C prefix:	ADC_CH3
C offset:	0x10

31	30	29	28	27	26	25	24
ADC_CH3[31:24]

23	22	21	20	19	18	17	16
ADC_CH3[23:16]

15	14	13	12	11	10	9	8
ADC_CH3[15:8]

7	6	5	4	3	2	1	0
ADC_CH3[7:0]

ADC_CH3 [read-only]: ADC Chanel3
Reading of channel 1 of 18bit ADC AD7806

3.6. ADC Chanel 4

HW prefix:	fmc_adc_core_adc_ch4
HW address:	0x5
C prefix:	ADC_CH4
C offset:	0x14

31	30	29	28	27	26	25	24
ADC_CH4[31:24]

23	22	21	20	19	18	17	16
ADC_CH4[23:16]

15	14	13	12	11	10	9	8
ADC_CH4[15:8]

7	6	5	4	3	2	1	0
ADC_CH4[7:0]

ADC_CH4 [read-only]: ADC Chanel4
Reading of channel 1 of 18bit ADC AD7806

3.7. ADC Chanel 5

HW prefix:	fmc_adc_core_adc_ch5
HW address:	0x6
C prefix:	ADC_CH5
C offset:	0x18

31	30	29	28	27	26	25	24
ADC_CH5[31:24]

23	22	21	20	19	18	17	16
ADC_CH5[23:16]

15	14	13	12	11	10	9	8
ADC_CH5[15:8]

7	6	5	4	3	2	1	0
ADC_CH5[7:0]

ADC_CH5 [read-only]: ADC Chanel5
Reading of channel 5 of 18bit ADC AD7806

3.8. ADC Chanel 6

HW prefix:	fmc_adc_core_adc_ch6
HW address:	0x7
C prefix:	ADC_CH6
C offset:	0x1c

31	30	29	28	27	26	25	24
ADC_CH6[31:24]

23	22	21	20	19	18	17	16
ADC_CH6[23:16]

15	14	13	12	11	10	9	8
ADC_CH6[15:8]

7	6	5	4	3	2	1	0
ADC_CH6[7:0]

ADC_CH6 [read-only]: ADC Chanel6
Reading of channel 6 of 18bit ADC AD7806

3.9. ADC Chanel 7

HW prefix:	fmc_adc_core_adc_ch7
HW address:	0x8
C prefix:	ADC_CH7
C offset:	0x20

31	30	29	28	27	26	25	24
ADC_CH7[31:24]

23	22	21	20	19	18	17	16
ADC_CH7[23:16]

15	14	13	12	11	10	9	8
ADC_CH7[15:8]

7	6	5	4	3	2	1	0
ADC_CH7[7:0]

ADC_CH7 [read-only]: ADC Chanel7
Reading of channel 7 of 18bit ADC AD7806

3.10. ADC Chanel 8

HW prefix:	fmc_adc_core_adc_ch8
HW address:	0x9
C prefix:	ADC_CH8
C offset:	0x24

31	30	29	28	27	26	25	24
ADC_CH8[31:24]

23	22	21	20	19	18	17	16
ADC_CH8[23:16]

15	14	13	12	11	10	9	8
ADC_CH8[15:8]

7	6	5	4	3	2	1	0
ADC_CH8[7:0]

ADC_CH8 [read-only]: ADC Chanel8
Reading of channel 8 of 18bit ADC AD7806

3.11. Samples counter

HW prefix:	fmc_adc_core_samples_cnt
HW address:	0xa
C prefix:	SAMPLES_CNT
C offset:	0x28

31	30	29	28	27	26	25	24
SAMPLES_CNT[31:24]

23	22	21	20	19	18	17	16
SAMPLES_CNT[23:16]

15	14	13	12	11	10	9	8
SAMPLES_CNT[15:8]

7	6	5	4	3	2	1	0
SAMPLES_CNT[7:0]

SAMPLES_CNT [read-only]: Samples counter
Counts the number of samples.
It is reset on START and then counts the number of pre-trigger + post-trigger samples

fmc_adc_18b_400ks_csr

FMC ADC 18bits 400kS/s core registers

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