Frequently Asked Questions
about the FMC ADC 1G 8b 2cha.
Hardware
Q: What's the allowed Vadj and with which carriers will it work?
A: Vadj can be 1.8V, 2.5V or 3.3V
A clarification about the FMC ADC 1G FMC VADJ compatibility:
- The ADC digital supply is 1.80V from an on board DCDC, powered from the FMC 3V3 supply. The ADC itself supports a digital supply from 1.70 to 2.00V, but the local 1.80V supply makes this range irrelevant external to the FM582.
- The ADC digital data outputs are strictly compliant to LVDS signalling levels, with 1.20V common mode.
- The FMC VADJ is used by FMC ADC 1G to define the LVCMOS signalling levels in 2 ways: It supplies the ADC pin 0VDD, which has a range of 1.7V to 3.6V, and sets the signalling levels for the ADC SPI bus, which is directly connected to the FMC with NO voltage translation. It supplies the other LVCMOS voltage translators, which convert ALL the other SPI bus signals from the FMC to 3.3V for use internally. These translators support a VADJ supply range of 1.65V to 5.5V.
To summarise:
- The ADC constrains the VADJ range to 1.70V - 3.60V, and this is the signalling level for all LVCMOS signals.
- The ADC LVDS outputs are independent of VADJ, and have 1.20V common mode at all times.
Implications for the carrier card: Xilinx FPGAs are usually forced to have a 1.80V supply to banks which have LVDS signalling. The Xilinx FPGA can have an entire bank connected to the FMC bus, so this bank has to support both LVDS and LVCMOS. This means the LVCMOS signalling level is also constrained to operate from 1.80V.
The FMC standard AV57DOT1-2019.pdf states the following:
"Rule 5.121: User defined signals on Bank A shall use the VADJ voltage as the IO power voltage."
Table 13 in this FMC standard defines the VADJ voltage for each of the different LVCMOS signalling standards.
- With VADJ 1.80V, standard is LVCMOS18
- With VADJ 2.50V, standard is LVCMOS25
- With VADJ 3.30V, standard is LVCMOS33
It also specifies LVDS signals should use a VADJ of 2.50V, however this is a problem for modern Xilinx FPGAs, not the FMC ADC 1G.
The FMC ADC 1G will support all of the following VADJ settings on the carrier, and anything in between:
Carrier Vadj | Signalling standard | LVDS from the ADC - common mode |
---|---|---|
1.80V | LVCMOS18 | 1.20V |
2.50V | LVCMOS25 | 1.20V |
3.30V | LVCMOS33 | 1.20V |
(SC, Sundance, 21/1/22)
21 January 2022