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FMC ADC 1G 8b 2cha
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FMC ADC 1G 8b 2cha
Issues
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33
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36
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V1: Silkscreen: no link to ohwr project
#36
· opened
Dec 13, 2021
by
Erik van der Bij
0
updated
Dec 13, 2021
Double-check intent of PIN diode circuit in the AC atenuator
#35
· opened
Apr 14, 2021
by
Christos Gentsos
Layout V1 done
layout-1
CLOSED
4
updated
Apr 19, 2021
IC10_Attenuator DC2: GND vias missing for 2 pads
#34
· opened
Apr 13, 2021
by
Christos Gentsos
Layout V1 done
layout-1
0
updated
Apr 13, 2021
IC36: 3V3P via not connected properly to pad
#33
· opened
Apr 13, 2021
by
Christos Gentsos
Layout V1 done
layout-1
1
updated
Apr 13, 2021
IC29, IC48: Add GND vias, move decoupling caps a bit closer
#32
· opened
Apr 13, 2021
by
Christos Gentsos
Layout V1 done
layout-1
0
updated
Apr 13, 2021
IC44: 100n decoupling cap is placed further from the 4.7u
#31
· opened
Apr 13, 2021
by
Christos Gentsos
Layout V1 done
layout-1
0
updated
Apr 13, 2021
Add return vias in reference plane changes
#30
· opened
Apr 13, 2021
by
Christos Gentsos
Layout V1 done
layout-1
0
updated
Apr 13, 2021
Layout (cosmetics)
#29
· opened
Mar 29, 2021
by
Tomasz Wlostowski
Layout V1 done
layout-1
0
updated
Mar 29, 2021
OSC1 frequency stability/tuning range
#28
· opened
Sep 23, 2020
by
Tomasz Wlostowski
Schematic done
hw
important
3
updated
Oct 15, 2020
Optimize clock distribution
#27
· opened
Sep 23, 2020
by
Tomasz Wlostowski
Schematic done
hw
important
question
8
updated
Oct 15, 2020
WR DAC reference voltage
#26
· opened
Sep 23, 2020
by
Tomasz Wlostowski
Schematic done
hw
important
1
updated
Oct 08, 2020
Trigger comparator hysteresis
#25
· opened
Sep 23, 2020
by
Tomasz Wlostowski
Schematic done
hw
important
1
updated
Oct 08, 2020
Output clock coupling
#24
· opened
Sep 23, 2020
by
Tomasz Wlostowski
Schematic done
hw
minor
1
updated
Oct 08, 2020
IC4O, IC43 - what's the role of this chip in the design?
#23
· opened
Sep 23, 2020
by
Tomasz Wlostowski
Schematic done
hw
minor
question
1
updated
Oct 08, 2020
Check mapping of FMC signals to FPGA
#22
· opened
Sep 23, 2020
by
Dimitris Lampridis
Critical
hdl
hw
CLOSED
5
updated
Apr 03, 2023
Bug in negative LDO enable generation
#21
· opened
Sep 22, 2020
by
Christos Gentsos
Schematic done
Critical
hw
3
updated
Oct 06, 2020
Wrong net label in FMC_Bus
#20
· opened
Sep 22, 2020
by
Dimitris Lampridis
Schematic done
Critical
hw
1
updated
Oct 06, 2020
Is Vadj = 2.2V realistic?
#19
· opened
Sep 21, 2020
by
Christos Gentsos
Schematic done
hw
question
3
updated
Oct 06, 2020
Remove unused signals from the FMCCLOCKS harness
#18
· opened
Sep 21, 2020
by
Christos Gentsos
Schematic done
cosmetics
hw
2
updated
Oct 06, 2020
VREF_A_M2C connection can be removed
#17
· opened
Sep 21, 2020
by
Christos Gentsos
Schematic done
cosmetics
hw
1
updated
Oct 06, 2020
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