• Federico Vaga's avatar
    sw:drv: data from FPGA is always little-endian · fe83df23
    Federico Vaga authored
    The data coming out from the FMC-ADC-110M FPGA is always using the
    little-endian byte order. This means that we need to fix the byte
    order only on big-endian CPUs.
    
    This allows to improve performances on SVEC-based designs since there
    is no need anymore to fix the endianness in software becuase it is
    already done in hardware.
    Signed-off-by: Federico Vaga's avatarFederico Vaga <federico.vaga@cern.ch>
    fe83df23
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