FmcAdc100M14b4cha svec firmware release 3.0 Changelog: - Increase decimation register width from 16 to 32 bits. - Change interrupt scheme, now uses eic + vic (changes in memory map). - Insert trigger time-tag in data, after post-trigger samples. - Fix sdb bridge offset address. - Prevent acquisition start if post trigger samples or number of shots is 0 (new "acq config ok" flag). - Change trigger position register to byte-address (was sample-address). - Add non-null meta field for timetags (mainly for test). - Move fmc eic and timetag core to mezzanine (behind the wb bridge). - Map 4kb on Wishbone bus for 'DDR data' slave (to allow for VME block access).