Programming languages used in this repository
-
VHDL
50.59 %
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C
31.95 %
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SystemVerilog
7.86 %
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Stata
3.0 %
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Verilog
2.47 %
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Makefile
1.89 %
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Python
1.27 %
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Tcl
0.98 %
Commit statistics for c60013144b652e7cb97163f2b79d309583693359 Nov 23 - Nov 25
- Total: 1294 commits
- Average per day: 0.3 commits
- Authors: 21
Commits per day of month
Commits per weekday
Commits per day hour (UTC)