Programming languages used in this repository

  •   VHDL
    50.44 %
  •   C
    32.01 %
  •   SystemVerilog
    7.83 %
  •   Stata
    2.99 %
  •   Verilog
    2.62 %
  •   Makefile
    1.88 %
  •   Python
    1.26 %
  •   Tcl
    0.98 %

Commit statistics for c60013144b652e7cb97163f2b79d309583693359 Nov 23 - Nov 25

  • Total: 1294 commits
  • Average per day: 0.3 commits
  • Authors: 21

Commits per day of month

Commits per weekday

Commits per day hour (UTC)