FMC ADC 100M 14b 4cha:svec-fmc-adc-v4.0 commitshttps://ohwr.org/project/fmc-adc-100m14b4cha/commits/svec-fmc-adc-v4.02014-04-25T11:57:25Zhttps://ohwr.org/project/fmc-adc-100m14b4cha/commit/06ab5cf448d60292313543c30d611e385bc1f088hdl: Fix bug in saturation block, add registers to improve timing.2014-04-25T11:57:25ZMatthieu Cattinmatthieu.cattin@cern.ch
- fixed and variable saturation blocks merged into one.
- registers added before the crossbar in the fmc-adc mezzanine component.
- acq_config_ok signal is now registered.https://ohwr.org/project/fmc-adc-100m14b4cha/commit/8f87d9baace5412e75575e2faa5fbb9cd3e15b1bhdl: Remove "reserved" fields from svec/spec carrier csr cores.2014-04-25T06:56:59ZMatthieu Cattinmatthieu.cattin@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha/commit/23fbb4787b93521fe494179503e85b5bea1a3697hdl: Remove "reserved" fields in fmc-adc core csr.2014-03-24T08:18:34ZMatthieu Cattinmatthieu.cattin@cern.ch
It was creating a big multiplexer in the wishbone crossbar and violating timing constrains.
Those reserved fields are replaced by "don't care" -> better optimised during synthesis.https://ohwr.org/project/fmc-adc-100m14b4cha/commit/af30d2cbd882f9bba5a344eb229feaea8524f322hdl: Move bicolor led controller to general-cores.2014-03-21T08:30:15ZMatthieu Cattinmatthieu.cattin@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha/commit/7c913fc1d118f9b04c09a659e38fa982ba46deb2doc: Update doc to describe new features.2014-03-20T10:13:36ZMatthieu Cattinmatthieu.cattin@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha/commit/267af46a92bf5be49595f270999e61846acbabe6hdl: Implements a seris of new features:2014-03-20T09:23:46ZMatthieu Cattinmatthieu.cattin@cern.ch
- Variable data saturation.
- Optional trigger threshold detection deglitch filter.
- Internal trigger test mode.
- Sampling frequency counter.
- Remaining shot counter.
- Defined DAC (for VCXO) control outputs value.
- Check number of samples in multi-shot (shouldn't exceed ram depth).https://ohwr.org/project/fmc-adc-100m14b4cha/commit/eb59690bf2dab2c318ca32854fad38572b4f1734doc: todo list -> add hysteresis on internal trigger slope detection.2014-03-11T08:36:29ZMatthieu Cattinmatthieu.cattin@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha/commit/09563ffb978ee6afec5410821b134344c12c9df5hdl: Add spexi top hdl design (Note that it's not compliant to the latest…2014-03-04T15:49:26ZMatthieu Cattinmatthieu.cattin@cern.chhdl: Add spexi top hdl design (Note that it's not compliant to the latest architecture and gnum core, yet).
https://ohwr.org/project/fmc-adc-100m14b4cha/commit/82789fdf0f742c8b402cca0242f44a7357b368d7doc: Remove outdated users guide (replaced by gateware guide).2014-03-04T15:42:50ZMatthieu Cattinmatthieu.cattin@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha/commit/2848345123681f9c5b24503e9fd94b8b208ab10bdoc: Add some point to the todo list.2014-02-17T13:00:20ZMatthieu Cattinmatthieu.cattin@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha/commit/daa3054c8b719c6e96f9e508a0fd7bb5008ad6cdhdl: Adapt interface to the new GN4124 core version.2014-02-07T16:10:55ZMatthieu Cattinmatthieu.cattin@cern.ch
The new GN4124 core version implements a timeout and ERR treatment on the csr wishbone interface.https://ohwr.org/project/fmc-adc-100m14b4cha/commit/1a901c7b0d78cccc784ede26137b60319aa4c21fdoc: Change fmc_adc_eic description.2014-01-30T10:49:33ZMatthieu Cattinmatthieu.cattin@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha/commit/aa03f4387f952a749dbe69237060ea7be8bfe9aadoc: rename firmware manual into gateware manual.2014-01-28T11:20:00ZMatthieu Cattinmatthieu.cattin@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha/commit/c5f6bc268cd049c1671ba0e30352dfb03f226613doc: Remove empty reference section.2014-01-17T10:16:32ZMatthieu Cattinmatthieu.cattin@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha/commit/7eb36a280e0606625accfc381b98a6ee62ee5dc3doc: Finalise gateware manual v3.02014-01-17T10:03:37ZMatthieu Cattinmatthieu.cattin@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha/commit/b84cf2ce606b8bd024296ede8f0d5ac164e53b47doc: Add some drawings, register docs and sdb tree descriptions.2014-01-17T09:01:46ZMatthieu Cattinmatthieu.cattin@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha/commit/010020ed8a33b8e1898a92afa2297d68d2abe6cedoc: Updating documentation for release v3.0 (in progress).2014-01-17T08:34:46ZMatthieu Cattinmatthieu.cattin@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha/commit/92c891b4047b0f44af4ea2533b5aeb56f6e4a9b6syn: svec-fmc-adc firmware release 3.02014-01-17T07:52:03ZMatthieu Cattinmatthieu.cattin@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha/commit/d620877893a014b684d7f7db8e8e560efc56a618hdl: Make mezzanine reset inactive by default on the svec.2014-01-16T17:28:40ZMatthieu Cattinmatthieu.cattin@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha/commit/f48f3593a8505a15d128e0d3cdea1c4e64e97a03syn: spec-fmc-adc firmware release 3.02014-01-16T17:26:26ZMatthieu Cattinmatthieu.cattin@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha/commit/3c4e2201126f2951a7a0333495a69ce5c7bac92ehdl: Make mezzanine reset inactive by default on the spec.2014-01-16T16:50:02ZMatthieu Cattinmatthieu.cattin@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha/commit/b536d7b48d21023d4f7002843925adc515d41bfchdl: Move fmc eic and timetag core to mezzanine (behind the wb bridge).2014-01-09T13:48:07ZMatthieu Cattinmatthieu.cattin@cern.ch
-> memory map changed!https://ohwr.org/project/fmc-adc-100m14b4cha/commit/f0c9a78a35e7a5af7e07594de21930824e0707e6hdl: Update fmc adc eic sdb records (with same data as in spec version).2014-01-07T16:48:49ZMatthieu Cattinmatthieu.cattin@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha/commit/d3c248bcbe9d60f4b8338464d4a8d1a7b0b8d26fhdl: Add non-null meta field for timetags (mainly for test).2014-01-07T16:35:23ZMatthieu Cattinmatthieu.cattin@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha/commit/5c6c0ed75e88d117f9fa4fbd194bba1bb79db152hdl: Change trigger position register to byte-address (was sample-address).2014-01-07T16:31:04ZMatthieu Cattinmatthieu.cattin@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha/commit/ddf254eed558826b17e8732584b0a16653f50987hdl, doc: Delete irq controller files (not used any more).2014-01-07T16:29:37ZMatthieu Cattinmatthieu.cattin@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha/commit/0580effb06addde059c6e36dd4050bab594c8294hdl, doc, sim: Fix sdb bridge offset address, add config ok flag, update doc ...2014-01-06T10:59:13ZMatthieu Cattinmatthieu.cattin@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha/commit/b48832a992e99449018fd39acaf75d2e57f6b7c5hdl: Insert trigger time-tag in data, after post-trigger samples.2013-12-13T16:38:43ZMatthieu Cattinmatthieu.cattin@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha/commit/94774b6696936c4b6bd2551a212e360d4c504774hdl: Change interrupt scheme, now uses eic + vic. Changes in memory map.2013-12-06T17:30:29ZMatthieu Cattinmatthieu.cattin@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha/commit/a7b6eaf56132cafb9aabf9f1a031d9a3ef3bf99adoc: Update todo list.2013-11-11T10:29:30ZMatthieu Cattinmatthieu.cattin@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha/commit/e513c580b51332e9c046b514f0479e30c45043e3hdl: Update vme core to latest version.2013-11-11T10:27:23ZMatthieu Cattinmatthieu.cattin@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha/commit/10d68343e22de9cce81f1f74108eeafe82c15c32hdl: Adapt xwb_clock_crossing generic to general-cores proposed master branch.2013-09-18T16:36:07ZMatthieu Cattinmatthieu.cattin@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha/commit/2f858137e574016251f8c255b4655f8c7568b24dhdl: Fix "unused" field width of the reset register.2013-09-18T16:28:42ZMatthieu Cattinmatthieu.cattin@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha/commit/f9628bcedd69cf38307f8565909d09a1b85e1a9ahdl: Increase decimation register width from 16 to 32 bits.2013-09-18T16:28:41ZMatthieu Cattinmatthieu.cattin@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha/commit/4ace92212d7d82c8ead7291af9a2f47c4fde45b0hdl: Uses general-cores proposed_master branch, since generic fifo have been ...2013-09-18T16:28:41ZMatthieu Cattinmatthieu.cattin@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha/commit/df8d5123962faad77b949d68400c211f4fbd52aesyn: Svec firmware release 1.02013-07-29T14:28:51ZMatthieu Cattinmatthieu.cattin@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha/commit/d742c0b873b078e981b38791aceeee4da2a61dcchdl: Add a software reset register to reset the mezzanines related cores.2013-07-29T09:52:49ZMatthieu Cattinmatthieu.cattin@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha/commit/2565e72452449ba51e5d69b12b48051b839cc0b1hdl: Update wbgen2 and re-generate cores.2013-07-29T09:52:48ZMatthieu Cattinmatthieu.cattin@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha/commit/414ece4f96db5af60c8ea72afcd2f61168c1a39bhdl: svec ise project for new interrupt controller.2013-07-29T09:52:48ZMatthieu Cattinmatthieu.cattin@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha/commit/2756acdd0cc075dd3a578f4a9fbeec20f5eb1109sim: Add random data acquisition to simulation to test interrupts.2013-07-29T09:52:48ZMatthieu Cattinmatthieu.cattin@cern.ch