[spec] fix WB mode for GN4124 interface, it should be CLASSIC

f54f430a · Dimitris Lampridis · e2122371 · f54f430a · f54f430a · f54f430a
Commit f54f430a authored Dec 12, 2019 by Dimitris Lampridis
Showing with 10 additions and 8 deletions

fmc_adc_100Ms_core.vhd hdl/rtl/fmc_adc_100Ms_core.vhd +1 -1

fmc_adc_mezzanine.vhd hdl/rtl/fmc_adc_mezzanine.vhd +5 -5

spec_ref_fmc_adc_100Ms.vhd hdl/top/spec_ref_design/spec_ref_fmc_adc_100Ms.vhd +4 -2

No files found.
--- a/hdl/rtl/fmc_adc_100Ms_core.vhd
+++ b/hdl/rtl/fmc_adc_100Ms_core.vhd
@@ -350,7 +350,7 @@ begin
  cmp_csr_wb_slave_adapter : wb_slave_adapter
    generic map (
      g_master_use_struct  => TRUE,
-      g_master_mode        => CLASSIC,
+      g_master_mode        => PIPELINED,
      g_master_granularity => BYTE,
      g_slave_use_struct   => TRUE,
      g_slave_mode         => g_WB_CSR_MODE,

--- a/hdl/rtl/fmc_adc_mezzanine.vhd
+++ b/hdl/rtl/fmc_adc_mezzanine.vhd
@@ -202,7 +202,7 @@ begin
  cmp_fmc_wb_slave_adapter_in : wb_slave_adapter
    generic map (
      g_master_use_struct  => TRUE,
-      g_master_mode        => CLASSIC,
+      g_master_mode        => PIPELINED,
      g_master_granularity => BYTE,
      g_slave_use_struct   => TRUE,
      g_slave_mode         => g_WB_MODE,
@@ -218,7 +218,7 @@ begin
  -- Additional register to help timing
  cmp_xwb_register : xwb_register
    generic map (
-      g_WB_MODE  => CLASSIC)
+      g_WB_MODE => PIPELINED)
    port map (
      rst_n_i  => sys_rst_n_i,
      clk_i    => sys_clk_i,
@@ -253,7 +253,7 @@ begin
  ------------------------------------------------------------------------------
  cmp_fmc_spi : xwb_spi
    generic map(
-      g_interface_mode      => CLASSIC,
+      g_interface_mode      => PIPELINED,
      g_address_granularity => BYTE
      )
    port map (
@@ -293,7 +293,7 @@ begin
  ------------------------------------------------------------------------------
  cmp_fmc_i2c : xwb_i2c_master
    generic map(
-      g_interface_mode      => CLASSIC,
+      g_interface_mode      => PIPELINED,
      g_address_granularity => BYTE
      )
    port map (
@@ -333,7 +333,7 @@ begin
      g_SPARTAN6_USE_PLL   => g_SPARTAN6_USE_PLL,
      g_TRIG_DELAY_EXT     => g_TRIG_DELAY_EXT,
      g_TRIG_DELAY_SW      => g_TRIG_DELAY_SW,
-      g_WB_CSR_MODE        => CLASSIC,
+      g_WB_CSR_MODE        => PIPELINED,
      g_WB_CSR_GRANULARITY => BYTE)
    port map (
      sys_clk_i   => sys_clk_i,

--- a/hdl/top/spec_ref_design/spec_ref_fmc_adc_100Ms.vhd
+++ b/hdl/top/spec_ref_design/spec_ref_fmc_adc_100Ms.vhd
@@ -424,6 +424,9 @@ begin  -- architecture arch
  ------------------------------------------------------------------------------
  cmp_xwb_clock_bridge : xwb_clock_bridge
+    generic map (
+      g_SLAVE_PORT_WB_MODE  => CLASSIC,
+      g_MASTER_PORT_WB_MODE => PIPELINED)
    port map (
      slave_clk_i    => clk_sys_62m5,
      slave_rst_n_i  => rst_sys_62m5_n,
@@ -432,8 +435,7 @@ begin  -- architecture arch
      master_clk_i   => clk_ref_125m,
      master_rst_n_i => rst_ref_125m_n,
      master_i       => cnx_fmc_sync_master_in,
-      master_o       => cnx_fmc_sync_master_out
+      master_o       => cnx_fmc_sync_master_out);
-      );
  cmp_tm_time_valid_sync : gc_sync_ffs
    port map (