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FMC ADC 100M 14b 4cha
Commit e433068e authored by Dimitris Lampridis's avatar Dimitris Lampridis
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update submodules to bring in latest versions and fixes

parent a32bdc66
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Showing with 26 additions and 25 deletions
general-cores @ aeee595d
Subproject commit 0ed0cf1d2d8b21a9d92fea949a1ccaa03d9883a2
Subproject commit aeee595d5d0079f036d3eade44d479a8650f1285
gn4124-core @ b5752886
Subproject commit 10cd74b06a094c5b6c1a566676785e1814001404
Subproject commit b57528861e0ee8351b87dc3d4ec4da6a118b4a48
vme64x-core @ 1204aeca
Subproject commit 78cac8713658de449dcccbce5a5d35131461fc34
Subproject commit 1204aeca29ec3c72b6fa615976f000c664c7d152
wr-cores @ 3dcac448
Subproject commit 0d636aa520d0b547dbb1e8bd6f09d85f21203347
Subproject commit 3dcac4483417a159f0b9495adab0c15b7b45692b
hdl/syn/spec_ref_design_wr/spec_ref_fmc_adc_100Ms_wr.ucf
View file @ e433068e
......@@ -380,16 +380,6 @@ NET "adc_si570_scl_b" IOSTANDARD = "LVCMOS25";
NET "adc_si570_sda_b" IOSTANDARD = "LVCMOS25";
NET "adc_one_wire_b" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# IOBs
#----------------------------------------
INST "cmp_gn4124_core/cmp_wrapped_gn4124/l2p_rdy_t" IOB = FALSE;
INST "cmp_gn4124_core/cmp_wrapped_gn4124/l_wr_rdy_t*" IOB = FALSE;
INST "cmp_fmc_adc_mezzanine/cmp_fmc_spi/*/Wrapped_SPI/shift/s_out" IOB = FALSE;
INST "cmp_fmc_adc_mezzanine/cmp_fmc_spi/*/Wrapped_SPI/clgen/clk_out" IOB = FALSE;
#===============================================================================
# Timing Constraints
#===============================================================================
......@@ -447,7 +437,6 @@ NET "cmp_ddr_ctrl_bank?/*/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
# GN4124
NET "gn_rst_n_i" TIG;
NET "cmp_gn4124_core/cmp_wrapped_gn4124/rst_*" TIG;
# Ignore async reset inputs to reset synchronisers
NET "*/gc_reset_async_in" TIG;
......
hdl/top/spec_ref_design/spec_ref_fmc_adc_100Ms.vhd
View file @ e433068e
......@@ -314,8 +314,9 @@ architecture rtl of spec_ref_fmc_adc_100Ms is
------------------------------------------------------------------------------
-- WRPC Xilinx platform auxiliary clock configuration, used for DDR clock
constant c_WRPC_PLL_CONFIG : t_px_pll_cfg := (
enabled => TRUE, divide => 3, multiply => 8 );
constant c_WRPC_PLL_CONFIG : t_auxpll_cfg_array := (
0 => (enabled => TRUE, bufg_en => TRUE, divide => 3),
others => c_AUXPLL_CFG_DEFAULT);
-- SPEC carrier CSR constants
constant c_CARRIER_TYPE : std_logic_vector(15 downto 0) := X"0001";
......@@ -341,7 +342,9 @@ architecture rtl of spec_ref_fmc_adc_100Ms is
signal clk_ref_125m : std_logic;
signal sys_clk_pll_locked : std_logic;
signal clk_ddr_333m : std_logic;
signal clk_pll_aux : std_logic_vector(3 downto 0);
signal rst_pll_aux_n : std_logic_vector(3 downto 0) := (others => '0');
signal rst_sys_62m5_n : std_logic := '0';
signal rst_ref_125m_n : std_logic := '0';
signal rst_ddr_333m_n : std_logic := '0';
......@@ -546,7 +549,7 @@ begin
g_SIMULATION => g_SIMULATION,
g_WITH_EXTERNAL_CLOCK_INPUT => FALSE,
g_DPRAM_INITF => g_WRPC_INITF,
g_AUX_PLL_CONFIG => c_WRPC_PLL_CONFIG,
g_AUX_PLL_CFG => c_WRPC_PLL_CONFIG,
g_FABRIC_IFACE => PLAIN)
port map (
clk_20m_vcxo_i => clk_20m_vcxo_i,
......@@ -558,10 +561,10 @@ begin
areset_edge_n_i => gn_rst_n_i,
clk_sys_62m5_o => clk_sys_62m5,
clk_ref_125m_o => clk_ref_125m,
clk_pll_aux_o => clk_ddr_333m,
clk_pll_aux_o => clk_pll_aux,
rst_sys_62m5_n_o => rst_sys_62m5_n,
rst_ref_125m_n_o => rst_ref_125m_n,
rst_pll_aux_n_o => rst_ddr_333m_n,
rst_pll_aux_n_o => rst_pll_aux_n,
plldac_sclk_o => plldac_sclk_o,
plldac_din_o => plldac_din_o,
pll25dac_cs_n_o => pll25dac_sync_n_o,
......@@ -599,6 +602,9 @@ begin
led_act_o => wr_led_act,
link_ok_o => wrabbit_en);
clk_ddr_333m <= clk_pll_aux(0);
rst_ddr_333m_n <= rst_pll_aux_n(0);
------------------------------------------------------------------------------
-- Carrier CSR
-- Carrier type and PCB version
......
hdl/top/svec_ref_design/svec_ref_fmc_adc_100Ms.vhd
View file @ e433068e
......@@ -346,8 +346,9 @@ architecture rtl of svec_ref_fmc_adc_100Ms is
------------------------------------------------------------------------------
-- WRPC Xilinx platform auxiliary clock configuration, used for DDR clock
constant c_WRPC_PLL_CONFIG : t_px_pll_cfg := (
enabled => TRUE, divide => 3, multiply => 8 );
constant c_WRPC_PLL_CONFIG : t_auxpll_cfg_array := (
0 => (enabled => TRUE, bufg_en => TRUE, divide => 3),
others => c_AUXPLL_CFG_DEFAULT);
-- SVEC carrier CSR constants
constant c_CARRIER_TYPE : std_logic_vector(15 downto 0) := X"0002";
......@@ -375,7 +376,9 @@ architecture rtl of svec_ref_fmc_adc_100Ms is
signal clk_ref_125m : std_logic;
signal sys_clk_pll_locked : std_logic;
signal clk_ddr_333m : std_logic;
signal clk_pll_aux : std_logic_vector(3 downto 0);
signal rst_pll_aux_n : std_logic_vector(3 downto 0) := (others => '0');
signal areset_n : std_logic := '0';
signal rst_sys_62m5_n : std_logic := '0';
signal rst_ref_125m_n : std_logic := '0';
......@@ -610,7 +613,7 @@ begin
g_SIMULATION => g_SIMULATION,
g_WITH_EXTERNAL_CLOCK_INPUT => FALSE,
g_DPRAM_INITF => g_WRPC_INITF,
g_AUX_PLL_CONFIG => c_WRPC_PLL_CONFIG,
g_AUX_PLL_CFG => c_WRPC_PLL_CONFIG,
g_FABRIC_IFACE => PLAIN)
port map (
clk_20m_vcxo_i => clk_20m_vcxo_i,
......@@ -621,10 +624,10 @@ begin
areset_n_i => areset_n,
clk_sys_62m5_o => clk_sys_62m5,
clk_ref_125m_o => clk_ref_125m,
clk_pll_aux_o => clk_ddr_333m,
clk_pll_aux_o => clk_pll_aux,
rst_sys_62m5_n_o => rst_sys_62m5_n,
rst_ref_125m_n_o => rst_ref_125m_n,
rst_pll_aux_n_o => rst_ddr_333m_n,
rst_pll_aux_n_o => rst_pll_aux_n,
pll20dac_din_o => pll20dac_din_o,
pll20dac_sclk_o => pll20dac_sclk_o,
pll20dac_sync_n_o => pll20dac_sync_n_o,
......@@ -668,6 +671,9 @@ begin
led_act_o => wr_led_act,
link_ok_o => wrabbit_en);
clk_ddr_333m <= clk_pll_aux(0);
rst_ddr_333m_n <= rst_pll_aux_n(0);
------------------------------------------------------------------------------
-- Carrier CSR
-- Carrier type and PCB version
......
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