Merge branch '25-build-fpga-bitstreams-in-ci' into 'master'

Resolve "Build FPGA bitstreams in CI" Closes #25 See merge request be-cem-edl/fec/hardware-modules/fmc-adc-100m14b4cha!10

Merge branch '25-build-fpga-bitstreams-in-ci' into 'master'
Resolve "Build FPGA bitstreams in CI" Closes #25 See merge request be-cem-edl/fec/hardware-modules/fmc-adc-100m14b4cha!10
d5b74fb1 · Dimitris Lampridis · b0612ebf · f9896a9d · d5b74fb1 · d5b74fb1
Commit d5b74fb1 authored Dec 05, 2022 by Dimitris Lampridis
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.gitlab-ci.yml .gitlab-ci.yml +1 -0

.gitlab-ci.yml hdl/syn/.gitlab-ci.yml +39 -0

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--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -10,6 +10,7 @@ include:
    ref: master
    file:
      - 'edl-gitlab-ci.yml'
+  - local: 'hdl/syn/.gitlab-ci.yml'

 cppcheck:
  stage: analyse

--- a/hdl/syn/.gitlab-ci.yml
+++ b/hdl/syn/.gitlab-ci.yml
+# SPDX-FileCopyrightText: 2022 CERN (home.cern)
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+
+.syn_template: &syn_template
+  interruptible: true
+  stage: build
+  needs: []
+  tags:
+    - xilinx_ise
+    - "14.7"
+  script:
+    - git submodule init && git submodule update
+    - cd hdl/syn/"$SYN_NAME"/
+    - hdlmake
+    - make
+  artifacts:
+    name: "$SYN_NAME-synthesis-$CI_JOB_NAME-$CI_COMMIT_REF_NAME"
+    paths:
+      - hdl/syn/$SYN_NAME/*.syr
+      - hdl/syn/$SYN_NAME/*.par
+      - hdl/syn/$SYN_NAME/*.twr
+      - hdl/syn/$SYN_NAME/*.bit
+      - hdl/syn/$SYN_NAME/*.bin
+
+SPEC45T synthesis:
+  variables:
+    SYN_NAME: "spec_ref_design_wr"
+  <<: *syn_template
+
+SPEC150T synthesis:
+  variables:
+    SYN_NAME: "spec150_ref_design_wr"
+  <<: *syn_template
+
+SVEC synthesis:
+  variables:
+    SYN_NAME: "svec_ref_design_wr"
+  <<: *syn_template