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FMC ADC 100M 14b 4cha
Commit d2cc3e3c authored by Dimitris Lampridis's avatar Dimitris Lampridis
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doc: fix small typo 

Signed-off-by: Dimitris Lampridis's avatarDimitris Lampridis <dimitris.lampridis@cern.ch>
parent b5b291e7
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doc/gateware/index.rst
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......@@ -444,7 +444,7 @@ of a data word are always set to zero.
Control and Status Registers
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Writing one to to the ``FMC_CLK_OE`` field of the ADC core control
Writing one to the ``FMC_CLK_OE`` field of the ADC core control
register enables the sampling clock (Si570 chip). Also, in order to use
the input offset DACs, the ``OFFSET_DAC_CLR_N`` field must be set to
one.
......
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