Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
F
FMC ADC 100M 14b 4cha
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
FMC ADC 100M 14b 4cha
Commits
c5f1f0c6
Commit
c5f1f0c6
authored
Jun 13, 2016
by
Dimitris Lampridis
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
hdl: added a bit to carrier CSR to control enabling of WR features
parent
14262933
Hide whitespace changes
Inline
Side-by-side
Showing
16 changed files
with
249 additions
and
121 deletions
+249
-121
carrier_csr.tex
doc/manual/spec/carrier_csr.tex
+6
-0
carrier_csr.tex
doc/manual/svec/carrier_csr.tex
+6
-0
fmc_adc_mezzanine.vhd
hdl/adc/rtl/fmc_adc_mezzanine.vhd
+39
-33
fmc_adc_mezzanine_pkg.vhd
hdl/adc/rtl/fmc_adc_mezzanine_pkg.vhd
+38
-38
timetag_core.vhd
hdl/ip_cores/timetag_core/rtl/timetag_core.vhd
+16
-6
timetag_core_pkg.vhd
hdl/ip_cores/timetag_core/rtl/timetag_core_pkg.vhd
+20
-17
carrier_csr.vhd
hdl/spec/rtl/carrier_csr.vhd
+9
-2
spec_top_fmc_adc_100Ms.vhd
hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
+17
-11
carrier_csr.h
hdl/spec/wb_gen/carrier_csr.h
+4
-1
carrier_csr.htm
hdl/spec/wb_gen/carrier_csr.htm
+23
-2
carrier_csr.wb
hdl/spec/wb_gen/carrier_csr.wb
+10
-0
carrier_csr.vhd
hdl/svec/rtl/carrier_csr.vhd
+9
-2
svec_top_fmc_adc_100Ms.vhd
hdl/svec/rtl/svec_top_fmc_adc_100Ms.vhd
+15
-6
carrier_csr.h
hdl/svec/wb_gen/carrier_csr.h
+4
-1
carrier_csr.htm
hdl/svec/wb_gen/carrier_csr.htm
+23
-2
carrier_csr.wb
hdl/svec/wb_gen/carrier_csr.wb
+10
-0
No files found.
doc/manual/spec/carrier_csr.tex
View file @
c5f1f0c6
...
...
@@ -92,12 +92,18 @@ Red LED
@code
{
DAC
_
CLR
_
N
}
@tab @code
{
0
}
@tab
DAC clear
@item @code
{
3
}
@tab R/W @tab
@code
{
WRABBIT
_
EN
}
@tab @code
{
0
}
@tab
White Rabbit enable
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code
{
led
_
green
}
@tab Manual control of the front panel green LED (unused in the fmc-adc application)
@item @code
{
led
_
red
}
@tab Manual control of the front panel red LED (unused in the fmc-adc application)
@item @code
{
dac
_
clr
_
n
}
@tab Active low clear signal for VCXO DACs
@item @code
{
wrabbit
_
en
}
@tab Enable White Rabbit features
@end multitable
@regsection @code
{
rst
}
- Reset Register
Controls software reset of the mezzanine including the ddr interface and the time-tagging core.
...
...
doc/manual/svec/carrier_csr.tex
View file @
c5f1f0c6
...
...
@@ -88,10 +88,16 @@ DDR3 bank 5 calibration status
@code
{
FP
_
LEDS
_
MAN
}
@tab @code
{
0
}
@tab
Front panel LED manual control
@item @code
{
16
}
@tab R/W @tab
@code
{
WRABBIT
_
EN
}
@tab @code
{
0
}
@tab
White Rabbit enable
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code
{
fp
_
leds
_
man
}
@tab Height front panel LED, two bits per LED.@*00 = OFF@*01 = Green@*10 = Red@*11 = Orange
@item @code
{
wrabbit
_
en
}
@tab Enable White Rabbit features
@end multitable
@regsection @code
{
rst
}
- Reset Register
Controls software reset of the mezzanines including the ddr interface and the time-tagging core.
...
...
hdl/adc/rtl/fmc_adc_mezzanine.vhd
View file @
c5f1f0c6
...
...
@@ -8,7 +8,7 @@
-- Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2013-05-07
-- Last update: 2016-06-0
8
-- Last update: 2016-06-0
9
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: The FMC ADC mezzanine is wrapper around the fmc-adc-100ms core
...
...
@@ -83,7 +83,7 @@ entity fmc_adc_mezzanine is
eic_irq_o
:
out
std_logic
;
-- FMC interface
ext_trigger_p_i
:
in
std_logic
;
-- External trigger
ext_trigger_p_i
:
in
std_logic
;
-- External trigger
ext_trigger_n_i
:
in
std_logic
;
adc_dco_p_i
:
in
std_logic
;
-- ADC data clock
...
...
@@ -95,31 +95,33 @@ entity fmc_adc_mezzanine is
adc_outb_p_i
:
in
std_logic_vector
(
3
downto
0
);
-- ADC serial data (even bits)
adc_outb_n_i
:
in
std_logic_vector
(
3
downto
0
);
gpio_dac_clr_n_o
:
out
std_logic
;
-- offset DACs clear (active low)
gpio_led_acq_o
:
out
std_logic
;
-- Mezzanine front panel power LED (PWR)
gpio_led_trig_o
:
out
std_logic
;
-- Mezzanine front panel trigger LED (TRIG)
gpio_dac_clr_n_o
:
out
std_logic
;
-- offset DACs clear (active low)
gpio_led_acq_o
:
out
std_logic
;
-- Mezzanine front panel power LED (PWR)
gpio_led_trig_o
:
out
std_logic
;
-- Mezzanine front panel trigger LED (TRIG)
gpio_ssr_ch1_o
:
out
std_logic_vector
(
6
downto
0
);
-- Channel 1 solid state relays control
gpio_ssr_ch2_o
:
out
std_logic_vector
(
6
downto
0
);
-- Channel 2 solid state relays control
gpio_ssr_ch3_o
:
out
std_logic_vector
(
6
downto
0
);
-- Channel 3 solid state relays control
gpio_ssr_ch4_o
:
out
std_logic_vector
(
6
downto
0
);
-- Channel 4 solid state relays control
gpio_si570_oe_o
:
out
std_logic
;
-- Si570 (programmable oscillator) output enable
gpio_si570_oe_o
:
out
std_logic
;
-- Si570 (programmable oscillator) output enable
spi_din_i
:
in
std_logic
;
-- SPI data from FMC
spi_dout_o
:
out
std_logic
;
-- SPI data to FMC
spi_sck_o
:
out
std_logic
;
-- SPI clock
spi_cs_adc_n_o
:
out
std_logic
;
-- SPI ADC chip select (active low)
spi_cs_dac1_n_o
:
out
std_logic
;
-- SPI channel 1 offset DAC chip select (active low)
spi_cs_dac2_n_o
:
out
std_logic
;
-- SPI channel 2 offset DAC chip select (active low)
spi_cs_dac3_n_o
:
out
std_logic
;
-- SPI channel 3 offset DAC chip select (active low)
spi_cs_dac4_n_o
:
out
std_logic
;
-- SPI channel 4 offset DAC chip select (active low)
spi_din_i
:
in
std_logic
;
-- SPI data from FMC
spi_dout_o
:
out
std_logic
;
-- SPI data to FMC
spi_sck_o
:
out
std_logic
;
-- SPI clock
spi_cs_adc_n_o
:
out
std_logic
;
-- SPI ADC chip select (active low)
spi_cs_dac1_n_o
:
out
std_logic
;
-- SPI channel 1 offset DAC chip select (active low)
spi_cs_dac2_n_o
:
out
std_logic
;
-- SPI channel 2 offset DAC chip select (active low)
spi_cs_dac3_n_o
:
out
std_logic
;
-- SPI channel 3 offset DAC chip select (active low)
spi_cs_dac4_n_o
:
out
std_logic
;
-- SPI channel 4 offset DAC chip select (active low)
si570_scl_b
:
inout
std_logic
;
-- I2C bus clock (Si570)
si570_sda_b
:
inout
std_logic
;
-- I2C bus data (Si570)
si570_scl_b
:
inout
std_logic
;
-- I2C bus clock (Si570)
si570_sda_b
:
inout
std_logic
;
-- I2C bus data (Si570)
mezz_one_wire_b
:
inout
std_logic
;
-- Mezzanine 1-wire interface (DS18B20 thermometer + unique ID)
sys_scl_b
:
inout
std_logic
;
-- Mezzanine system I2C clock (EEPROM)
sys_sda_b
:
inout
std_logic
-- Mezzanine system I2C data (EEPROM)
sys_scl_b
:
inout
std_logic
;
-- Mezzanine system I2C clock (EEPROM)
sys_sda_b
:
inout
std_logic
;
-- Mezzanine system I2C data (EEPROM)
wr_enable_i
:
in
std_logic
-- enable white rabbit features on mezzanine
);
end
fmc_adc_mezzanine
;
...
...
@@ -174,49 +176,49 @@ architecture rtl of fmc_adc_mezzanine is
-- Devices sdb description
constant
c_wb_adc_csr_sdb
:
t_sdb_device
:
=
(
abi_class
=>
x"0000"
,
-- undocumented device
abi_class
=>
x"0000"
,
-- undocumented device
abi_ver_major
=>
x"01"
,
abi_ver_minor
=>
x"01"
,
wbd_endian
=>
c_sdb_endian_big
,
wbd_width
=>
x"4"
,
-- 32-bit port granularity
wbd_width
=>
x"4"
,
-- 32-bit port granularity
sdb_component
=>
(
addr_first
=>
x"0000000000000000"
,
addr_last
=>
x"00000000000000FF"
,
product
=>
(
vendor_id
=>
x"000000000000CE42"
,
-- CERN
vendor_id
=>
x"000000000000CE42"
,
-- CERN
device_id
=>
x"00000608"
,
version
=>
x"00000001"
,
date
=>
x"20121116"
,
name
=>
"WB-FMC-ADC-Core "
)));
constant
c_wb_timetag_sdb
:
t_sdb_device
:
=
(
abi_class
=>
x"0000"
,
-- undocumented device
abi_class
=>
x"0000"
,
-- undocumented device
abi_ver_major
=>
x"01"
,
abi_ver_minor
=>
x"01"
,
wbd_endian
=>
c_sdb_endian_big
,
wbd_width
=>
x"4"
,
-- 32-bit port granularity
wbd_width
=>
x"4"
,
-- 32-bit port granularity
sdb_component
=>
(
addr_first
=>
x"0000000000000000"
,
addr_last
=>
x"000000000000007F"
,
product
=>
(
vendor_id
=>
x"000000000000CE42"
,
-- CERN
vendor_id
=>
x"000000000000CE42"
,
-- CERN
device_id
=>
x"00000604"
,
version
=>
x"00000001"
,
date
=>
x"20121116"
,
name
=>
"WB-Timetag-Core "
)));
constant
c_wb_fmc_adc_eic_sdb
:
t_sdb_device
:
=
(
abi_class
=>
x"0000"
,
-- undocumented device
abi_class
=>
x"0000"
,
-- undocumented device
abi_ver_major
=>
x"01"
,
abi_ver_minor
=>
x"01"
,
wbd_endian
=>
c_sdb_endian_big
,
wbd_width
=>
x"4"
,
-- 32-bit port granularity
wbd_width
=>
x"4"
,
-- 32-bit port granularity
sdb_component
=>
(
addr_first
=>
x"0000000000000000"
,
addr_last
=>
x"000000000000000F"
,
product
=>
(
vendor_id
=>
x"000000000000CE42"
,
-- CERN
device_id
=>
x"26ec6086"
,
-- "WB-FMC-ADC.EIC " | md5sum | cut -c1-8
vendor_id
=>
x"000000000000CE42"
,
-- CERN
device_id
=>
x"26ec6086"
,
-- "WB-FMC-ADC.EIC " | md5sum | cut -c1-8
version
=>
x"00000001"
,
date
=>
x"20131204"
,
name
=>
"WB-FMC-ADC.EIC "
)));
...
...
@@ -311,8 +313,8 @@ begin
generic
map
(
g_num_masters
=>
c_NUM_WB_SLAVES
,
g_num_slaves
=>
c_NUM_WB_MASTERS
,
g_registered
=>
true
,
g_wraparound
=>
true
,
g_registered
=>
TRUE
,
g_wraparound
=>
TRUE
,
g_layout
=>
c_INTERCONNECT_LAYOUT
,
g_sdb_addr
=>
c_SDB_ADDRESS
)
port
map
(
...
...
@@ -388,7 +390,7 @@ begin
pad_cs_o
=>
spi_ss_t
,
pad_sclk_o
=>
spi_sck_o
,
pad_mosi_o
=>
spi_dout_o
,
pad_miso_i
=>
spi_din_t
(
spi_din_t
'
left
)
pad_miso_i
=>
spi_din_t
(
spi_din_t
'
LEFT
)
);
-- Assign slave select lines
...
...
@@ -405,7 +407,7 @@ begin
if
sys_rst_n_i
=
'0'
then
spi_din_t
<=
(
others
=>
'0'
);
else
spi_din_t
<=
spi_din_t
(
spi_din_t
'
left
-1
downto
0
)
&
spi_din_i
;
spi_din_t
<=
spi_din_t
(
spi_din_t
'
LEFT
-1
downto
0
)
&
spi_din_i
;
end
if
;
end
if
;
end
process
p_fmc_spi
;
...
...
@@ -610,7 +612,11 @@ begin
acq_stop_p_i
=>
acq_stop_p
,
acq_end_p_i
=>
acq_end_p
,
wr_enabled_i
=>
'0'
,
wr_enabled_i
=>
wr_enable_i
,
wr_tm_time_valid_i
=>
'1'
,
wr_tm_tai_i
=>
X"123456789a"
,
wr_tm_cycles_i
=>
X"edcba98"
,
trig_tag_o
=>
trigger_tag
,
...
...
hdl/adc/rtl/fmc_adc_mezzanine_pkg.vhd
View file @
c5f1f0c6
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- FMC ADC mezzanine package
-- http://www.ohwr.org/projects/fmc-adc-100m14b4cha
--------------------------------------------------------------------------------
--
-- unit name: fmc_adc_mezzanine_pkg (fmc_adc_mezzanine_pkg.vhd)
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 03-07-2013
--
-- version: 1.0
--
-- description: Package for FMC ADC mezzanine
--
-- dependencies:
--
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Title : FMC ADC mezzanine package
-- Project : FMC ADC 100M 14B 4CHA gateware
-- URL : http://www.ohwr.org/projects/fmc-adc-100m14b4cha-gw
-------------------------------------------------------------------------------
-- File : fmc_adc_mezzanine_pkg.vhd
-- Author(s) : Matthieu Cattin <matthieu.cattin@cern.ch>
-- Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2013-07-03
-- Last update: 2016-06-09
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Package for FMC ADC mezzanine
-------------------------------------------------------------------------------
-- Copyright (c) 2013-2016 CERN (BE-CO-HT)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------
-
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
...
...
@@ -28,11 +26,11 @@
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-
--
last changes: see svn log.
--
------------------------------------------------------------------------------
--
TODO: -
-------------------------------------------------------------------------------
-
-------------------------------------------------------------------------------
--
Revisions :
--
Date Version Author
--
2013-07-03 1.0 Matthieu Cattin
-------------------------------------------------------------------------------
library
IEEE
;
use
IEEE
.
STD_LOGIC_1164
.
all
;
...
...
@@ -89,7 +87,7 @@ package fmc_adc_mezzanine_pkg is
eic_irq_o
:
out
std_logic
;
-- FMC interface
ext_trigger_p_i
:
in
std_logic
;
-- External trigger
ext_trigger_p_i
:
in
std_logic
;
-- External trigger
ext_trigger_n_i
:
in
std_logic
;
adc_dco_p_i
:
in
std_logic
;
-- ADC data clock
...
...
@@ -101,31 +99,33 @@ package fmc_adc_mezzanine_pkg is
adc_outb_p_i
:
in
std_logic_vector
(
3
downto
0
);
-- ADC serial data (even bits)
adc_outb_n_i
:
in
std_logic_vector
(
3
downto
0
);
gpio_dac_clr_n_o
:
out
std_logic
;
-- offset DACs clear (active low)
gpio_led_acq_o
:
out
std_logic
;
-- Mezzanine front panel power LED (PWR)
gpio_led_trig_o
:
out
std_logic
;
-- Mezzanine front panel trigger LED (TRIG)
gpio_dac_clr_n_o
:
out
std_logic
;
-- offset DACs clear (active low)
gpio_led_acq_o
:
out
std_logic
;
-- Mezzanine front panel power LED (PWR)
gpio_led_trig_o
:
out
std_logic
;
-- Mezzanine front panel trigger LED (TRIG)
gpio_ssr_ch1_o
:
out
std_logic_vector
(
6
downto
0
);
-- Channel 1 solid state relays control
gpio_ssr_ch2_o
:
out
std_logic_vector
(
6
downto
0
);
-- Channel 2 solid state relays control
gpio_ssr_ch3_o
:
out
std_logic_vector
(
6
downto
0
);
-- Channel 3 solid state relays control
gpio_ssr_ch4_o
:
out
std_logic_vector
(
6
downto
0
);
-- Channel 4 solid state relays control
gpio_si570_oe_o
:
out
std_logic
;
-- Si570 (programmable oscillator) output enable
gpio_si570_oe_o
:
out
std_logic
;
-- Si570 (programmable oscillator) output enable
spi_din_i
:
in
std_logic
;
-- SPI data from FMC
spi_dout_o
:
out
std_logic
;
-- SPI data to FMC
spi_sck_o
:
out
std_logic
;
-- SPI clock
spi_cs_adc_n_o
:
out
std_logic
;
-- SPI ADC chip select (active low)
spi_din_i
:
in
std_logic
;
-- SPI data from FMC
spi_dout_o
:
out
std_logic
;
-- SPI data to FMC
spi_sck_o
:
out
std_logic
;
-- SPI clock
spi_cs_adc_n_o
:
out
std_logic
;
-- SPI ADC chip select (active low)
spi_cs_dac1_n_o
:
out
std_logic
;
-- SPI channel 1 offset DAC chip select (active low)
spi_cs_dac2_n_o
:
out
std_logic
;
-- SPI channel 2 offset DAC chip select (active low)
spi_cs_dac3_n_o
:
out
std_logic
;
-- SPI channel 3 offset DAC chip select (active low)
spi_cs_dac4_n_o
:
out
std_logic
;
-- SPI channel 4 offset DAC chip select (active low)
si570_scl_b
:
inout
std_logic
;
-- I2C bus clock (Si570)
si570_sda_b
:
inout
std_logic
;
-- I2C bus data (Si570)
si570_scl_b
:
inout
std_logic
;
-- I2C bus clock (Si570)
si570_sda_b
:
inout
std_logic
;
-- I2C bus data (Si570)
mezz_one_wire_b
:
inout
std_logic
;
-- Mezzanine 1-wire interface (DS18B20 thermometer + unique ID)
sys_scl_b
:
inout
std_logic
;
-- Mezzanine system I2C clock (EEPROM)
sys_sda_b
:
inout
std_logic
-- Mezzanine system I2C data (EEPROM)
sys_scl_b
:
inout
std_logic
;
-- Mezzanine system I2C clock (EEPROM)
sys_sda_b
:
inout
std_logic
;
-- Mezzanine system I2C data (EEPROM)
wr_enable_i
:
in
std_logic
-- enable white rabbit features on mezzanine
);
end
component
fmc_adc_mezzanine
;
...
...
hdl/ip_cores/timetag_core/rtl/timetag_core.vhd
View file @
c5f1f0c6
...
...
@@ -8,7 +8,7 @@
-- : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-11-18
-- Last update: 2016-06-0
8
-- Last update: 2016-06-0
9
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Implements a UTC seconds counter and a 125MHz system clock
...
...
@@ -53,6 +53,11 @@ entity timetag_core is
-- White Rabbit enabled flag
wr_enabled_i
:
in
std_logic
;
-- White Rabbit timecode interface input
wr_tm_time_valid_i
:
in
std_logic
;
wr_tm_tai_i
:
in
std_logic_vector
(
39
downto
0
);
wr_tm_cycles_i
:
in
std_logic_vector
(
27
downto
0
);
-- Trigger time-tag output
trig_tag_o
:
out
t_timetag
;
...
...
@@ -129,10 +134,13 @@ architecture rtl of timetag_core is
signal
local_pps
:
std_logic
;
signal
wr_enabled
:
std_logic
:
=
'0'
;
begin
-- logic to detect if WR is enabled and timecode is valid
wr_enabled
<=
wr_enabled_i
and
wr_tm_time_valid_i
;
------------------------------------------------------------------------------
-- Wishbone interface to UTC core registers
------------------------------------------------------------------------------
...
...
@@ -184,12 +192,14 @@ begin
elsif
timetag_seconds_load_en
(
0
)
=
'1'
then
timetag_seconds_cnt
(
31
downto
0
)
<=
unsigned
(
timetag_seconds_load_value
(
31
downto
0
));
elsif
local_pps
=
'1'
then
timetag_seconds_cnt
<=
timetag_seconds_cnt
+
1
;
timetag_seconds_cnt
<=
unsigned
(
timetag_seconds
)
+
1
;
else
timetag_seconds_cnt
<=
unsigned
(
timetag_seconds
);
end
if
;
end
if
;
end
process
p_timetag_seconds_cnt
;
timetag_seconds
<=
std_logic_vector
(
timetag_seconds_cnt
);
timetag_seconds
<=
wr_tm_tai_i
when
wr_enabled_i
=
'1'
else
std_logic_vector
(
timetag_seconds_cnt
);
------------------------------------------------------------------------------
-- UTC 125MHz clock ticks counter
...
...
@@ -207,13 +217,13 @@ begin
timetag_coarse_cnt
<=
(
others
=>
'0'
);
local_pps
<=
'1'
;
else
timetag_coarse_cnt
<=
timetag_coarse_cnt
+
1
;
timetag_coarse_cnt
<=
unsigned
(
timetag_coarse
)
+
1
;
local_pps
<=
'0'
;
end
if
;
end
if
;
end
process
p_timetag_coarse_cnt
;
timetag_coarse
<=
std_logic_vector
(
timetag_coarse_cnt
);
timetag_coarse
<=
wr_tm_cycles_i
when
wr_enabled_i
=
'1'
else
std_logic_vector
(
timetag_coarse_cnt
);
------------------------------------------------------------------------------
-- Last trigger event time-tag
...
...
hdl/ip_cores/timetag_core/rtl/timetag_core_pkg.vhd
View file @
c5f1f0c6
...
...
@@ -8,7 +8,7 @@
-- : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2013-07-05
-- Last update: 2016-06-0
8
-- Last update: 2016-06-0
9
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Package for timetag core
...
...
@@ -55,22 +55,25 @@ package timetag_core_pkg is
------------------------------------------------------------------------------
component
timetag_core
is
port
(
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
trigger_p_i
:
in
std_logic
;
acq_start_p_i
:
in
std_logic
;
acq_stop_p_i
:
in
std_logic
;
acq_end_p_i
:
in
std_logic
;
wr_enabled_i
:
in
std_logic
;
trig_tag_o
:
out
t_timetag
;
wb_adr_i
:
in
std_logic_vector
(
3
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
);
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
trigger_p_i
:
in
std_logic
;
acq_start_p_i
:
in
std_logic
;
acq_stop_p_i
:
in
std_logic
;
acq_end_p_i
:
in
std_logic
;
wr_enabled_i
:
in
std_logic
;
wr_tm_time_valid_i
:
in
std_logic
;
wr_tm_tai_i
:
in
std_logic_vector
(
39
downto
0
);
wr_tm_cycles_i
:
in
std_logic_vector
(
27
downto
0
);
trig_tag_o
:
out
t_timetag
;
wb_adr_i
:
in
std_logic_vector
(
3
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
);
end
component
timetag_core
;
end
timetag_core_pkg
;
...
...
hdl/spec/rtl/carrier_csr.vhd
View file @
c5f1f0c6
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : T
ue May 17 11:36:06
2016
-- Created : T
hu Jun 9 13:40:05
2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
...
...
@@ -47,6 +47,8 @@ entity carrier_csr is
carrier_csr_ctrl_led_red_o
:
out
std_logic
;
-- Port for BIT field: 'DAC clear' in reg: 'Control'
carrier_csr_ctrl_dac_clr_n_o
:
out
std_logic
;
-- Port for BIT field: 'White Rabbit enable' in reg: 'Control'
carrier_csr_ctrl_wrabbit_en_o
:
out
std_logic
;
-- Port for BIT field: 'State of the reset line' in reg: 'Reset Register'
carrier_csr_rst_fmc0_o
:
out
std_logic
);
...
...
@@ -57,6 +59,7 @@ architecture syn of carrier_csr is
signal
carrier_csr_ctrl_led_green_int
:
std_logic
;
signal
carrier_csr_ctrl_led_red_int
:
std_logic
;
signal
carrier_csr_ctrl_dac_clr_n_int
:
std_logic
;
signal
carrier_csr_ctrl_wrabbit_en_int
:
std_logic
;
signal
carrier_csr_rst_fmc0_int
:
std_logic
;
signal
ack_sreg
:
std_logic_vector
(
9
downto
0
);
signal
rddata_reg
:
std_logic_vector
(
31
downto
0
);
...
...
@@ -88,6 +91,7 @@ begin
carrier_csr_ctrl_led_green_int
<=
'0'
;
carrier_csr_ctrl_led_red_int
<=
'0'
;
carrier_csr_ctrl_dac_clr_n_int
<=
'0'
;
carrier_csr_ctrl_wrabbit_en_int
<=
'0'
;
carrier_csr_rst_fmc0_int
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
-- advance the ACK generator shift register
...
...
@@ -151,11 +155,12 @@ begin
carrier_csr_ctrl_led_green_int
<=
wrdata_reg
(
0
);
carrier_csr_ctrl_led_red_int
<=
wrdata_reg
(
1
);
carrier_csr_ctrl_dac_clr_n_int
<=
wrdata_reg
(
2
);
carrier_csr_ctrl_wrabbit_en_int
<=
wrdata_reg
(
3
);
end
if
;
rddata_reg
(
0
)
<=
carrier_csr_ctrl_led_green_int
;
rddata_reg
(
1
)
<=
carrier_csr_ctrl_led_red_int
;
rddata_reg
(
2
)
<=
carrier_csr_ctrl_dac_clr_n_int
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
3
)
<=
carrier_csr_ctrl_wrabbit_en_int
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
...
...
@@ -250,6 +255,8 @@ begin
carrier_csr_ctrl_led_red_o
<=
carrier_csr_ctrl_led_red_int
;
-- DAC clear
carrier_csr_ctrl_dac_clr_n_o
<=
carrier_csr_ctrl_dac_clr_n_int
;
-- White Rabbit enable
carrier_csr_ctrl_wrabbit_en_o
<=
carrier_csr_ctrl_wrabbit_en_int
;
-- State of the reset line
carrier_csr_rst_fmc0_o
<=
carrier_csr_rst_fmc0_int
;
rwaddr_reg
<=
wb_adr_i
;
...
...
hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
View file @
c5f1f0c6
...
...
@@ -8,7 +8,7 @@
-- : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-02-24
-- Last update: 2016-0
5-18
-- Last update: 2016-0
6-09
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Top entity of FMC ADC 100Ms/s design for Simple PCIe FMC
...
...
@@ -182,7 +182,7 @@ architecture rtl of spec_top_fmc_adc_100Ms is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component
carrier_csr
component
carrier_csr
is
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
...
...
@@ -205,6 +205,7 @@ architecture rtl of spec_top_fmc_adc_100Ms is
carrier_csr_ctrl_led_green_o
:
out
std_logic
;
carrier_csr_ctrl_led_red_o
:
out
std_logic
;
carrier_csr_ctrl_dac_clr_n_o
:
out
std_logic
;
carrier_csr_ctrl_wrabbit_en_o
:
out
std_logic
;
carrier_csr_rst_fmc0_o
:
out
std_logic
);
end
component
carrier_csr
;
...
...
@@ -352,14 +353,14 @@ architecture rtl of spec_top_fmc_adc_100Ms is
signal
ddr_clk_buf
:
std_logic
;
-- Reset
signal
powerup_arst_n
:
std_logic
:
=
'0'
;
signal
powerup_clk_in
:
std_logic_vector
(
2
downto
0
);
signal
powerup_rst_out
:
std_logic_vector
(
2
downto
0
);
signal
sys_rst_62_5_n
:
std_logic
;
signal
sys_rst_125_n
:
std_logic
;
signal
sw_rst_fmc0
:
std_logic
:
=
'1'
;
signal
fmc0_rst_n
:
std_logic
;
signal
ddr_rst_n
:
std_logic
;
signal
powerup_arst_n
:
std_logic
:
=
'0'
;
signal
powerup_clk_in
:
std_logic_vector
(
2
downto
0
);
signal
powerup_rst_out
:
std_logic_vector
(
2
downto
0
);
signal
sys_rst_62_5_n
:
std_logic
;
signal
sys_rst_125_n
:
std_logic
;
signal
sw_rst_fmc0
:
std_logic
:
=
'1'
;
signal
fmc0_rst_n
:
std_logic
;
signal
ddr_rst_n
:
std_logic
;
-- Wishbone buse(s) from crossbar master port(s)
signal
cnx_master_out
:
t_wishbone_master_out_array
(
c_NUM_WB_MASTERS
-1
downto
0
);
...
...
@@ -446,6 +447,8 @@ architecture rtl of spec_top_fmc_adc_100Ms is
signal
led_pwm_cnt
:
unsigned
(
16
downto
0
);
signal
led_pwm
:
std_logic
;
-- White Rabbit
signal
wrabbit_en
:
std_logic
;
begin
...
...
@@ -728,6 +731,7 @@ begin
carrier_csr_ctrl_led_green_o
=>
led_green
,
carrier_csr_ctrl_led_red_o
=>
led_red
,
carrier_csr_ctrl_dac_clr_n_o
=>
open
,
carrier_csr_ctrl_wrabbit_en_o
=>
wrabbit_en
,
carrier_csr_rst_fmc0_o
=>
sw_rst_fmc0
);
...
...
@@ -865,7 +869,9 @@ begin
mezz_one_wire_b
=>
adc0_one_wire_b
,
sys_scl_b
=>
fmc0_sys_scl_b
,
sys_sda_b
=>
fmc0_sys_sda_b
sys_sda_b
=>
fmc0_sys_sda_b
,
wr_enable_i
=>
wrabbit_en
);
-- Unused wishbone signals
...
...
hdl/spec/wb_gen/carrier_csr.h
View file @
c5f1f0c6
...
...
@@ -3,7 +3,7 @@
* File : carrier_csr.h
* Author : auto-generated by wbgen2 from carrier_csr.wb
* Created : T
ue May 17 11:36:06
2016
* Created : T
hu Jun 9 13:40:05
2016
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
...
...
@@ -76,6 +76,9 @@
/* definitions for field: DAC clear in reg: Control */
#define CARRIER_CSR_CTRL_DAC_CLR_N WBGEN2_GEN_MASK(2, 1)
/* definitions for field: White Rabbit enable in reg: Control */
#define CARRIER_CSR_CTRL_WRABBIT_EN WBGEN2_GEN_MASK(3, 1)
/* definitions for register: Reset Register */
/* definitions for field: State of the reset line in reg: Reset Register */
...
...
hdl/spec/wb_gen/carrier_csr.htm
View file @
c5f1f0c6
...
...
@@ -390,6 +390,23 @@ carrier_csr_ctrl_dac_clr_n_o
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
carrier_csr_ctrl_wrabbit_en_o
</td>
<td
class=
"td_arrow_right"
>
→
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
...
...
@@ -1212,8 +1229,8 @@ CTRL
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unuse
d"
>
-
<td
style=
"border: solid 1px black;"
colspan=
1
class=
"td_fiel
d"
>
WRABBIT_EN
</td>
<td
style=
"border: solid 1px black;"
colspan=
1
class=
"td_field"
>
DAC_CLR_N
...
...
@@ -1239,6 +1256,10 @@ LED_RED
DAC_CLR_N
</b>
[
<i>
read/write
</i>
]: DAC clear
<br>
Active low clear signal for VCXO DACs
<li><b>
WRABBIT_EN
</b>
[
<i>
read/write
</i>
]: White Rabbit enable
<br>
Enable White Rabbit features
</ul>
<a
name=
"RST"
></a>
<h3><a
name=
"sect_3_4"
>
3.4. Reset Register
</a></h3>
...
...
hdl/spec/wb_gen/carrier_csr.wb
View file @
c5f1f0c6
...
...
@@ -111,6 +111,16 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "White Rabbit enable";
description = "Enable White Rabbit features";
prefix = "wrabbit_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
...
...
hdl/svec/rtl/carrier_csr.vhd
View file @
c5f1f0c6
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : T
ue May 17 11:35:37
2016
-- Created : T
hu Jun 9 13:46:23
2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
...
...
@@ -45,6 +45,8 @@ entity carrier_csr is
carrier_csr_stat_ddr1_cal_done_i
:
in
std_logic
;
-- Port for std_logic_vector field: 'Front panel LED manual control' in reg: 'Control'
carrier_csr_ctrl_fp_leds_man_o
:
out
std_logic_vector
(
15
downto
0
);
-- Port for BIT field: 'White Rabbit enable' in reg: 'Control'
carrier_csr_ctrl_wrabbit_en_o
:
out
std_logic
;
-- Port for BIT field: 'State of the FMC 1 reset line' in reg: 'Reset Register'
carrier_csr_rst_fmc0_o
:
out
std_logic
;
-- Port for BIT field: 'State of the FMC 2 reset line' in reg: 'Reset Register'
...
...
@@ -55,6 +57,7 @@ end carrier_csr;
architecture
syn
of
carrier_csr
is
signal
carrier_csr_ctrl_fp_leds_man_int
:
std_logic_vector
(
15
downto
0
);
signal
carrier_csr_ctrl_wrabbit_en_int
:
std_logic
;
signal
carrier_csr_rst_fmc0_int
:
std_logic
;
signal
carrier_csr_rst_fmc1_int
:
std_logic
;
signal
ack_sreg
:
std_logic_vector
(
9
downto
0
);
...
...
@@ -85,6 +88,7 @@ begin
ack_in_progress
<=
'0'
;
rddata_reg
<=
"00000000000000000000000000000000"
;
carrier_csr_ctrl_fp_leds_man_int
<=
"0000000000000000"
;
carrier_csr_ctrl_wrabbit_en_int
<=
'0'
;
carrier_csr_rst_fmc0_int
<=
'0'
;
carrier_csr_rst_fmc1_int
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
...
...
@@ -147,9 +151,10 @@ begin
when
"10"
=>
if
(
wb_we_i
=
'1'
)
then
carrier_csr_ctrl_fp_leds_man_int
<=
wrdata_reg
(
15
downto
0
);
carrier_csr_ctrl_wrabbit_en_int
<=
wrdata_reg
(
16
);
end
if
;
rddata_reg
(
15
downto
0
)
<=
carrier_csr_ctrl_fp_leds_man_int
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
16
)
<=
carrier_csr_ctrl_wrabbit_en_int
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
...
...
@@ -229,6 +234,8 @@ begin
-- DDR3 bank 5 calibration status
-- Front panel LED manual control
carrier_csr_ctrl_fp_leds_man_o
<=
carrier_csr_ctrl_fp_leds_man_int
;
-- White Rabbit enable
carrier_csr_ctrl_wrabbit_en_o
<=
carrier_csr_ctrl_wrabbit_en_int
;
-- State of the FMC 1 reset line
carrier_csr_rst_fmc0_o
<=
carrier_csr_rst_fmc0_int
;
-- State of the FMC 2 reset line
...
...
hdl/svec/rtl/svec_top_fmc_adc_100Ms.vhd
View file @
c5f1f0c6
...
...
@@ -8,7 +8,7 @@
-- : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2013-07-04
-- Last update: 2016-0
5-18
-- Last update: 2016-0
6-09
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Top entity of FMC ADC 100Ms/s design for Simple VME FMC
...
...
@@ -261,7 +261,7 @@ architecture rtl of svec_top_fmc_adc_100Ms is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component
carrier_csr
component
carrier_csr
is
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
...
...
@@ -283,9 +283,9 @@ architecture rtl of svec_top_fmc_adc_100Ms is
carrier_csr_stat_ddr0_cal_done_i
:
in
std_logic
;
carrier_csr_stat_ddr1_cal_done_i
:
in
std_logic
;
carrier_csr_ctrl_fp_leds_man_o
:
out
std_logic_vector
(
15
downto
0
);
carrier_csr_ctrl_wrabbit_en_o
:
out
std_logic
;
carrier_csr_rst_fmc0_o
:
out
std_logic
;
carrier_csr_rst_fmc1_o
:
out
std_logic
);
carrier_csr_rst_fmc1_o
:
out
std_logic
);
end
component
carrier_csr
;
component
fmc_adc_eic
...
...
@@ -548,6 +548,8 @@ architecture rtl of svec_top_fmc_adc_100Ms is
signal
led_pwm_cnt
:
unsigned
(
16
downto
0
);
signal
led_pwm
:
std_logic
;
-- White Rabbit
signal
wrabbit_en
:
std_logic
;
begin
...
...
@@ -839,6 +841,7 @@ begin
carrier_csr_stat_ddr0_cal_done_i
=>
ddr0_calib_done
,
carrier_csr_stat_ddr1_cal_done_i
=>
ddr1_calib_done
,
carrier_csr_ctrl_fp_leds_man_o
=>
led_state_man
,
carrier_csr_ctrl_wrabbit_en_o
=>
wrabbit_en
,
carrier_csr_rst_fmc0_o
=>
sw_rst_fmc0
,
carrier_csr_rst_fmc1_o
=>
sw_rst_fmc1
);
...
...
@@ -945,7 +948,10 @@ begin
mezz_one_wire_b
=>
adc0_one_wire_b
,
sys_scl_b
=>
fmc0_scl_b
,
sys_sda_b
=>
fmc0_sda_b
sys_sda_b
=>
fmc0_sda_b
,
wr_enable_i
=>
wrabbit_en
);
-- Unused wishbone signals
...
...
@@ -1031,7 +1037,10 @@ begin
mezz_one_wire_b
=>
adc1_one_wire_b
,
sys_scl_b
=>
fmc1_scl_b
,
sys_sda_b
=>
fmc1_sda_b
sys_sda_b
=>
fmc1_sda_b
,
wr_enable_i
=>
wrabbit_en
);
-- Unused wishbone signals
...
...
hdl/svec/wb_gen/carrier_csr.h
View file @
c5f1f0c6
...
...
@@ -3,7 +3,7 @@
* File : carrier_csr.h
* Author : auto-generated by wbgen2 from carrier_csr.wb
* Created : T
ue May 17 11:35:37
2016
* Created : T
hu Jun 9 13:46:23
2016
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
...
...
@@ -76,6 +76,9 @@
#define CARRIER_CSR_CTRL_FP_LEDS_MAN_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define CARRIER_CSR_CTRL_FP_LEDS_MAN_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: White Rabbit enable in reg: Control */
#define CARRIER_CSR_CTRL_WRABBIT_EN WBGEN2_GEN_MASK(16, 1)
/* definitions for register: Reset Register */
/* definitions for field: State of the FMC 1 reset line in reg: Reset Register */
...
...
hdl/svec/wb_gen/carrier_csr.htm
View file @
c5f1f0c6
...
...
@@ -373,6 +373,23 @@ carrier_csr_ctrl_fp_leds_man_o[15:0]
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
carrier_csr_ctrl_wrabbit_en_o
</td>
<td
class=
"td_arrow_right"
>
→
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
...
...
@@ -1117,8 +1134,8 @@ CTRL
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unuse
d"
>
-
<td
style=
"border: solid 1px black;"
colspan=
1
class=
"td_fiel
d"
>
WRABBIT_EN
</td>
</tr>
</table>
...
...
@@ -1235,6 +1252,10 @@ FP_LEDS_MAN[7:0]
FP_LEDS_MAN
</b>
[
<i>
read/write
</i>
]: Front panel LED manual control
<br>
Height front panel LED, two bits per LED.
<br>
00 = OFF
<br>
01 = Green
<br>
10 = Red
<br>
11 = Orange
<li><b>
WRABBIT_EN
</b>
[
<i>
read/write
</i>
]: White Rabbit enable
<br>
Enable White Rabbit features
</ul>
<a
name=
"RST"
></a>
<h3><a
name=
"sect_3_4"
>
3.4. Reset Register
</a></h3>
...
...
hdl/svec/wb_gen/carrier_csr.wb
View file @
c5f1f0c6
...
...
@@ -103,6 +103,16 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "White Rabbit enable";
description = "Enable White Rabbit features";
prefix = "wrabbit_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment