Merge branch 'release/v5.0.0.rc7' into master

bdfff5dd · Federico Vaga · c8295403 · 45f25d71 · bdfff5dd · bdfff5dd
Commit bdfff5dd authored Sep 23, 2020 by Federico Vaga
1000 changed files
--- a/.gitignore
+++ b/.gitignore
@@ -69,8 +69,40 @@ hdl/svec/sim/testbench/top/transcript
 hdl/svec/sim/testbench/top/vsim.wlf
 hdl/svec/sim/testbench/top/vsim_stacktrace.vstf
 hdl/svec/sim/testbench/top/work/
-doc/manual/*.html
+doc/manual/fmcadc100m14b4cha_gateware_manual.info
+doc/manual/fmcadc100m14b4cha_gateware_manual.pdf
+doc/manual/fmcadc100m14b4cha_gateware_manual.txt
 *.texi
 *.aux
 *.log
 *.toc
+*~
+.*cmd
+.*ersions
+*.o
+*.ko
+*.order
+*.symvers
+*.mod.c
+*.mod
+*.o.d
+*.tmp
+*.lof
+*.bib
+*.bbl
+*.blg
+*.out
+*.a
+\#*\#
+*.sh
+Makefile.specific
+# eclipse files
+.pydevproject
+.cproject
+.project
+.settings
+TAGS*
+*.unsigned
+GTAGS
+GPATH
+GRTAGS
--- a/.gitmodules
+++ b/.gitmodules
 [submodule "hdl/ip_cores/general-cores"]
 	path = hdl/ip_cores/general-cores
-	url = git://ohwr.org/hdl-core-lib/general-cores.git
+	url = https://ohwr.org/project/general-cores.git
 [submodule "hdl/ip_cores/ddr3-sp6-core"]
 	path = hdl/ip_cores/ddr3-sp6-core
-	url = git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git
+	url = https://ohwr.org/project/ddr3-sp6-core.git
 [submodule "hdl/ip_cores/gn4124-core"]
 	path = hdl/ip_cores/gn4124-core
-	url = git://ohwr.org/hdl-core-lib/gn4124-core.git
+	url = https://ohwr.org/project/gn4124-core.git
 [submodule "hdl/ip_cores/vme64x-core"]
 	path = hdl/ip_cores/vme64x-core
-	url = git://ohwr.org/hdl-core-lib/vme64x-core.git
+	url = https://ohwr.org/project/vme64x-core.git
+[submodule "hdl/ip_cores/wr-cores"]
+	path = hdl/ip_cores/wr-cores
+	url = https://ohwr.org/project/wr-cores.git
+[submodule "hdl/ip_cores/spec"]
+	path = hdl/ip_cores/spec
+	url = https://ohwr.org/project/spec.git
+[submodule "hdl/ip_cores/svec"]
+	path = hdl/ip_cores/svec
+	url = https://ohwr.org/project/svec.git
--- a/LICENSES/GPL-2.0-or-later.txt
+++ b/LICENSES/GPL-2.0-or-later.txt
--- a/LICENSES/GPL-3.0-or-later.txt
+++ b/LICENSES/GPL-3.0-or-later.txt
--- a/Manifest.py
+++ b/Manifest.py
+modules = {
+    "local" : [
+        "hdl/rtl",
+        "hdl/platform",
+    ],
+}
--- a/distribution/.gitignore
+++ b/distribution/.gitignore
+build/
\ No newline at end of file
--- a/distribution/Makefile
+++ b/distribution/Makefile
+TOP_DIR ?= ..
+DRIVER_NAME := fmc-adc-100m14b4ch
+VERSION := $(shell git describe --abbrev=0)
+DIR_NAME := $(DRIVER_NAME)-$(VERSION)
+KEEP_TEMP ?= n
+BUILD ?= $(abspath build)
+BUILD_DKMS := $(BUILD)/dkms
+BUILD_DKMSSOURCE := $(BUILD_DKMS)/source
+BUILD_DKMSTREE := $(BUILD_DKMS)/tree
+
+
+DKMS_OPT := --dkmstree $(BUILD_DKMSTREE) -m $(DRIVER_NAME)/$(VERSION)
+
+all: kernel
+
+kernel: dkms-tar dkms-rpm
+
+dkms-tree:
+	@mkdir -p $(BUILD_DKMSSOURCE)
+	@mkdir -p $(BUILD_DKMSTREE)
+
+dkms-src: dkms-tree
+	$(eval $@_dir := $(BUILD_DKMSSOURCE)/$(DRIVER_NAME)-$(VERSION))
+	$(eval $@_src := $(shell git ls-tree -r --name-only HEAD $(TOP_DIR)/software/kernel/))
+	@mkdir -p $($@_dir)
+	@cp $(TOP_DIR)/distribution/dkms.conf $($@_dir)
+	@cp $(TOP_DIR)/distribution/fmc-adc-100m14b4ch-dkms-mkrpm.spec $($@_dir)
+	@cp $($@_src) $($@_dir)
+	@cp $(TOP_DIR)/LICENSES/GPL-2.0-or-later.txt $($@_dir)/LICENSE
+	@sed -r -i -e "s/^GIT_VERSION\s=\s.*/GIT_VERSION = $(VERSION)/" $($@_dir)/Makefile
+	@sed -r -i -e "s/@PKGVER@/$(VERSION)/g" -e "s/@PKGNAME@/$(DRIVER_NAME)/g" $($@_dir)/dkms.conf
+
+dkms-add: dkms-src
+	@dkms add $(DKMS_OPT) --sourcetree $(BUILD_DKMSSOURCE)
+
+dkms-tar: dkms-add
+	@dkms mktarball $(DKMS_OPT) --source-only
+
+dkms-rpm: dkms-add
+	@dkms mkrpm $(DKMS_OPT) --source-only
+
+clean:
+	@rm -rf $(BUILD)
+
+.PHONY: dkmstree dkms-add kernel-dkms-tar
--- a/distribution/dkms.conf
+++ b/distribution/dkms.conf
+PACKAGE_NAME="@PKGNAME@"
+PACKAGE_VERSION="@PKGVER@"
+CLEAN="make KVERSION=$kernelver DKMSTREE=$dkms_tree DKMS=1 clean"
+MAKE[0]="make KVERSION=$kernelver DKMSTREE=$dkms_tree DKMS=1"
+BUILT_MODULE_NAME[0]="@PKGNAME@"
+DEST_MODULE_LOCATION[0]="/updates"
+AUTOINSTALL="yes"
+BUILD_DEPENDS[0]="zio"
\ No newline at end of file
--- a/distribution/fmc-adc-100m14b4ch-dkms-mkrpm.spec
+++ b/distribution/fmc-adc-100m14b4ch-dkms-mkrpm.spec
+# Mainline copied from the template, added requirements
+
+%{?!module_name: %{error: You did not specify a module name (%%module_name)}}
+%{?!version: %{error: You did not specify a module version (%%version)}}
+%{?!kernel_versions: %{error: You did not specify kernel versions (%%kernel_version)}}
+%{?!packager: %define packager DKMS <dkms-devel@lists.us.dell.com>}
+%{?!license: %define license Unknown}
+%{?!_dkmsdir: %define _dkmsdir /var/lib/dkms}
+%{?!_srcdir: %define _srcdir %_prefix/src}
+%{?!_datarootdir: %define _datarootdir %{_datadir}}
+
+Summary:	%{module_name} %{version} dkms package
+Name:		%{module_name}
+Version:	%{version}
+License:	%license
+Release:	1dkms
+BuildArch:	noarch
+Group:		System/Kernel
+Requires: 	dkms >= 1.95, zio >= 1.4
+BuildRequires: 	dkms
+BuildRoot: 	%{_tmppath}/%{name}-%{version}-%{release}-root/
+
+%description
+Kernel modules for %{module_name} %{version} in a DKMS wrapper.
+
+%prep
+if [ "%mktarball_line" != "none" ]; then
+        /usr/sbin/dkms mktarball -m %module_name -v %version %mktarball_line --archive `basename %{module_name}-%{version}.dkms.tar.gz`
+        cp -af %{_dkmsdir}/%{module_name}/%{version}/tarball/`basename %{module_name}-%{version}.dkms.tar.gz` %{module_name}-%{version}.dkms.tar.gz
+fi
+
+%install
+if [ "$RPM_BUILD_ROOT" != "/" ]; then
+        rm -rf $RPM_BUILD_ROOT
+fi
+mkdir -p $RPM_BUILD_ROOT/%{_srcdir}
+mkdir -p $RPM_BUILD_ROOT/%{_datarootdir}/%{module_name}
+
+if [ -d %{_sourcedir}/%{module_name}-%{version} ]; then
+        cp -Lpr %{_sourcedir}/%{module_name}-%{version} $RPM_BUILD_ROOT/%{_srcdir}
+fi
+
+if [ -f %{module_name}-%{version}.dkms.tar.gz ]; then
+        install -m 644 %{module_name}-%{version}.dkms.tar.gz $RPM_BUILD_ROOT/%{_datarootdir}/%{module_name}
+fi
+
+if [ -f %{_sourcedir}/common.postinst ]; then
+        install -m 755 %{_sourcedir}/common.postinst $RPM_BUILD_ROOT/%{_datarootdir}/%{module_name}/postinst
+fi
+
+%clean
+if [ "$RPM_BUILD_ROOT" != "/" ]; then
+        rm -rf $RPM_BUILD_ROOT
+fi
+
+%post
+for POSTINST in %{_prefix}/lib/dkms/common.postinst %{_datarootdir}/%{module_name}/postinst; do
+        if [ -f $POSTINST ]; then
+                $POSTINST %{module_name} %{version} %{_datarootdir}/%{module_name}
+                exit $?
+        fi
+        echo "WARNING: $POSTINST does not exist."
+done
+echo -e "ERROR: DKMS version is too old and %{module_name} was not"
+echo -e "built with legacy DKMS support."
+echo -e "You must either rebuild %{module_name} with legacy postinst"
+echo -e "support or upgrade DKMS to a more current version."
+exit 1
+
+%preun
+echo -e
+echo -e "Uninstall of %{module_name} module (version %{version}) beginning:"
+dkms remove -m %{module_name} -v %{version} --all --rpm_safe_upgrade
+exit 0
+
+%files
+%defattr(-,root,root)
+%{_srcdir}
+%{_datarootdir}/%{module_name}/
+
+%changelog
+* %(date "+%a %b %d %Y") %packager %{version}-%{release}
+- Automatic build by DKMS
+
--- a/doc/.gitignore
+++ b/doc/.gitignore
+*~
+*.aux
+*.cp
+*.cps
+*.fn
+*.fns
+*.html
+*.info
+*.ky
+*.log
+/*.pdf
+*.pg
+*.texi
+*.toc
+*.tp
+/*.txt
+*.vr
+_build
--- a/doc/Makefile
+++ b/doc/Makefile
+# Minimal makefile for Sphinx documentation
+#
+
+# You can set these variables from the command line.
+SPHINXOPTS    =
+SPHINXBUILD   = sphinx-build
+SPHINXPROJ    = FMCADC100M14bit4Channel
+SOURCEDIR     = .
+BUILDDIR      = _build
+
+# Put it first so that "make" without argument is like "make help".
+help:
+	@$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
+
+.PHONY: help Makefile
+
+# Catch-all target: route all unknown targets to Sphinx using the new
+# "make mode" option.  $(O) is meant as a shortcut for $(SPHINXOPTS).
+%: Makefile
+	@$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
\ No newline at end of file
--- a/doc/conf.py
+++ b/doc/conf.py
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# FMC ADC 100M 14 bit 4 Channel documentation build configuration file, created by
+# sphinx-quickstart on Thu Jan 25 09:54:50 2018.
+#
+# This file is execfile()d with the current directory set to its
+# containing dir.
+#
+# Note that not all possible configuration values are present in this
+# autogenerated file.
+#
+# All configuration values have a default; values that are commented out
+# serve to show the default.
+
+# If extensions (or modules to document with autodoc) are in another directory,
+# add these directories to sys.path here. If the directory is relative to the
+# documentation root, use os.path.abspath to make it absolute, like shown here.
+#
+# import os
+# import sys
+# sys.path.insert(0, os.path.abspath('.'))
+
+
+# -- General configuration ------------------------------------------------
+
+# If your documentation needs a minimal Sphinx version, state it here.
+#
+# needs_sphinx = '1.0'
+
+# Add any Sphinx extension module names here, as strings. They can be
+# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
+# ones.
+extensions = ['sphinx.ext.autodoc',
+    'sphinx.ext.todo',
+    'sphinx.ext.coverage',
+    'sphinx.ext.graphviz',]
+
+# Add any paths that contain templates here, relative to this directory.
+templates_path = ['_templates']
+
+# The suffix(es) of source filenames.
+# You can specify multiple suffix as a list of string:
+#
+# source_suffix = ['.rst', '.md']
+source_suffix = '.rst'
+
+# The master toctree document.
+master_doc = 'index'
+
+# General information about the project.
+project = 'FMC ADC 100M 14 bit 4 Channel'
+copyright = '2018, Federico Vaga <federico.vaga@cern.ch>'
+author = 'Federico Vaga <federico.vaga@cern.ch>'
+
+# The version info for the project you're documenting, acts as replacement for
+# |version| and |release|, also used in various other places throughout the
+# built documents.
+#
+# The short X.Y version.
+version = '5.0'
+# The full version, including alpha/beta/rc tags.
+release = '5.0'
+
+# The language for content autogenerated by Sphinx. Refer to documentation
+# for a list of supported languages.
+#
+# This is also used if you do content translation via gettext catalogs.
+# Usually you set "language" from the command line for these cases.
+language = None
+
+# List of patterns, relative to source directory, that match files and
+# directories to ignore when looking for source files.
+# This patterns also effect to html_static_path and html_extra_path
+exclude_patterns = ['_build', 'Thumbs.db', '.DS_Store']
+
+# The name of the Pygments (syntax highlighting) style to use.
+pygments_style = 'sphinx'
+
+# If true, `todo` and `todoList` produce output, else they produce nothing.
+todo_include_todos = True
+
+
+# -- Options for HTML output ----------------------------------------------
+
+# The theme to use for HTML and HTML Help pages.  See the documentation for
+# a list of builtin themes.
+#
+#html_theme = 'alabaster'
+html_theme = "sphinx_rtd_theme"
+
+# Theme options are theme-specific and customize the look and feel of a theme
+# further.  For a list of options available for each theme, see the
+# documentation.
+#
+# html_theme_options = {}
+
+# Add any paths that contain custom static files (such as style sheets) here,
+# relative to this directory. They are copied after the builtin static files,
+# so a file named "default.css" will overwrite the builtin "default.css".
+html_static_path = ['_static']
+
+# Custom sidebar templates, must be a dictionary that maps document names
+# to template names.
+#
+# This is required for the alabaster theme
+# refs: http://alabaster.readthedocs.io/en/latest/installation.html#sidebars
+html_sidebars = {
+    '**': [
+        'relations.html',  # needs 'show_related': True theme option to display
+        'searchbox.html',
+    ]
+}
+
+
+# -- Options for HTMLHelp output ------------------------------------------
+
+# Output file base name for HTML help builder.
+htmlhelp_basename = 'FMCADC100M14bit4Channeldoc'
+
+
+# -- Options for LaTeX output ---------------------------------------------
+
+latex_elements = {
+    # The paper size ('letterpaper' or 'a4paper').
+    #
+    # 'papersize': 'letterpaper',
+
+    # The font size ('10pt', '11pt' or '12pt').
+    #
+    # 'pointsize': '10pt',
+
+    # Additional stuff for the LaTeX preamble.
+    #
+    # 'preamble': '',
+
+    # Latex figure (float) alignment
+    #
+    # 'figure_align': 'htbp',
+}
+
+# Grouping the document tree into LaTeX files. List of tuples
+# (source start file, target name, title,
+#  author, documentclass [howto, manual, or own class]).
+latex_documents = [
+    (master_doc, 'FMCADC100M14bit4Channel.tex', 'FMC ADC 100M 14 bit 4 Channel Documentation',
+     'Federico Vaga \\textless{}federico.vaga@cern.ch\\textgreater{}', 'manual'),
+]
+
+
+# -- Options for manual page output ---------------------------------------
+
+# One entry per manual page. List of tuples
+# (source start file, name, description, authors, manual section).
+man_pages = [
+    (master_doc, 'fmcadc100m14bit4channel', 'FMC ADC 100M 14 bit 4 Channel Documentation',
+     [author], 1)
+]
+
+
+# -- Options for Texinfo output -------------------------------------------
+
+# Grouping the document tree into Texinfo files. List of tuples
+# (source start file, target name, title, author,
+#  dir menu entry, description, category)
+texinfo_documents = [
+    (master_doc, 'FMCADC100M14bit4Channel', 'FMC ADC 100M 14 bit 4 Channel Documentation',
+     author, 'FMCADC100M14bit4Channel', 'One line description of project.',
+     'Miscellaneous'),
+]
+
+
+
+# -- Options for Epub output ----------------------------------------------
+
+# Bibliographic Dublin Core info.
+epub_title = project
+epub_author = author
+epub_publisher = author
+epub_copyright = copyright
+
+# The unique identifier of the text. This can be a ISBN number
+# or the project homepage.
+#
+# epub_identifier = ''
+
+# A unique identification for the text.
+#
+# epub_uid = ''
+
+# A list of files that should not be packed into the epub file.
+epub_exclude_files = ['search.html']
+
+
+smart_quotes = False
--- a/doc/img/config-if.gif
+++ b/doc/img/config-if.gif
--- a/doc/img/config-if.pdf
+++ b/doc/img/config-if.pdf
--- a/doc/img/config-if.txt
+++ b/doc/img/config-if.txt
+Two snapshots of fa-config-if
--- a/doc/img/fmc-adc-call.graphml
+++ b/doc/img/fmc-adc-call.graphml
--- a/doc/img/fmc-adc-call.pdf
+++ b/doc/img/fmc-adc-call.pdf
--- a/doc/img/fmc-adc-fsm.graphml
+++ b/doc/img/fmc-adc-fsm.graphml
--- a/doc/img/fmc-adc-fsm.pdf
+++ b/doc/img/fmc-adc-fsm.pdf
--- a/doc/img/fmc-adc-hierarchy.graphml
+++ b/doc/img/fmc-adc-hierarchy.graphml
--- a/doc/img/fmc-adc-hierarchy.pdf
+++ b/doc/img/fmc-adc-hierarchy.pdf
--- a/doc/img/interleaved.graphml
+++ b/doc/img/interleaved.graphml
--- a/doc/img/interleaved.pdf
+++ b/doc/img/interleaved.pdf
--- a/doc/img/library.graphml
+++ b/doc/img/library.graphml
--- a/doc/img/library.pdf
+++ b/doc/img/library.pdf
--- a/doc/index.rst
+++ b/doc/index.rst
+..
+  SPDX-License-Identifier: CC-BY-SA-4.0
+  SPDX-FileCopyrightText: 2020 CERN
+
+Welcome to FMC ADC 100M 14 bit 4 Channel's documentation!
+=========================================================
+This is the user manual of the driver for the `FMC ADC 100M 14b 4cha`_
+board developed on the `Open Hardware Repository`_. FMC is the form
+factor of the card, ADC is its role, 100M means it can acquire
+100Msample per second, 14b is the numbers of meaningful bits and 4cha
+states it has 4 input channels (plus a trigger input).
+
+.. _`Open Hardware Repository`: http://www.ohwr.org/
+.. _`FMC ADC 100M 14b 4cha`: http://www.ohwr.org/projects/fmc-adc-100m14b4cha
+
+.. toctree::
+   :maxdepth: 2
+   :caption: Contents:
+
+   software/index
+
+Indices and tables
+==================
+
+* :ref:`genindex`
+* :ref:`modindex`
+* :ref:`search`
--- a/doc/manual/fmc_adc_100Ms_csr.tex
+++ b/doc/manual/fmc_adc_100Ms_csr.tex
--- a/doc/manual/fmcadc100m14b4cha_gateware_manual.in
+++ b/doc/manual/fmcadc100m14b4cha_gateware_manual.in
@@ -735,6 +735,13 @@ The frame rate signal is used to align the de-serialiser to data words.
 The four channel data (16-bit) are concatenated together to form a 64-bit vector.
 As shown in @ref{fig:ltc2174_mode}, the two LSB bits of a data word are always set to zero.

+@strong{Important:} Upon reset the ADC defaults to ``offset binary''
+representation for the channel data. However, the ADC core expects
+``two's complement''. Therefore, it is important to change the
+relevant configuration register in the ADC itself. When using the
+provided FMC-ADC driver, this is done automatically during driver
+initialisation.
+
 @c ==========================================================================
 @section Control and Status Registers

@@ -956,7 +963,7 @@ As for the ADC correction values, there is one pair (offset, gain) of DAC correc
 Below is the formula to calculate the corrected DAC value (applying gain and offset correction):
 @example
 @group
-c_val = ((val + offset) * gain/0x8000) - 0x8000
+c_val = ((val + offset) * gain/0x8000) + 0x8000
 where:
 c_val  = corrected value to write to DAC (16-bit unsigned)
 val    = value from user (16-bit signed)

--- a/doc/manual/spec/carrier_csr.tex
+++ b/doc/manual/spec/carrier_csr.tex
@@ -105,11 +105,11 @@ Controls software reset of the mezzanine including the ddr interface and the tim
 @headitem Bits @tab Access @tab Prefix @tab Default @tab Name
 @item @code{0}
 @tab R/W @tab
-@code{FMC0_N}
-@tab @code{X} @tab 
+@code{FMC0}
+@tab @code{0} @tab 
 State of the reset line
 @end multitable
 @multitable @columnfractions 0.15 0.85
 @headitem Field @tab Description
-@item @code{fmc0_n} @tab write 0: FMC is held in reset@* write 1: Normal FMC operation (default)
+@item @code{fmc0} @tab write 0: Normal FMC operation@* 		 write 1: FMC is held in reset
 @end multitable
--- a/doc/manual/svec/carrier_csr.tex
+++ b/doc/manual/svec/carrier_csr.tex
@@ -99,17 +99,17 @@ Controls software reset of the mezzanines including the ddr interface and the ti
 @headitem Bits @tab Access @tab Prefix @tab Default @tab Name
 @item @code{0}
 @tab R/W @tab
-@code{FMC0_N}
-@tab @code{X} @tab 
+@code{FMC0}
+@tab @code{0} @tab 
 State of the FMC 1 reset line
 @item @code{1}
 @tab R/W @tab
-@code{FMC1_N}
-@tab @code{X} @tab 
+@code{FMC1}
+@tab @code{0} @tab 
 State of the FMC 2 reset line
 @end multitable
 @multitable @columnfractions 0.15 0.85
 @headitem Field @tab Description
-@item @code{fmc0_n} @tab write 0: FMC is held in reset@* write 1: Normal FMC operation (default)
-@item @code{fmc1_n} @tab write 0: FMC is held in reset@* write 1: Normal FMC operation (default)
+@item @code{fmc0} @tab write 0: Normal FMC operation@* 		 write 1: FMC is held in reset
+@item @code{fmc1} @tab write 0: Normal FMC operation@* 		 write 1: FMC is held in reset
 @end multitable
--- a/doc/manual/timetag_core_regs.tex
+++ b/doc/manual/timetag_core_regs.tex
--- a/doc/software/driver.rst
+++ b/doc/software/driver.rst
--- a/doc/software/index.rst
+++ b/doc/software/index.rst
+..
+  SPDX-License-Identifier: CC-BY-SA-4.0
+  SPDX-FileCopyrightText: 2020 CERN
+
+============
+The Software
+============
+
+.. toctree::
+   :maxdepth: 1
+   :caption: Contents
+
+   driver
+   tools
--- a/doc/software/tools.rst
+++ b/doc/software/tools.rst
+..
+  SPDX-License-Identifier: CC-BY-SA-4.0
+  SPDX-FileCopyrightText: 2020 CERN
+
+Tools
+=====
+
+The driver is distributed with a few tools living in the ``tools/``
+subdirectory and they do not use any dedicated library, instead
+they do raw accesses to the driver. The programs are meant to provide
+examples about the use of the driver interface.
+
+The generic library `adc-lib`_ supports this driver, so you may want to
+consider to use the generic tools from that library.
+
+.. _`adc-lib`: http://www.ohwr.org/projects/adc-lib
+
+Trigger Configuration
+---------------------
+
+The program ``fau-trg-config`` configures the FMC ADC trigger. The tool
+offers command line parameters to configure every register exported by
+the driver. The help screen for the program summarizes the options::
+
+     # ./tools/fau-trg-config --help
+
+     fau-trg-config [OPTIONS] <DEVICE>
+
+       <DEVICE>: ZIO name of the device to use
+       --pre|-p <value>: number of pre samples
+       --post|-P <value>: number of pre samples
+       --nshots|-n <value>: number of trigger shots
+       --delay|-d <value>: set the ticks delay of the trigger
+       --threshold|-t <value>: set internal trigger threshold
+       --channel|-c <value>: select the internal channel as trigger
+       --external: set to external trigger. The default is the internal trigger.
+       --negative-edge: set internal trigger polarity to negative edge. The default
+                         is positive edge.
+       --enable-sw-trg: enable the software trigger. By default is disabled.
+       --disable-hw-trg: disable the hardware trigger. By default is enabled
+       --force: force all attribute to the program default
+       --help|-h: show this help
+
+     NOTE: The software trigger works only if also hardware trigger is enabled
+
+The tool gets the configuration values from the user and it writes them
+to the corresponding sysfs attributes for the specified device. or
+example, if you want to configure the board for the external trigger and
+3 shots of 10 pre-samples and 100 post-samples, this is the associated
+command line::
+
+     # ./tools/fau-trg-config --external --pre 10 --post 100 --re-enable 2 \
+             adc-100m14b-0200
+
+As shown, the nshot parameter is passed as a number of re-enables,
+because the trigger is initially automatically enabled. This may change
+in the future, for better naming consistency with hardware documentation
+and across tools.
+
+Acquisition Time
+----------------
+
+The program fau-acq-time retrieves the timestamps associated with the
+acquisition. This is the help screen of the program::
+
+     ./tools/fau-acq-time --help
+
+     fau-acq-time [OPTIONS] <DEVICE>
+
+       <DEVICE>: ZIO name of the device to use
+       --last|-l : time between the last trigger and the acquisition end
+       --full|-f : time between the acquisition start and the acquisition end
+       --help|-h: show this help
+
+The program can return two different *types* of acquisition time. The
+value returned by **last** represent the time elapsed between the last
+trigger event and the acquire-end event; this is the time spent during
+the last capture.
+
+The value returned by **full** is the time elapsed between the
+acquisition start event and the acquisition end event, i.e. the total
+time spent waiting for all trigger events and the time spent acquiring
+all samples.
+
+Channel Configuration
+---------------------
+
+The program ``tools/fau-config-if`` is a simple graphic tool that allow to
+select offset and range for the four channels, activate termination and
+see the current value of each channel, every 500ms.
+
+The program open one window for each detected card, and configures it by
+writing to sysfs. Such writes are also reported to stdout (in the
+terminal where you invoked the program), so you can easily copy the
+pathnames in your shell commands.
+
+The figure below shows two instances of the tool, running on the same card
+with device_id 0x200 (your window decorations will be different, according
+to your choice of window manager or desktop environment).
+The first one (at the left) is running under Tk-8.5; the second one shows
+the graphic appearance of Tk-8.4 (and earlier versions). If you prefer the
+older one, run *wish8.4 tools/fau-config-if* instead of
+``tools/fau-config-if`` (or set the previous version as default Tk interpreter).
+
+.. figure:: ../img/config-if.gif
+   :alt: Two snapshots of fa-config-if
+   :align: center
+
+Parallel Port Burst
+-------------------
+
+If you have a Parallel Port you can use it to generate bursts of pulses
+with a software program. This may be useful to test the external
+trigger; you can connect the parallel port to the external trigger of
+the FMC ADC and generate your trigger events with this program
+
+The program parport-burst, part of this package, generates a burst
+according to three command line parameters: the I/O port of the data
+byte of the parallel port, the repeat count and the duration of each
+period. This example makes 1000 pulses of 100 usec each, using the
+physical address of my parallel port (if yours is part of the
+motherboard, the address is ``378``)::
+
+    ./tools/parport-burst dd00 1000 100
+
+Calibration Data
+----------------
+
+The FMC ADC 100M mezzanine stores its calibration data in the FMC
+EEPROM at offset 256. You could you ``hexdump`` to read it:::
+
+
+  $ hexdump -n 108 /sys/bus/zio/devices/adc-100m14b-0021/calibration_data
+  0000000 ffe8 0044 ffc2 ff9d 76bc 7658 7637 769c
+  0000010 1211 ffd7 002e ffa6 ff88 7894 78ae 7887
+  0000020 78ba 121d ff94 ff7e ff36 fef8 7962 7915
+  0000030 7881 7851 122a 0000 fffc 0000 0003 7d1e
+  0000040 7d5f 7e05 7d3c 1211 0000 0000 0000 0000
+  0000050 801b 8014 8018 8014 121d 0000 0000 0000
+  0000060 0000 8303 82dc 82e3 82ce 122a
+
+The output is hard to read, that's why we wrote ``fau-calibration``
+that make the calibration data human readable:::
+
+  $ fau-calibration -f /sys/bus/zio/devices/adc-100m14b-0021/calibration_data
+  ADC Range 10V
+    temperature: 46.250000 C
+    gain: [0x76bc, 0x7658, 0x7637, 0x769c]
+    offset: [0xffffffe8, 0x0044, 0xffffffc2, 0xffffff9d]
+  DAC Range 10V
+    temperature: 46.250000 C
+    gain: [0x7d1e, 0x7d5f, 0x7e05, 0x7d3c]
+    offset: [0x0000, 0xfffffffc, 0x0000, 0x0003]
+  ADC Range 1V
+    temperature: 46.370000 C
+    gain: [0x7894, 0x78ae, 0x7887, 0x78ba]
+    offset: [0xffffffd7, 0x002e, 0xffffffa6, 0xffffff88]
+  DAC Range 1V
+    temperature: 46.370000 C
+    gain: [0x801b, 0x8014, 0x8018, 0x8014]
+    offset: [0x0000, 0x0000, 0x0000, 0x0000]
+  ADC Range 100mV
+    temperature: 46.500000 C
+    gain: [0x7962, 0x7915, 0x7881, 0x7851]
+    offset: [0xffffff94, 0xffffff7e, 0xffffff36, 0xfffffef8]
+  DAC Range 100mV
+    temperature: 46.500000 C
+    gain: [0x8303, 0x82dc, 0x82e3, 0x82ce]
+    offset: [0x0000, 0x0000, 0x0000, 0x0000]
--- a/fmcadc_fw_testing.txt
+++ b/fmcadc_fw_testing.txt
--- a/hdl/LICENSE.txt
+++ b/hdl/LICENSE.txt
--- a/hdl/adc/rtl/Manifest.py
+++ b/hdl/adc/rtl/Manifest.py
-files = [
-    "fmc_adc_mezzanine.vhd",
-    "fmc_adc_mezzanine_pkg.vhd",
-    "fmc_adc_100Ms_core.vhd",
-    "fmc_adc_100Ms_core_pkg.vhd",
-    "fmc_adc_100Ms_csr.vhd",
-    "fmc_adc_eic.vhd",
-    "offset_gain_s.vhd",
-    "var_sat_s.vhd"]
--- a/hdl/adc/rtl/fmc_adc_100Ms_core.vhd
+++ b/hdl/adc/rtl/fmc_adc_100Ms_core.vhd
--- a/hdl/adc/rtl/fmc_adc_100Ms_core_pkg.vhd
+++ b/hdl/adc/rtl/fmc_adc_100Ms_core_pkg.vhd
--- a/hdl/adc/rtl/fmc_adc_100Ms_csr.vhd
+++ b/hdl/adc/rtl/fmc_adc_100Ms_csr.vhd
--- a/hdl/adc/rtl/fmc_adc_eic.vhd
+++ b/hdl/adc/rtl/fmc_adc_eic.vhd
--- a/hdl/adc/rtl/fmc_adc_mezzanine.vhd
+++ b/hdl/adc/rtl/fmc_adc_mezzanine.vhd
--- a/hdl/adc/rtl/fmc_adc_mezzanine_pkg.vhd
+++ b/hdl/adc/rtl/fmc_adc_mezzanine_pkg.vhd
--- a/hdl/adc/rtl/offset_gain.vhd
+++ b/hdl/adc/rtl/offset_gain.vhd
--- a/hdl/adc/rtl/offset_gain_s.vhd
+++ b/hdl/adc/rtl/offset_gain_s.vhd
--- a/hdl/adc/rtl/offset_gain_s_tb.vhd
+++ b/hdl/adc/rtl/offset_gain_s_tb.vhd
--- a/hdl/adc/rtl/offset_gain_tb.vhd
+++ b/hdl/adc/rtl/offset_gain_tb.vhd
--- a/hdl/adc/rtl/var_sat_s.vhd
+++ b/hdl/adc/rtl/var_sat_s.vhd
--- a/hdl/adc/ucf_gen/fmc-adc.pins
+++ b/hdl/adc/ucf_gen/fmc-adc.pins
-
-#
-# Mezzanine top level pin assignment file:
-# syntax: pin FMC_pin_name Core_Pin_name IO_Standard
-# % is replaced with FMC number if the carrier supports more than 1 mezzanine
-#
-
-mezzanine fmc-adc-v5
-
-pin la_n17 adc%_ext_trigger_n_i lvds_25
-pin la_p17 adc%_ext_trigger_p_i lvds_25
-pin la_n0 adc%_dco_n_i lvds_25
-pin la_p0 adc%_dco_p_i lvds_25
-pin la_n1 adc%_fr_n_i lvds_25
-pin la_p1 adc%_fr_p_i lvds_25
-pin la_n14 adc%_outa_n_i[0] lvds_25
-pin la_p14 adc%_outa_p_i[0] lvds_25
-pin la_n15 adc%_outb_n_i[0] lvds_25
-pin la_p15 adc%_outb_p_i[0] lvds_25
-pin la_n16 adc%_outa_n_i[1] lvds_25
-pin la_p16 adc%_outa_p_i[1] lvds_25
-pin la_n13 adc%_outb_n_i[1] lvds_25
-pin la_p13 adc%_outb_p_i[1] lvds_25
-pin la_n10 adc%_outa_n_i[2] lvds_25
-pin la_p10 adc%_outa_p_i[2] lvds_25
-pin la_n9 adc%_outb_n_i[2] lvds_25
-pin la_p9 adc%_outb_p_i[2] lvds_25
-pin la_n7 adc%_outa_n_i[3] lvds_25
-pin la_p7 adc%_outa_p_i[3] lvds_25
-pin la_n5 adc%_outb_n_i[3] lvds_25
-pin la_p5 adc%_outb_p_i[3] lvds_25
-pin la_p25 adc%_spi_din_i lvcmos25
-pin la_n31 adc%_spi_dout_o lvcmos25
-pin la_p31 adc%_spi_sck_o lvcmos25
-pin la_p30 adc%_spi_cs_adc_n_o lvcmos25
-pin la_p32 adc%_spi_cs_dac1_n_o lvcmos25
-pin la_n32 adc%_spi_cs_dac2_n_o lvcmos25
-pin la_p33 adc%_spi_cs_dac3_n_o lvcmos25
-pin la_n33 adc%_spi_cs_dac4_n_o lvcmos25
-pin la_n30 adc%_gpio_dac_clr_n_o lvcmos25
-pin la_n28 adc%_gpio_led_acq_o lvcmos25
-pin la_p28 adc%_gpio_led_trig_o lvcmos25
-pin la_p26 adc%_gpio_ssr_ch1_o[0] lvcmos25
-pin la_n26 adc%_gpio_ssr_ch1_o[1] lvcmos25
-pin la_n27 adc%_gpio_ssr_ch1_o[2] lvcmos25
-pin la_n25 adc%_gpio_ssr_ch1_o[3] lvcmos25
-pin la_p24 adc%_gpio_ssr_ch1_o[4] lvcmos25
-pin la_n24 adc%_gpio_ssr_ch1_o[5] lvcmos25
-pin la_p29 adc%_gpio_ssr_ch1_o[6] lvcmos25
-pin la_p20 adc%_gpio_ssr_ch2_o[0] lvcmos25
-pin la_n19 adc%_gpio_ssr_ch2_o[1] lvcmos25
-pin la_p22 adc%_gpio_ssr_ch2_o[2] lvcmos25
-pin la_n22 adc%_gpio_ssr_ch2_o[3] lvcmos25
-pin la_p21 adc%_gpio_ssr_ch2_o[4] lvcmos25
-pin la_p27 adc%_gpio_ssr_ch2_o[5] lvcmos25
-pin la_n21 adc%_gpio_ssr_ch2_o[6] lvcmos25
-pin la_p8 adc%_gpio_ssr_ch3_o[0] lvcmos25
-pin la_n8 adc%_gpio_ssr_ch3_o[1] lvcmos25
-pin la_p12 adc%_gpio_ssr_ch3_o[2] lvcmos25
-pin la_n12 adc%_gpio_ssr_ch3_o[3] lvcmos25
-pin la_p11 adc%_gpio_ssr_ch3_o[4] lvcmos25
-pin la_n11 adc%_gpio_ssr_ch3_o[5] lvcmos25
-pin la_n20 adc%_gpio_ssr_ch3_o[6] lvcmos25
-pin la_p2 adc%_gpio_ssr_ch4_o[0] lvcmos25
-pin la_n2 adc%_gpio_ssr_ch4_o[1] lvcmos25
-pin la_p3 adc%_gpio_ssr_ch4_o[2] lvcmos25
-pin la_n3 adc%_gpio_ssr_ch4_o[3] lvcmos25
-pin la_p4 adc%_gpio_ssr_ch4_o[4] lvcmos25
-pin la_p6 adc%_gpio_ssr_ch4_o[5] lvcmos25
-pin la_n4 adc%_gpio_ssr_ch4_o[6] lvcmos25
-pin la_n6 adc%_gpio_si570_oe_o lvcmos25
-pin la_n18 adc%_si570_scl_b lvcmos25
-pin la_p18 adc%_si570_sda_b lvcmos25
-pin la_n29 adc%_one_wire_b lvcmos25
-
-
-#eof
--- a/hdl/adc/wb_gen/Makefile
+++ b/hdl/adc/wb_gen/Makefile
-WBGEN2=$(shell which wbgen2)
-RTL=../rtl/
-TEX=../../../doc/manual/
-
-fmc_adc_100Ms_csr:
-	$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
-	$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
-
-fmc_adc_eic:
-	$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
-	$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
--- a/hdl/adc/wb_gen/fmc_adc_100Ms_csr.h
+++ b/hdl/adc/wb_gen/fmc_adc_100Ms_csr.h
--- a/hdl/adc/wb_gen/fmc_adc_100Ms_csr.htm
+++ b/hdl/adc/wb_gen/fmc_adc_100Ms_csr.htm
--- a/hdl/adc/wb_gen/fmc_adc_100Ms_csr.wb
+++ b/hdl/adc/wb_gen/fmc_adc_100Ms_csr.wb
--- a/hdl/adc/wb_gen/fmc_adc_eic.h
+++ b/hdl/adc/wb_gen/fmc_adc_eic.h
--- a/hdl/adc/wb_gen/fmc_adc_eic.htm
+++ b/hdl/adc/wb_gen/fmc_adc_eic.htm
--- a/hdl/adc/wb_gen/fmc_adc_eic.wb
+++ b/hdl/adc/wb_gen/fmc_adc_eic.wb
--- a/hdl/cheby/Makefile
+++ b/hdl/cheby/Makefile
--- a/hdl/cheby/fmc_adc_100Ms_channel_regs.cheby
+++ b/hdl/cheby/fmc_adc_100Ms_channel_regs.cheby
--- a/hdl/cheby/fmc_adc_100Ms_channel_regs.vhd
+++ b/hdl/cheby/fmc_adc_100Ms_channel_regs.vhd
--- a/hdl/cheby/fmc_adc_100Ms_csr.cheby
+++ b/hdl/cheby/fmc_adc_100Ms_csr.cheby
--- a/hdl/cheby/fmc_adc_100Ms_csr.vhd
+++ b/hdl/cheby/fmc_adc_100Ms_csr.vhd
--- a/hdl/cheby/fmc_adc_aux_trigin.cheby
+++ b/hdl/cheby/fmc_adc_aux_trigin.cheby
--- a/hdl/cheby/fmc_adc_aux_trigin.vhd
+++ b/hdl/cheby/fmc_adc_aux_trigin.vhd
--- a/hdl/cheby/fmc_adc_aux_trigout.cheby
+++ b/hdl/cheby/fmc_adc_aux_trigout.cheby
--- a/hdl/cheby/fmc_adc_aux_trigout.vhd
+++ b/hdl/cheby/fmc_adc_aux_trigout.vhd
--- a/hdl/cheby/fmc_adc_eic_regs.cheby
+++ b/hdl/cheby/fmc_adc_eic_regs.cheby
--- a/hdl/cheby/fmc_adc_eic_regs.vhd
+++ b/hdl/cheby/fmc_adc_eic_regs.vhd
--- a/hdl/cheby/fmc_adc_mezzanine_mmap.cheby
+++ b/hdl/cheby/fmc_adc_mezzanine_mmap.cheby
--- a/hdl/cheby/fmc_adc_mezzanine_mmap.vhd
+++ b/hdl/cheby/fmc_adc_mezzanine_mmap.vhd
--- a/hdl/cheby/spec_ref_fmc_adc_100Ms_mmap.cheby
+++ b/hdl/cheby/spec_ref_fmc_adc_100Ms_mmap.cheby
--- a/hdl/cheby/spec_ref_fmc_adc_100Ms_mmap.vhd
+++ b/hdl/cheby/spec_ref_fmc_adc_100Ms_mmap.vhd
--- a/hdl/cheby/svec_ref_fmc_adc_100Ms_mmap.cheby
+++ b/hdl/cheby/svec_ref_fmc_adc_100Ms_mmap.cheby
--- a/hdl/cheby/svec_ref_fmc_adc_100Ms_mmap.vhd
+++ b/hdl/cheby/svec_ref_fmc_adc_100Ms_mmap.vhd
--- a/hdl/cheby/timetag_core_regs.cheby
+++ b/hdl/cheby/timetag_core_regs.cheby
--- a/hdl/cheby/timetag_core_regs.vhd
+++ b/hdl/cheby/timetag_core_regs.vhd
--- a/hdl/ip_cores/adc_serdes.asy
+++ b/hdl/ip_cores/adc_serdes.asy
--- a/hdl/ip_cores/adc_serdes.ejp
+++ b/hdl/ip_cores/adc_serdes.ejp
--- a/hdl/ip_cores/adc_serdes.gise
+++ b/hdl/ip_cores/adc_serdes.gise
--- a/hdl/ip_cores/adc_serdes.ucf
+++ b/hdl/ip_cores/adc_serdes.ucf
--- a/hdl/ip_cores/adc_serdes.vhd
+++ b/hdl/ip_cores/adc_serdes.vhd
--- a/hdl/ip_cores/adc_serdes.vho
+++ b/hdl/ip_cores/adc_serdes.vho
--- a/hdl/ip_cores/adc_serdes.xco
+++ b/hdl/ip_cores/adc_serdes.xco
--- a/hdl/ip_cores/adc_serdes.xise
+++ b/hdl/ip_cores/adc_serdes.xise
--- a/hdl/ip_cores/adc_serdes/doc/selectio_wiz_ds746.pdf
+++ b/hdl/ip_cores/adc_serdes/doc/selectio_wiz_ds746.pdf
--- a/hdl/ip_cores/adc_serdes/doc/selectio_wiz_gsg700.pdf
+++ b/hdl/ip_cores/adc_serdes/doc/selectio_wiz_gsg700.pdf
--- a/hdl/ip_cores/adc_serdes/example_design/adc_serdes_exdes.vhd
+++ b/hdl/ip_cores/adc_serdes/example_design/adc_serdes_exdes.vhd
--- a/hdl/ip_cores/adc_serdes/implement/implement.bat
+++ b/hdl/ip_cores/adc_serdes/implement/implement.bat
--- a/hdl/ip_cores/adc_serdes/implement/implement.sh
+++ b/hdl/ip_cores/adc_serdes/implement/implement.sh
--- a/hdl/ip_cores/adc_serdes/implement/synplify.prj
+++ b/hdl/ip_cores/adc_serdes/implement/synplify.prj
-
--- a/hdl/ip_cores/adc_serdes/implement/xst.prj
+++ b/hdl/ip_cores/adc_serdes/implement/xst.prj
-
-vhdl work ../../adc_serdes.vhd
-vhdl work ../example_design/adc_serdes_exdes.vhd
--- a/hdl/ip_cores/adc_serdes/implement/xst.scr
+++ b/hdl/ip_cores/adc_serdes/implement/xst.scr
--- a/hdl/ip_cores/adc_serdes/selectio_wiz_readme.txt
+++ b/hdl/ip_cores/adc_serdes/selectio_wiz_readme.txt
--- a/hdl/ip_cores/adc_serdes/simulation/adc_serdes_tb.vhd
+++ b/hdl/ip_cores/adc_serdes/simulation/adc_serdes_tb.vhd
--- a/hdl/ip_cores/adc_serdes/simulation/functional/simcmds.tcl
+++ b/hdl/ip_cores/adc_serdes/simulation/functional/simcmds.tcl
--- a/hdl/ip_cores/adc_serdes/simulation/functional/simulate_isim.bat
+++ b/hdl/ip_cores/adc_serdes/simulation/functional/simulate_isim.bat
--- a/hdl/ip_cores/adc_serdes/simulation/functional/simulate_isim.sh
+++ b/hdl/ip_cores/adc_serdes/simulation/functional/simulate_isim.sh
--- a/hdl/ip_cores/adc_serdes/simulation/functional/simulate_mti.do
+++ b/hdl/ip_cores/adc_serdes/simulation/functional/simulate_mti.do
--- a/hdl/ip_cores/adc_serdes/simulation/functional/simulate_ncsim.sh
+++ b/hdl/ip_cores/adc_serdes/simulation/functional/simulate_ncsim.sh
--- a/hdl/ip_cores/adc_serdes/simulation/functional/simulate_vcs.sh
+++ b/hdl/ip_cores/adc_serdes/simulation/functional/simulate_vcs.sh
-
--- a/hdl/ip_cores/adc_serdes/simulation/functional/ucli_commands.key
+++ b/hdl/ip_cores/adc_serdes/simulation/functional/ucli_commands.key
-
--- a/hdl/ip_cores/adc_serdes/simulation/functional/vcs_session.tcl
+++ b/hdl/ip_cores/adc_serdes/simulation/functional/vcs_session.tcl
--- a/hdl/ip_cores/adc_serdes/simulation/functional/wave.do
+++ b/hdl/ip_cores/adc_serdes/simulation/functional/wave.do
--- a/hdl/ip_cores/adc_serdes_flist.txt
+++ b/hdl/ip_cores/adc_serdes_flist.txt
--- a/hdl/ip_cores/adc_serdes_xmdf.tcl
+++ b/hdl/ip_cores/adc_serdes_xmdf.tcl
--- a/hdl/ip_cores/adc_sync_fifo.asy
+++ b/hdl/ip_cores/adc_sync_fifo.asy
--- a/hdl/ip_cores/adc_sync_fifo.gise
+++ b/hdl/ip_cores/adc_sync_fifo.gise
--- a/hdl/ip_cores/adc_sync_fifo.ngc
+++ b/hdl/ip_cores/adc_sync_fifo.ngc
--- a/hdl/ip_cores/adc_sync_fifo.sym
+++ b/hdl/ip_cores/adc_sync_fifo.sym
--- a/hdl/ip_cores/adc_sync_fifo.vhd
+++ b/hdl/ip_cores/adc_sync_fifo.vhd
--- a/hdl/ip_cores/adc_sync_fifo.vho
+++ b/hdl/ip_cores/adc_sync_fifo.vho
--- a/hdl/ip_cores/adc_sync_fifo.xco
+++ b/hdl/ip_cores/adc_sync_fifo.xco
--- a/hdl/ip_cores/adc_sync_fifo.xise
+++ b/hdl/ip_cores/adc_sync_fifo.xise
--- a/hdl/ip_cores/adc_sync_fifo_flist.txt
+++ b/hdl/ip_cores/adc_sync_fifo_flist.txt
--- a/hdl/ip_cores/adc_sync_fifo_xmdf.tcl
+++ b/hdl/ip_cores/adc_sync_fifo_xmdf.tcl
--- a/hdl/ip_cores/coregen.cgc
+++ b/hdl/ip_cores/coregen.cgc
--- a/hdl/ip_cores/coregen.cgp
+++ b/hdl/ip_cores/coregen.cgp
--- a/hdl/ip_cores/coregen.log
+++ b/hdl/ip_cores/coregen.log
--- a/ddr3-sp6-core @ 70f9de31
+++ b/ddr3-sp6-core @ 70f9de31
--- a/hdl/ip_cores/ext_pulse_sync/ext_pulse_sync_rtl.vhd
+++ b/hdl/ip_cores/ext_pulse_sync/ext_pulse_sync_rtl.vhd
--- a/hdl/ip_cores/fifo_generator_readme.txt
+++ b/hdl/ip_cores/fifo_generator_readme.txt
--- a/hdl/ip_cores/fifo_generator_ug175.pdf
+++ b/hdl/ip_cores/fifo_generator_ug175.pdf
--- a/general-cores @ 258eb8e0
+++ b/general-cores @ 258eb8e0
--- a/gn4124-core @ e7637624
+++ b/gn4124-core @ e7637624
--- a/hdl/ip_cores/monostable/monostable_rtl.vhd
+++ b/hdl/ip_cores/monostable/monostable_rtl.vhd
--- a/hdl/ip_cores/monostable/monostable_tb.vhd
+++ b/hdl/ip_cores/monostable/monostable_tb.vhd
--- a/hdl/ip_cores/multishot_dpram.asy
+++ b/hdl/ip_cores/multishot_dpram.asy
--- a/hdl/ip_cores/multishot_dpram.gise
+++ b/hdl/ip_cores/multishot_dpram.gise
--- a/hdl/ip_cores/multishot_dpram.ngc
+++ b/hdl/ip_cores/multishot_dpram.ngc
--- a/hdl/ip_cores/multishot_dpram.sym
+++ b/hdl/ip_cores/multishot_dpram.sym
--- a/hdl/ip_cores/multishot_dpram.vhd
+++ b/hdl/ip_cores/multishot_dpram.vhd
--- a/hdl/ip_cores/multishot_dpram.vho
+++ b/hdl/ip_cores/multishot_dpram.vho
--- a/hdl/ip_cores/multishot_dpram.xco
+++ b/hdl/ip_cores/multishot_dpram.xco
--- a/hdl/ip_cores/multishot_dpram.xise
+++ b/hdl/ip_cores/multishot_dpram.xise
--- a/hdl/ip_cores/multishot_dpram_flist.txt
+++ b/hdl/ip_cores/multishot_dpram_flist.txt
--- a/hdl/ip_cores/multishot_dpram_xmdf.tcl
+++ b/hdl/ip_cores/multishot_dpram_xmdf.tcl
--- a/spec @ 1e9e50ec
+++ b/spec @ 1e9e50ec
--- a/svec @ 7d85d3b7
+++ b/svec @ 7d85d3b7
--- a/hdl/ip_cores/timetag_core/rtl/Manifest.py
+++ b/hdl/ip_cores/timetag_core/rtl/Manifest.py
--- a/hdl/ip_cores/timetag_core/rtl/timetag_core.vhd
+++ b/hdl/ip_cores/timetag_core/rtl/timetag_core.vhd
--- a/hdl/ip_cores/timetag_core/rtl/timetag_core_pkg.vhd
+++ b/hdl/ip_cores/timetag_core/rtl/timetag_core_pkg.vhd
--- a/hdl/ip_cores/timetag_core/rtl/timetag_core_regs.vhd
+++ b/hdl/ip_cores/timetag_core/rtl/timetag_core_regs.vhd
--- a/hdl/ip_cores/timetag_core/wb_gen/Makefile
+++ b/hdl/ip_cores/timetag_core/wb_gen/Makefile
--- a/hdl/ip_cores/timetag_core/wb_gen/timetag_core_regs.h
+++ b/hdl/ip_cores/timetag_core/wb_gen/timetag_core_regs.h
--- a/hdl/ip_cores/timetag_core/wb_gen/timetag_core_regs.htm
+++ b/hdl/ip_cores/timetag_core/wb_gen/timetag_core_regs.htm
--- a/hdl/ip_cores/timetag_core/wb_gen/timetag_core_regs.wb
+++ b/hdl/ip_cores/timetag_core/wb_gen/timetag_core_regs.wb
--- a/hdl/ip_cores/utils/utils_pkg.vhd
+++ b/hdl/ip_cores/utils/utils_pkg.vhd
--- a/vme64x-core @ f85c29db
+++ b/vme64x-core @ f85c29db
--- a/hdl/ip_cores/wb_ddr_fifo.asy
+++ b/hdl/ip_cores/wb_ddr_fifo.asy
--- a/hdl/ip_cores/wb_ddr_fifo.gise
+++ b/hdl/ip_cores/wb_ddr_fifo.gise
--- a/hdl/ip_cores/wb_ddr_fifo.ngc
+++ b/hdl/ip_cores/wb_ddr_fifo.ngc
--- a/hdl/ip_cores/wb_ddr_fifo.sym
+++ b/hdl/ip_cores/wb_ddr_fifo.sym
--- a/hdl/ip_cores/wb_ddr_fifo.vhd
+++ b/hdl/ip_cores/wb_ddr_fifo.vhd
--- a/hdl/ip_cores/wb_ddr_fifo.vho
+++ b/hdl/ip_cores/wb_ddr_fifo.vho
--- a/hdl/ip_cores/wb_ddr_fifo.xco
+++ b/hdl/ip_cores/wb_ddr_fifo.xco
--- a/hdl/ip_cores/wb_ddr_fifo.xise
+++ b/hdl/ip_cores/wb_ddr_fifo.xise
--- a/hdl/ip_cores/wb_ddr_fifo_flist.txt
+++ b/hdl/ip_cores/wb_ddr_fifo_flist.txt
--- a/hdl/ip_cores/wb_ddr_fifo_xmdf.tcl
+++ b/hdl/ip_cores/wb_ddr_fifo_xmdf.tcl
--- a/hdl/ip_cores/wb_sync_fifo.asy
+++ b/hdl/ip_cores/wb_sync_fifo.asy
--- a/hdl/ip_cores/wb_sync_fifo.gise
+++ b/hdl/ip_cores/wb_sync_fifo.gise
--- a/hdl/ip_cores/wb_sync_fifo.ngc
+++ b/hdl/ip_cores/wb_sync_fifo.ngc
--- a/hdl/ip_cores/wb_sync_fifo.sym
+++ b/hdl/ip_cores/wb_sync_fifo.sym
--- a/hdl/ip_cores/wb_sync_fifo.vhd
+++ b/hdl/ip_cores/wb_sync_fifo.vhd
--- a/hdl/ip_cores/wb_sync_fifo.vho
+++ b/hdl/ip_cores/wb_sync_fifo.vho
--- a/hdl/ip_cores/wb_sync_fifo.xco
+++ b/hdl/ip_cores/wb_sync_fifo.xco
--- a/hdl/ip_cores/wb_sync_fifo.xise
+++ b/hdl/ip_cores/wb_sync_fifo.xise
--- a/hdl/ip_cores/wb_sync_fifo_flist.txt
+++ b/hdl/ip_cores/wb_sync_fifo_flist.txt
--- a/hdl/ip_cores/wb_sync_fifo_xmdf.tcl
+++ b/hdl/ip_cores/wb_sync_fifo_xmdf.tcl
--- a/wr-cores @ a72a4223
+++ b/wr-cores @ a72a4223
--- a/hdl/platform/Manifest.py
+++ b/hdl/platform/Manifest.py
--- a/hdl/platform/xilinx/Manifest.py
+++ b/hdl/platform/xilinx/Manifest.py
--- a/hdl/platform/xilinx/spartan6/Manifest.py
+++ b/hdl/platform/xilinx/spartan6/Manifest.py
--- a/hdl/platform/xilinx/spartan6/ltc2174_2l16b_receiver.vhd
+++ b/hdl/platform/xilinx/spartan6/ltc2174_2l16b_receiver.vhd
--- a/hdl/rtl/Manifest.py
+++ b/hdl/rtl/Manifest.py
--- a/hdl/rtl/fmc_adc_100Ms_core.vhd
+++ b/hdl/rtl/fmc_adc_100Ms_core.vhd
--- a/hdl/rtl/fmc_adc_100Ms_core_pkg.vhd
+++ b/hdl/rtl/fmc_adc_100Ms_core_pkg.vhd
--- a/hdl/rtl/fmc_adc_eic.vhd
+++ b/hdl/rtl/fmc_adc_eic.vhd
--- a/hdl/rtl/fmc_adc_mezzanine.vhd
+++ b/hdl/rtl/fmc_adc_mezzanine.vhd
--- a/hdl/rtl/fmc_adc_mezzanine_pkg.vhd
+++ b/hdl/rtl/fmc_adc_mezzanine_pkg.vhd
--- a/hdl/rtl/offset_gain_s.vhd
+++ b/hdl/rtl/offset_gain_s.vhd
--- a/hdl/rtl/timetag_core.vhd
+++ b/hdl/rtl/timetag_core.vhd
--- a/hdl/spec/chipscope/acq_to_ddr.cdc
+++ b/hdl/spec/chipscope/acq_to_ddr.cdc
--- a/hdl/spec/chipscope/acq_to_ddr.cpj
+++ b/hdl/spec/chipscope/acq_to_ddr.cpj
--- a/hdl/spec/chipscope/datapath.cdc
+++ b/hdl/spec/chipscope/datapath.cdc
--- a/hdl/spec/chipscope/datapath_fsclk.cdc
+++ b/hdl/spec/chipscope/datapath_fsclk.cdc
--- a/hdl/spec/chipscope/datapath_gn4124.cdc
+++ b/hdl/spec/chipscope/datapath_gn4124.cdc
--- a/hdl/spec/chipscope/datapath_sysclk.cdc
+++ b/hdl/spec/chipscope/datapath_sysclk.cdc
--- a/hdl/spec/chipscope/datapath_wb_to_ddr.cdc
+++ b/hdl/spec/chipscope/datapath_wb_to_ddr.cdc
--- a/hdl/spec/chipscope/end_acq_irq_bug.cdc
+++ b/hdl/spec/chipscope/end_acq_irq_bug.cdc
--- a/hdl/spec/chipscope/gn4124_dma_wb_sdb_hang.cdc
+++ b/hdl/spec/chipscope/gn4124_dma_wb_sdb_hang.cdc
--- a/hdl/spec/chipscope/gn4124_local_bus_drv_dma_freeze.cdc
+++ b/hdl/spec/chipscope/gn4124_local_bus_drv_dma_freeze.cdc
--- a/hdl/spec/chipscope/gn4124_local_bus_sdb_hang.cdc
+++ b/hdl/spec/chipscope/gn4124_local_bus_sdb_hang.cdc
--- a/hdl/spec/chipscope/gn4124_local_bus_sdb_hang.cpj
+++ b/hdl/spec/chipscope/gn4124_local_bus_sdb_hang.cpj
--- a/hdl/spec/chipscope/gn4124_sdb_hang.cdc
+++ b/hdl/spec/chipscope/gn4124_sdb_hang.cdc
--- a/hdl/spec/chipscope/int_trigger.cdc
+++ b/hdl/spec/chipscope/int_trigger.cdc
--- a/hdl/spec/chipscope/irq.cdc
+++ b/hdl/spec/chipscope/irq.cdc
--- a/hdl/spec/chipscope/onewire_debug.cdc
+++ b/hdl/spec/chipscope/onewire_debug.cdc
--- a/hdl/spec/chipscope/serdes_issue.cdc
+++ b/hdl/spec/chipscope/serdes_issue.cdc
--- a/hdl/spec/chipscope/serdes_issue.cpj
+++ b/hdl/spec/chipscope/serdes_issue.cpj
--- a/hdl/spec/memory_map.txt
+++ b/hdl/spec/memory_map.txt
--- a/hdl/spec/rtl/Manifest.py
+++ b/hdl/spec/rtl/Manifest.py
--- a/hdl/spec/rtl/carrier_csr.vhd
+++ b/hdl/spec/rtl/carrier_csr.vhd
--- a/hdl/spec/rtl/dma_eic.vhd
+++ b/hdl/spec/rtl/dma_eic.vhd
--- a/hdl/spec/rtl/sdb_meta_pkg.vhd
+++ b/hdl/spec/rtl/sdb_meta_pkg.vhd
--- a/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
+++ b/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
--- a/hdl/spec/sim-old/mk/adc_serdes.mk
+++ b/hdl/spec/sim-old/mk/adc_serdes.mk
--- a/hdl/spec/sim-old/mk/adc_sync_fifo.mk
+++ b/hdl/spec/sim-old/mk/adc_sync_fifo.mk
--- a/hdl/spec/sim-old/mk/carrier_csr.mk
+++ b/hdl/spec/sim-old/mk/carrier_csr.mk
--- a/hdl/spec/sim-old/mk/cmd_router.mk
+++ b/hdl/spec/sim-old/mk/cmd_router.mk
--- a/hdl/spec/sim-old/mk/cmd_router1.mk
+++ b/hdl/spec/sim-old/mk/cmd_router1.mk
--- a/hdl/spec/sim-old/mk/ddr3.mk
+++ b/hdl/spec/sim-old/mk/ddr3.mk
--- a/hdl/spec/sim-old/mk/ddr3_ctrl.mk
+++ b/hdl/spec/sim-old/mk/ddr3_ctrl.mk
--- a/hdl/spec/sim-old/mk/ddr_controller_bank3_64b.mk
+++ b/hdl/spec/sim-old/mk/ddr_controller_bank3_64b.mk
--- a/hdl/spec/sim-old/mk/dma_controller.mk
+++ b/hdl/spec/sim-old/mk/dma_controller.mk
--- a/hdl/spec/sim-old/mk/dma_controller_wb_slave.mk
+++ b/hdl/spec/sim-old/mk/dma_controller_wb_slave.mk
--- a/hdl/spec/sim-old/mk/ext_pulse_sync_rtl.mk
+++ b/hdl/spec/sim-old/mk/ext_pulse_sync_rtl.mk
--- a/hdl/spec/sim-old/mk/fifo_32x512.mk
+++ b/hdl/spec/sim-old/mk/fifo_32x512.mk
--- a/hdl/spec/sim-old/mk/fifo_64x512.mk
+++ b/hdl/spec/sim-old/mk/fifo_64x512.mk
--- a/hdl/spec/sim-old/mk/fmc_adc_100Ms_core.mk
+++ b/hdl/spec/sim-old/mk/fmc_adc_100Ms_core.mk
--- a/hdl/spec/sim-old/mk/fmc_adc_100Ms_csr.mk
+++ b/hdl/spec/sim-old/mk/fmc_adc_100Ms_csr.mk
--- a/hdl/spec/sim-old/mk/gn4124_core.mk
+++ b/hdl/spec/sim-old/mk/gn4124_core.mk
--- a/hdl/spec/sim-old/mk/gn4124_core_pkg.mk
+++ b/hdl/spec/sim-old/mk/gn4124_core_pkg.mk
--- a/hdl/spec/sim-old/mk/gn4124_core_pkg_s6.mk
+++ b/hdl/spec/sim-old/mk/gn4124_core_pkg_s6.mk
--- a/hdl/spec/sim-old/mk/gn4124_core_s6.mk
+++ b/hdl/spec/sim-old/mk/gn4124_core_s6.mk
--- a/hdl/spec/sim-old/mk/gn412x_bfm.mk
+++ b/hdl/spec/sim-old/mk/gn412x_bfm.mk
--- a/hdl/spec/sim-old/mk/i2c_master_bit_ctrl.mk
+++ b/hdl/spec/sim-old/mk/i2c_master_bit_ctrl.mk
--- a/hdl/spec/sim-old/mk/i2c_master_byte_ctrl.mk
+++ b/hdl/spec/sim-old/mk/i2c_master_byte_ctrl.mk
--- a/hdl/spec/sim-old/mk/i2c_master_top.mk
+++ b/hdl/spec/sim-old/mk/i2c_master_top.mk
--- a/hdl/spec/sim-old/mk/iodrp_controller.mk
+++ b/hdl/spec/sim-old/mk/iodrp_controller.mk
--- a/hdl/spec/sim-old/mk/iodrp_mcb_controller.mk
+++ b/hdl/spec/sim-old/mk/iodrp_mcb_controller.mk
--- a/hdl/spec/sim-old/mk/l2p_arbiter.mk
+++ b/hdl/spec/sim-old/mk/l2p_arbiter.mk
--- a/hdl/spec/sim-old/mk/l2p_dma_master.mk
+++ b/hdl/spec/sim-old/mk/l2p_dma_master.mk
--- a/hdl/spec/sim-old/mk/l2p_ser.mk
+++ b/hdl/spec/sim-old/mk/l2p_ser.mk
--- a/hdl/spec/sim-old/mk/l2p_ser_s6.mk
+++ b/hdl/spec/sim-old/mk/l2p_ser_s6.mk
--- a/hdl/spec/sim-old/mk/mcb_raw_wrapper.mk
+++ b/hdl/spec/sim-old/mk/mcb_raw_wrapper.mk
--- a/hdl/spec/sim-old/mk/mcb_soft_calibration.mk
+++ b/hdl/spec/sim-old/mk/mcb_soft_calibration.mk
--- a/hdl/spec/sim-old/mk/mcb_soft_calibration_top.mk
+++ b/hdl/spec/sim-old/mk/mcb_soft_calibration_top.mk
--- a/hdl/spec/sim-old/mk/mem_model.mk
+++ b/hdl/spec/sim-old/mk/mem_model.mk
--- a/hdl/spec/sim-old/mk/memc3_infrastructure.mk
+++ b/hdl/spec/sim-old/mk/memc3_infrastructure.mk
--- a/hdl/spec/sim-old/mk/memc3_wrapper.mk
+++ b/hdl/spec/sim-old/mk/memc3_wrapper.mk
--- a/hdl/spec/sim-old/mk/monostable_rtl.mk
+++ b/hdl/spec/sim-old/mk/monostable_rtl.mk
--- a/hdl/spec/sim-old/mk/multishot_dpram.mk
+++ b/hdl/spec/sim-old/mk/multishot_dpram.mk
--- a/hdl/spec/sim-old/mk/p2l_decode32.mk
+++ b/hdl/spec/sim-old/mk/p2l_decode32.mk
--- a/hdl/spec/sim-old/mk/p2l_des.mk
+++ b/hdl/spec/sim-old/mk/p2l_des.mk
--- a/hdl/spec/sim-old/mk/p2l_des_s6.mk
+++ b/hdl/spec/sim-old/mk/p2l_des_s6.mk
--- a/hdl/spec/sim-old/mk/p2l_dma_master.mk
+++ b/hdl/spec/sim-old/mk/p2l_dma_master.mk
--- a/hdl/spec/sim-old/mk/serdes_1_to_n_clk_pll_s2_diff.mk
+++ b/hdl/spec/sim-old/mk/serdes_1_to_n_clk_pll_s2_diff.mk
--- a/hdl/spec/sim-old/mk/serdes_1_to_n_data_s2_se.mk
+++ b/hdl/spec/sim-old/mk/serdes_1_to_n_data_s2_se.mk
--- a/hdl/spec/sim-old/mk/serdes_n_to_1_s2_diff.mk
+++ b/hdl/spec/sim-old/mk/serdes_n_to_1_s2_diff.mk
--- a/hdl/spec/sim-old/mk/serdes_n_to_1_s2_se.mk
+++ b/hdl/spec/sim-old/mk/serdes_n_to_1_s2_se.mk
--- a/hdl/spec/sim-old/mk/spec_top_fmc_adc_100Ms.mk
+++ b/hdl/spec/sim-old/mk/spec_top_fmc_adc_100Ms.mk
--- a/hdl/spec/sim-old/mk/spi_clgen.mk
+++ b/hdl/spec/sim-old/mk/spi_clgen.mk
--- a/hdl/spec/sim-old/mk/spi_defines.mk
+++ b/hdl/spec/sim-old/mk/spi_defines.mk
--- a/hdl/spec/sim-old/mk/spi_shift.mk
+++ b/hdl/spec/sim-old/mk/spi_shift.mk
--- a/hdl/spec/sim-old/mk/spi_top.mk
+++ b/hdl/spec/sim-old/mk/spi_top.mk
--- a/hdl/spec/sim-old/mk/tb_spec.mk
+++ b/hdl/spec/sim-old/mk/tb_spec.mk
--- a/hdl/spec/sim-old/mk/test_dpram.mk
+++ b/hdl/spec/sim-old/mk/test_dpram.mk
--- a/hdl/spec/sim-old/mk/textutil.mk
+++ b/hdl/spec/sim-old/mk/textutil.mk
--- a/hdl/spec/sim-old/mk/timescale.mk
+++ b/hdl/spec/sim-old/mk/timescale.mk
--- a/hdl/spec/sim-old/mk/util.mk
+++ b/hdl/spec/sim-old/mk/util.mk
--- a/hdl/spec/sim-old/mk/utils_pkg.mk
+++ b/hdl/spec/sim-old/mk/utils_pkg.mk
--- a/hdl/spec/sim-old/mk/wb_ddr_fifo.mk
+++ b/hdl/spec/sim-old/mk/wb_ddr_fifo.mk
--- a/hdl/spec/sim-old/mk/wbmaster32.mk
+++ b/hdl/spec/sim-old/mk/wbmaster32.mk
--- a/hdl/spec/sim-old/unisims/afifo36_internal.v
+++ b/hdl/spec/sim-old/unisims/afifo36_internal.v
--- a/hdl/spec/sim-old/unisims/and2.v
+++ b/hdl/spec/sim-old/unisims/and2.v
--- a/hdl/spec/sim-old/unisims/and2b1.v
+++ b/hdl/spec/sim-old/unisims/and2b1.v
--- a/hdl/spec/sim-old/unisims/and2b2.v
+++ b/hdl/spec/sim-old/unisims/and2b2.v
--- a/hdl/spec/sim-old/unisims/and3.v
+++ b/hdl/spec/sim-old/unisims/and3.v
--- a/hdl/spec/sim-old/unisims/and3b1.v
+++ b/hdl/spec/sim-old/unisims/and3b1.v
--- a/hdl/spec/sim-old/unisims/and3b2.v
+++ b/hdl/spec/sim-old/unisims/and3b2.v
--- a/hdl/spec/sim-old/unisims/and3b3.v
+++ b/hdl/spec/sim-old/unisims/and3b3.v
--- a/hdl/spec/sim-old/unisims/and4.v
+++ b/hdl/spec/sim-old/unisims/and4.v
--- a/hdl/spec/sim-old/unisims/and4b1.v
+++ b/hdl/spec/sim-old/unisims/and4b1.v
--- a/hdl/spec/sim-old/unisims/and4b2.v
+++ b/hdl/spec/sim-old/unisims/and4b2.v
--- a/hdl/spec/sim-old/unisims/and4b3.v
+++ b/hdl/spec/sim-old/unisims/and4b3.v
--- a/hdl/spec/sim-old/unisims/and4b4.v
+++ b/hdl/spec/sim-old/unisims/and4b4.v
--- a/hdl/spec/sim-old/unisims/and5.v
+++ b/hdl/spec/sim-old/unisims/and5.v
--- a/hdl/spec/sim-old/unisims/and5b1.v
+++ b/hdl/spec/sim-old/unisims/and5b1.v
--- a/hdl/spec/sim-old/unisims/and5b2.v
+++ b/hdl/spec/sim-old/unisims/and5b2.v
--- a/hdl/spec/sim-old/unisims/and5b3.v
+++ b/hdl/spec/sim-old/unisims/and5b3.v
--- a/hdl/spec/sim-old/unisims/and5b4.v
+++ b/hdl/spec/sim-old/unisims/and5b4.v
--- a/hdl/spec/sim-old/unisims/and5b5.v
+++ b/hdl/spec/sim-old/unisims/and5b5.v
--- a/hdl/spec/sim-old/unisims/aramb36_internal.v
+++ b/hdl/spec/sim-old/unisims/aramb36_internal.v
--- a/hdl/spec/sim-old/unisims/bscan_fpgacore.v
+++ b/hdl/spec/sim-old/unisims/bscan_fpgacore.v
--- a/hdl/spec/sim-old/unisims/bscan_spartan2.v
+++ b/hdl/spec/sim-old/unisims/bscan_spartan2.v
--- a/hdl/spec/sim-old/unisims/bscan_spartan3.v
+++ b/hdl/spec/sim-old/unisims/bscan_spartan3.v
--- a/hdl/spec/sim-old/unisims/bscan_spartan3a.v
+++ b/hdl/spec/sim-old/unisims/bscan_spartan3a.v
--- a/hdl/spec/sim-old/unisims/bscan_virtex.v
+++ b/hdl/spec/sim-old/unisims/bscan_virtex.v
--- a/hdl/spec/sim-old/unisims/bscan_virtex2.v
+++ b/hdl/spec/sim-old/unisims/bscan_virtex2.v
--- a/hdl/spec/sim-old/unisims/bscan_virtex4.v
+++ b/hdl/spec/sim-old/unisims/bscan_virtex4.v
--- a/hdl/spec/sim-old/unisims/bscan_virtex5.v
+++ b/hdl/spec/sim-old/unisims/bscan_virtex5.v
--- a/hdl/spec/sim-old/unisims/buf.v
+++ b/hdl/spec/sim-old/unisims/buf.v
--- a/hdl/spec/sim-old/unisims/bufcf.v
+++ b/hdl/spec/sim-old/unisims/bufcf.v
--- a/hdl/spec/sim-old/unisims/bufe.v
+++ b/hdl/spec/sim-old/unisims/bufe.v
--- a/hdl/spec/sim-old/unisims/bufg.v
+++ b/hdl/spec/sim-old/unisims/bufg.v
--- a/hdl/spec/sim-old/unisims/bufgce.v
+++ b/hdl/spec/sim-old/unisims/bufgce.v
--- a/hdl/spec/sim-old/unisims/bufgce_1.v
+++ b/hdl/spec/sim-old/unisims/bufgce_1.v
--- a/hdl/spec/sim-old/unisims/bufgctrl.v
+++ b/hdl/spec/sim-old/unisims/bufgctrl.v
--- a/hdl/spec/sim-old/unisims/bufgdll.v
+++ b/hdl/spec/sim-old/unisims/bufgdll.v
--- a/hdl/spec/sim-old/unisims/bufgmux.v
+++ b/hdl/spec/sim-old/unisims/bufgmux.v
--- a/hdl/spec/sim-old/unisims/bufgmux_1.v
+++ b/hdl/spec/sim-old/unisims/bufgmux_1.v
--- a/hdl/spec/sim-old/unisims/bufgmux_ctrl.v
+++ b/hdl/spec/sim-old/unisims/bufgmux_ctrl.v
--- a/hdl/spec/sim-old/unisims/bufgmux_virtex4.v
+++ b/hdl/spec/sim-old/unisims/bufgmux_virtex4.v
--- a/hdl/spec/sim-old/unisims/bufgp.v
+++ b/hdl/spec/sim-old/unisims/bufgp.v
--- a/hdl/spec/sim-old/unisims/bufio.v
+++ b/hdl/spec/sim-old/unisims/bufio.v
--- a/hdl/spec/sim-old/unisims/bufr.v
+++ b/hdl/spec/sim-old/unisims/bufr.v
--- a/hdl/spec/sim-old/unisims/buft.v
+++ b/hdl/spec/sim-old/unisims/buft.v
--- a/hdl/spec/sim-old/unisims/capture_fpgacore.v
+++ b/hdl/spec/sim-old/unisims/capture_fpgacore.v
--- a/hdl/spec/sim-old/unisims/capture_spartan2.v
+++ b/hdl/spec/sim-old/unisims/capture_spartan2.v
--- a/hdl/spec/sim-old/unisims/capture_spartan3.v
+++ b/hdl/spec/sim-old/unisims/capture_spartan3.v
--- a/hdl/spec/sim-old/unisims/capture_spartan3a.v
+++ b/hdl/spec/sim-old/unisims/capture_spartan3a.v
--- a/hdl/spec/sim-old/unisims/capture_virtex.v
+++ b/hdl/spec/sim-old/unisims/capture_virtex.v
--- a/hdl/spec/sim-old/unisims/capture_virtex2.v
+++ b/hdl/spec/sim-old/unisims/capture_virtex2.v
--- a/hdl/spec/sim-old/unisims/capture_virtex4.v
+++ b/hdl/spec/sim-old/unisims/capture_virtex4.v
--- a/hdl/spec/sim-old/unisims/capture_virtex5.v
+++ b/hdl/spec/sim-old/unisims/capture_virtex5.v
--- a/hdl/spec/sim-old/unisims/carry4.v
+++ b/hdl/spec/sim-old/unisims/carry4.v
--- a/hdl/spec/sim-old/unisims/cfglut5.v
+++ b/hdl/spec/sim-old/unisims/cfglut5.v
--- a/hdl/spec/sim-old/unisims/clkdll.v
+++ b/hdl/spec/sim-old/unisims/clkdll.v
--- a/hdl/spec/sim-old/unisims/clkdlle.v
+++ b/hdl/spec/sim-old/unisims/clkdlle.v
--- a/hdl/spec/sim-old/unisims/clkdllhf.v
+++ b/hdl/spec/sim-old/unisims/clkdllhf.v
--- a/hdl/spec/sim-old/unisims/config.v
+++ b/hdl/spec/sim-old/unisims/config.v
--- a/hdl/spec/sim-old/unisims/crc32.v
+++ b/hdl/spec/sim-old/unisims/crc32.v
--- a/hdl/spec/sim-old/unisims/crc64.v
+++ b/hdl/spec/sim-old/unisims/crc64.v
--- a/hdl/spec/sim-old/unisims/dcc_fpgacore.v
+++ b/hdl/spec/sim-old/unisims/dcc_fpgacore.v
--- a/hdl/spec/sim-old/unisims/dcireset.v
+++ b/hdl/spec/sim-old/unisims/dcireset.v
--- a/hdl/spec/sim-old/unisims/dcm.v
+++ b/hdl/spec/sim-old/unisims/dcm.v
--- a/hdl/spec/sim-old/unisims/dcm_adv.v
+++ b/hdl/spec/sim-old/unisims/dcm_adv.v
--- a/hdl/spec/sim-old/unisims/dcm_base.v
+++ b/hdl/spec/sim-old/unisims/dcm_base.v
--- a/hdl/spec/sim-old/unisims/dcm_ps.v
+++ b/hdl/spec/sim-old/unisims/dcm_ps.v
--- a/hdl/spec/sim-old/unisims/dcm_sp.v
+++ b/hdl/spec/sim-old/unisims/dcm_sp.v
--- a/hdl/spec/sim-old/unisims/dna_port.v
+++ b/hdl/spec/sim-old/unisims/dna_port.v
--- a/hdl/spec/sim-old/unisims/dsp48.v
+++ b/hdl/spec/sim-old/unisims/dsp48.v
--- a/hdl/spec/sim-old/unisims/dsp48a.v
+++ b/hdl/spec/sim-old/unisims/dsp48a.v
--- a/hdl/spec/sim-old/unisims/dsp48e.v
+++ b/hdl/spec/sim-old/unisims/dsp48e.v
--- a/hdl/spec/sim-old/unisims/emac.v
+++ b/hdl/spec/sim-old/unisims/emac.v
--- a/hdl/spec/sim-old/unisims/fd.v
+++ b/hdl/spec/sim-old/unisims/fd.v
--- a/hdl/spec/sim-old/unisims/fd_1.v
+++ b/hdl/spec/sim-old/unisims/fd_1.v
--- a/hdl/spec/sim-old/unisims/fdc.v
+++ b/hdl/spec/sim-old/unisims/fdc.v
--- a/hdl/spec/sim-old/unisims/fdc_1.v
+++ b/hdl/spec/sim-old/unisims/fdc_1.v
--- a/hdl/spec/sim-old/unisims/fdce.v
+++ b/hdl/spec/sim-old/unisims/fdce.v
--- a/hdl/spec/sim-old/unisims/fdce_1.v
+++ b/hdl/spec/sim-old/unisims/fdce_1.v
--- a/hdl/spec/sim-old/unisims/fdcp.v
+++ b/hdl/spec/sim-old/unisims/fdcp.v
--- a/hdl/spec/sim-old/unisims/fdcp_1.v
+++ b/hdl/spec/sim-old/unisims/fdcp_1.v
--- a/hdl/spec/sim-old/unisims/fdcpe.v
+++ b/hdl/spec/sim-old/unisims/fdcpe.v
--- a/hdl/spec/sim-old/unisims/fdcpe_1.v
+++ b/hdl/spec/sim-old/unisims/fdcpe_1.v
--- a/hdl/spec/sim-old/unisims/fddrcpe.v
+++ b/hdl/spec/sim-old/unisims/fddrcpe.v
--- a/hdl/spec/sim-old/unisims/fddrrse.v
+++ b/hdl/spec/sim-old/unisims/fddrrse.v
--- a/hdl/spec/sim-old/unisims/fde.v
+++ b/hdl/spec/sim-old/unisims/fde.v
--- a/hdl/spec/sim-old/unisims/fde_1.v
+++ b/hdl/spec/sim-old/unisims/fde_1.v
--- a/hdl/spec/sim-old/unisims/fdp.v
+++ b/hdl/spec/sim-old/unisims/fdp.v
--- a/hdl/spec/sim-old/unisims/fdp_1.v
+++ b/hdl/spec/sim-old/unisims/fdp_1.v
--- a/hdl/spec/sim-old/unisims/fdpe.v
+++ b/hdl/spec/sim-old/unisims/fdpe.v
--- a/hdl/spec/sim-old/unisims/fdpe_1.v
+++ b/hdl/spec/sim-old/unisims/fdpe_1.v
--- a/hdl/spec/sim-old/unisims/fdr.v
+++ b/hdl/spec/sim-old/unisims/fdr.v
--- a/hdl/spec/sim-old/unisims/fdr_1.v
+++ b/hdl/spec/sim-old/unisims/fdr_1.v
--- a/hdl/spec/sim-old/unisims/fdre.v
+++ b/hdl/spec/sim-old/unisims/fdre.v
--- a/hdl/spec/sim-old/unisims/fdre_1.v
+++ b/hdl/spec/sim-old/unisims/fdre_1.v
--- a/hdl/spec/sim-old/unisims/fdrs.v
+++ b/hdl/spec/sim-old/unisims/fdrs.v
--- a/hdl/spec/sim-old/unisims/fdrs_1.v
+++ b/hdl/spec/sim-old/unisims/fdrs_1.v
--- a/hdl/spec/sim-old/unisims/fdrse.v
+++ b/hdl/spec/sim-old/unisims/fdrse.v
--- a/hdl/spec/sim-old/unisims/fdrse_1.v
+++ b/hdl/spec/sim-old/unisims/fdrse_1.v
--- a/hdl/spec/sim-old/unisims/fds.v
+++ b/hdl/spec/sim-old/unisims/fds.v
--- a/hdl/spec/sim-old/unisims/fds_1.v
+++ b/hdl/spec/sim-old/unisims/fds_1.v
--- a/hdl/spec/sim-old/unisims/fdse.v
+++ b/hdl/spec/sim-old/unisims/fdse.v
--- a/hdl/spec/sim-old/unisims/fdse_1.v
+++ b/hdl/spec/sim-old/unisims/fdse_1.v
--- a/hdl/spec/sim-old/unisims/fifo16.v
+++ b/hdl/spec/sim-old/unisims/fifo16.v
--- a/hdl/spec/sim-old/unisims/fifo18.v
+++ b/hdl/spec/sim-old/unisims/fifo18.v
--- a/hdl/spec/sim-old/unisims/fifo18_36.v
+++ b/hdl/spec/sim-old/unisims/fifo18_36.v
--- a/hdl/spec/sim-old/unisims/fifo36.v
+++ b/hdl/spec/sim-old/unisims/fifo36.v
--- a/hdl/spec/sim-old/unisims/fifo36_72.v
+++ b/hdl/spec/sim-old/unisims/fifo36_72.v
--- a/hdl/spec/sim-old/unisims/fifo36_72_exp.v
+++ b/hdl/spec/sim-old/unisims/fifo36_72_exp.v
--- a/hdl/spec/sim-old/unisims/fifo36_exp.v
+++ b/hdl/spec/sim-old/unisims/fifo36_exp.v
--- a/hdl/spec/sim-old/unisims/fmap.v
+++ b/hdl/spec/sim-old/unisims/fmap.v
--- a/hdl/spec/sim-old/unisims/frame_ecc_virtex4.v
+++ b/hdl/spec/sim-old/unisims/frame_ecc_virtex4.v
--- a/hdl/spec/sim-old/unisims/frame_ecc_virtex5.v
+++ b/hdl/spec/sim-old/unisims/frame_ecc_virtex5.v
--- a/hdl/spec/sim-old/unisims/glbl.v
+++ b/hdl/spec/sim-old/unisims/glbl.v
--- a/hdl/spec/sim-old/unisims/gnd.v
+++ b/hdl/spec/sim-old/unisims/gnd.v
--- a/hdl/spec/sim-old/unisims/gt.v
+++ b/hdl/spec/sim-old/unisims/gt.v
--- a/hdl/spec/sim-old/unisims/gt10.v
+++ b/hdl/spec/sim-old/unisims/gt10.v
--- a/hdl/spec/sim-old/unisims/gt10_10ge_4.v
+++ b/hdl/spec/sim-old/unisims/gt10_10ge_4.v
--- a/hdl/spec/sim-old/unisims/gt10_10ge_8.v
+++ b/hdl/spec/sim-old/unisims/gt10_10ge_8.v
--- a/hdl/spec/sim-old/unisims/gt10_10gfc_4.v
+++ b/hdl/spec/sim-old/unisims/gt10_10gfc_4.v
--- a/hdl/spec/sim-old/unisims/gt10_10gfc_8.v
+++ b/hdl/spec/sim-old/unisims/gt10_10gfc_8.v
--- a/hdl/spec/sim-old/unisims/gt10_aurora_1.v
+++ b/hdl/spec/sim-old/unisims/gt10_aurora_1.v
--- a/hdl/spec/sim-old/unisims/gt10_aurora_2.v
+++ b/hdl/spec/sim-old/unisims/gt10_aurora_2.v
--- a/hdl/spec/sim-old/unisims/gt10_aurora_4.v
+++ b/hdl/spec/sim-old/unisims/gt10_aurora_4.v
--- a/hdl/spec/sim-old/unisims/gt10_aurorax_4.v
+++ b/hdl/spec/sim-old/unisims/gt10_aurorax_4.v
--- a/hdl/spec/sim-old/unisims/gt10_aurorax_8.v
+++ b/hdl/spec/sim-old/unisims/gt10_aurorax_8.v
--- a/hdl/spec/sim-old/unisims/gt10_custom.v
+++ b/hdl/spec/sim-old/unisims/gt10_custom.v
--- a/hdl/spec/sim-old/unisims/gt10_infiniband_1.v
+++ b/hdl/spec/sim-old/unisims/gt10_infiniband_1.v
--- a/hdl/spec/sim-old/unisims/gt10_infiniband_2.v
+++ b/hdl/spec/sim-old/unisims/gt10_infiniband_2.v
--- a/hdl/spec/sim-old/unisims/gt10_infiniband_4.v
+++ b/hdl/spec/sim-old/unisims/gt10_infiniband_4.v
--- a/hdl/spec/sim-old/unisims/gt10_oc192_4.v
+++ b/hdl/spec/sim-old/unisims/gt10_oc192_4.v
--- a/hdl/spec/sim-old/unisims/gt10_oc192_8.v
+++ b/hdl/spec/sim-old/unisims/gt10_oc192_8.v
--- a/hdl/spec/sim-old/unisims/gt10_oc48_1.v
+++ b/hdl/spec/sim-old/unisims/gt10_oc48_1.v
--- a/hdl/spec/sim-old/unisims/gt10_oc48_2.v
+++ b/hdl/spec/sim-old/unisims/gt10_oc48_2.v
--- a/hdl/spec/sim-old/unisims/gt10_oc48_4.v
+++ b/hdl/spec/sim-old/unisims/gt10_oc48_4.v
--- a/hdl/spec/sim-old/unisims/gt10_pci_express_1.v
+++ b/hdl/spec/sim-old/unisims/gt10_pci_express_1.v
--- a/hdl/spec/sim-old/unisims/gt10_pci_express_2.v
+++ b/hdl/spec/sim-old/unisims/gt10_pci_express_2.v
--- a/hdl/spec/sim-old/unisims/gt10_pci_express_4.v
+++ b/hdl/spec/sim-old/unisims/gt10_pci_express_4.v
--- a/hdl/spec/sim-old/unisims/gt10_xaui_1.v
+++ b/hdl/spec/sim-old/unisims/gt10_xaui_1.v
--- a/hdl/spec/sim-old/unisims/gt10_xaui_2.v
+++ b/hdl/spec/sim-old/unisims/gt10_xaui_2.v
--- a/hdl/spec/sim-old/unisims/gt10_xaui_4.v
+++ b/hdl/spec/sim-old/unisims/gt10_xaui_4.v
--- a/hdl/spec/sim-old/unisims/gt11.v
+++ b/hdl/spec/sim-old/unisims/gt11.v
--- a/hdl/spec/sim-old/unisims/gt11_custom.v
+++ b/hdl/spec/sim-old/unisims/gt11_custom.v
--- a/hdl/spec/sim-old/unisims/gt11_dual.v
+++ b/hdl/spec/sim-old/unisims/gt11_dual.v
--- a/hdl/spec/sim-old/unisims/gt11clk.v
+++ b/hdl/spec/sim-old/unisims/gt11clk.v
--- a/hdl/spec/sim-old/unisims/gt11clk_mgt.v
+++ b/hdl/spec/sim-old/unisims/gt11clk_mgt.v
--- a/hdl/spec/sim-old/unisims/gt_aurora_1.v
+++ b/hdl/spec/sim-old/unisims/gt_aurora_1.v
--- a/hdl/spec/sim-old/unisims/gt_aurora_2.v
+++ b/hdl/spec/sim-old/unisims/gt_aurora_2.v
--- a/hdl/spec/sim-old/unisims/gt_aurora_4.v
+++ b/hdl/spec/sim-old/unisims/gt_aurora_4.v
--- a/hdl/spec/sim-old/unisims/gt_custom.v
+++ b/hdl/spec/sim-old/unisims/gt_custom.v
--- a/hdl/spec/sim-old/unisims/gt_ethernet_1.v
+++ b/hdl/spec/sim-old/unisims/gt_ethernet_1.v
--- a/hdl/spec/sim-old/unisims/gt_ethernet_2.v
+++ b/hdl/spec/sim-old/unisims/gt_ethernet_2.v
--- a/hdl/spec/sim-old/unisims/gt_ethernet_4.v
+++ b/hdl/spec/sim-old/unisims/gt_ethernet_4.v
--- a/hdl/spec/sim-old/unisims/gt_fibre_chan_1.v
+++ b/hdl/spec/sim-old/unisims/gt_fibre_chan_1.v
--- a/hdl/spec/sim-old/unisims/gt_fibre_chan_2.v
+++ b/hdl/spec/sim-old/unisims/gt_fibre_chan_2.v
--- a/hdl/spec/sim-old/unisims/gt_fibre_chan_4.v
+++ b/hdl/spec/sim-old/unisims/gt_fibre_chan_4.v
--- a/hdl/spec/sim-old/unisims/gt_infiniband_1.v
+++ b/hdl/spec/sim-old/unisims/gt_infiniband_1.v
--- a/hdl/spec/sim-old/unisims/gt_infiniband_2.v
+++ b/hdl/spec/sim-old/unisims/gt_infiniband_2.v
--- a/hdl/spec/sim-old/unisims/gt_infiniband_4.v
+++ b/hdl/spec/sim-old/unisims/gt_infiniband_4.v
--- a/hdl/spec/sim-old/unisims/gt_xaui_1.v
+++ b/hdl/spec/sim-old/unisims/gt_xaui_1.v
--- a/hdl/spec/sim-old/unisims/gt_xaui_2.v
+++ b/hdl/spec/sim-old/unisims/gt_xaui_2.v
--- a/hdl/spec/sim-old/unisims/gt_xaui_4.v
+++ b/hdl/spec/sim-old/unisims/gt_xaui_4.v
--- a/hdl/spec/sim-old/unisims/gtp_dual.v
+++ b/hdl/spec/sim-old/unisims/gtp_dual.v
--- a/hdl/spec/sim-old/unisims/gtx_dual.v
+++ b/hdl/spec/sim-old/unisims/gtx_dual.v
--- a/hdl/spec/sim-old/unisims/ibuf.v
+++ b/hdl/spec/sim-old/unisims/ibuf.v
--- a/hdl/spec/sim-old/unisims/ibuf_agp.v
+++ b/hdl/spec/sim-old/unisims/ibuf_agp.v
--- a/hdl/spec/sim-old/unisims/ibuf_ctt.v
+++ b/hdl/spec/sim-old/unisims/ibuf_ctt.v
--- a/hdl/spec/sim-old/unisims/ibuf_dly_adj.v
+++ b/hdl/spec/sim-old/unisims/ibuf_dly_adj.v
--- a/hdl/spec/sim-old/unisims/ibuf_gtl.v
+++ b/hdl/spec/sim-old/unisims/ibuf_gtl.v
--- a/hdl/spec/sim-old/unisims/ibuf_gtl_dci.v
+++ b/hdl/spec/sim-old/unisims/ibuf_gtl_dci.v
--- a/hdl/spec/sim-old/unisims/ibuf_gtlp.v
+++ b/hdl/spec/sim-old/unisims/ibuf_gtlp.v
--- a/hdl/spec/sim-old/unisims/ibuf_gtlp_dci.v
+++ b/hdl/spec/sim-old/unisims/ibuf_gtlp_dci.v
--- a/hdl/spec/sim-old/unisims/ibuf_hstl_i.v
+++ b/hdl/spec/sim-old/unisims/ibuf_hstl_i.v
--- a/hdl/spec/sim-old/unisims/ibuf_hstl_i_18.v
+++ b/hdl/spec/sim-old/unisims/ibuf_hstl_i_18.v
--- a/hdl/spec/sim-old/unisims/ibuf_hstl_i_dci.v
+++ b/hdl/spec/sim-old/unisims/ibuf_hstl_i_dci.v
--- a/hdl/spec/sim-old/unisims/ibuf_hstl_i_dci_18.v
+++ b/hdl/spec/sim-old/unisims/ibuf_hstl_i_dci_18.v
--- a/hdl/spec/sim-old/unisims/ibuf_hstl_ii.v
+++ b/hdl/spec/sim-old/unisims/ibuf_hstl_ii.v
--- a/hdl/spec/sim-old/unisims/ibuf_hstl_ii_18.v
+++ b/hdl/spec/sim-old/unisims/ibuf_hstl_ii_18.v
--- a/hdl/spec/sim-old/unisims/ibuf_hstl_ii_dci.v
+++ b/hdl/spec/sim-old/unisims/ibuf_hstl_ii_dci.v
--- a/hdl/spec/sim-old/unisims/ibuf_hstl_ii_dci_18.v
+++ b/hdl/spec/sim-old/unisims/ibuf_hstl_ii_dci_18.v
--- a/hdl/spec/sim-old/unisims/ibuf_hstl_iii.v
+++ b/hdl/spec/sim-old/unisims/ibuf_hstl_iii.v
--- a/hdl/spec/sim-old/unisims/ibuf_hstl_iii_18.v
+++ b/hdl/spec/sim-old/unisims/ibuf_hstl_iii_18.v
--- a/hdl/spec/sim-old/unisims/ibuf_hstl_iii_dci.v
+++ b/hdl/spec/sim-old/unisims/ibuf_hstl_iii_dci.v
--- a/hdl/spec/sim-old/unisims/ibuf_hstl_iii_dci_18.v
+++ b/hdl/spec/sim-old/unisims/ibuf_hstl_iii_dci_18.v
--- a/hdl/spec/sim-old/unisims/ibuf_hstl_iv.v
+++ b/hdl/spec/sim-old/unisims/ibuf_hstl_iv.v
--- a/hdl/spec/sim-old/unisims/ibuf_hstl_iv_18.v
+++ b/hdl/spec/sim-old/unisims/ibuf_hstl_iv_18.v
--- a/hdl/spec/sim-old/unisims/ibuf_hstl_iv_dci.v
+++ b/hdl/spec/sim-old/unisims/ibuf_hstl_iv_dci.v
--- a/hdl/spec/sim-old/unisims/ibuf_hstl_iv_dci_18.v
+++ b/hdl/spec/sim-old/unisims/ibuf_hstl_iv_dci_18.v
--- a/hdl/spec/sim-old/unisims/ibuf_lvcmos12.v
+++ b/hdl/spec/sim-old/unisims/ibuf_lvcmos12.v
--- a/hdl/spec/sim-old/unisims/ibuf_lvcmos15.v
+++ b/hdl/spec/sim-old/unisims/ibuf_lvcmos15.v
--- a/hdl/spec/sim-old/unisims/ibuf_lvcmos18.v
+++ b/hdl/spec/sim-old/unisims/ibuf_lvcmos18.v
--- a/hdl/spec/sim-old/unisims/ibuf_lvcmos2.v
+++ b/hdl/spec/sim-old/unisims/ibuf_lvcmos2.v
--- a/hdl/spec/sim-old/unisims/ibuf_lvcmos25.v
+++ b/hdl/spec/sim-old/unisims/ibuf_lvcmos25.v
--- a/hdl/spec/sim-old/unisims/ibuf_lvcmos33.v
+++ b/hdl/spec/sim-old/unisims/ibuf_lvcmos33.v
--- a/hdl/spec/sim-old/unisims/ibuf_lvdci_15.v
+++ b/hdl/spec/sim-old/unisims/ibuf_lvdci_15.v
--- a/hdl/spec/sim-old/unisims/ibuf_lvdci_18.v
+++ b/hdl/spec/sim-old/unisims/ibuf_lvdci_18.v
--- a/hdl/spec/sim-old/unisims/ibuf_lvdci_25.v
+++ b/hdl/spec/sim-old/unisims/ibuf_lvdci_25.v
--- a/hdl/spec/sim-old/unisims/ibuf_lvdci_33.v
+++ b/hdl/spec/sim-old/unisims/ibuf_lvdci_33.v
--- a/hdl/spec/sim-old/unisims/ibuf_lvdci_dv2_15.v
+++ b/hdl/spec/sim-old/unisims/ibuf_lvdci_dv2_15.v
--- a/hdl/spec/sim-old/unisims/ibuf_lvdci_dv2_18.v
+++ b/hdl/spec/sim-old/unisims/ibuf_lvdci_dv2_18.v
--- a/hdl/spec/sim-old/unisims/ibuf_lvdci_dv2_25.v
+++ b/hdl/spec/sim-old/unisims/ibuf_lvdci_dv2_25.v
--- a/hdl/spec/sim-old/unisims/ibuf_lvdci_dv2_33.v
+++ b/hdl/spec/sim-old/unisims/ibuf_lvdci_dv2_33.v
--- a/hdl/spec/sim-old/unisims/ibuf_lvds.v
+++ b/hdl/spec/sim-old/unisims/ibuf_lvds.v
--- a/hdl/spec/sim-old/unisims/ibuf_lvpecl.v
+++ b/hdl/spec/sim-old/unisims/ibuf_lvpecl.v
--- a/hdl/spec/sim-old/unisims/ibuf_lvttl.v
+++ b/hdl/spec/sim-old/unisims/ibuf_lvttl.v
--- a/hdl/spec/sim-old/unisims/ibuf_pci33_3.v
+++ b/hdl/spec/sim-old/unisims/ibuf_pci33_3.v
--- a/hdl/spec/sim-old/unisims/ibuf_pci33_5.v
+++ b/hdl/spec/sim-old/unisims/ibuf_pci33_5.v
--- a/hdl/spec/sim-old/unisims/ibuf_pci66_3.v
+++ b/hdl/spec/sim-old/unisims/ibuf_pci66_3.v
--- a/hdl/spec/sim-old/unisims/ibuf_pcix.v
+++ b/hdl/spec/sim-old/unisims/ibuf_pcix.v
--- a/hdl/spec/sim-old/unisims/ibuf_pcix66_3.v
+++ b/hdl/spec/sim-old/unisims/ibuf_pcix66_3.v
--- a/hdl/spec/sim-old/unisims/ibuf_sstl18_i.v
+++ b/hdl/spec/sim-old/unisims/ibuf_sstl18_i.v
--- a/hdl/spec/sim-old/unisims/ibuf_sstl18_i_dci.v
+++ b/hdl/spec/sim-old/unisims/ibuf_sstl18_i_dci.v
--- a/hdl/spec/sim-old/unisims/ibuf_sstl18_ii.v
+++ b/hdl/spec/sim-old/unisims/ibuf_sstl18_ii.v
--- a/hdl/spec/sim-old/unisims/ibuf_sstl18_ii_dci.v
+++ b/hdl/spec/sim-old/unisims/ibuf_sstl18_ii_dci.v
--- a/hdl/spec/sim-old/unisims/ibuf_sstl2_i.v
+++ b/hdl/spec/sim-old/unisims/ibuf_sstl2_i.v
--- a/hdl/spec/sim-old/unisims/ibuf_sstl2_i_dci.v
+++ b/hdl/spec/sim-old/unisims/ibuf_sstl2_i_dci.v
--- a/hdl/spec/sim-old/unisims/ibuf_sstl2_ii.v
+++ b/hdl/spec/sim-old/unisims/ibuf_sstl2_ii.v
--- a/hdl/spec/sim-old/unisims/ibuf_sstl2_ii_dci.v
+++ b/hdl/spec/sim-old/unisims/ibuf_sstl2_ii_dci.v
--- a/hdl/spec/sim-old/unisims/ibuf_sstl3_i.v
+++ b/hdl/spec/sim-old/unisims/ibuf_sstl3_i.v
--- a/hdl/spec/sim-old/unisims/ibuf_sstl3_i_dci.v
+++ b/hdl/spec/sim-old/unisims/ibuf_sstl3_i_dci.v
--- a/hdl/spec/sim-old/unisims/ibuf_sstl3_ii.v
+++ b/hdl/spec/sim-old/unisims/ibuf_sstl3_ii.v
--- a/hdl/spec/sim-old/unisims/ibuf_sstl3_ii_dci.v
+++ b/hdl/spec/sim-old/unisims/ibuf_sstl3_ii_dci.v
--- a/hdl/spec/sim-old/unisims/ibufds.v
+++ b/hdl/spec/sim-old/unisims/ibufds.v
--- a/hdl/spec/sim-old/unisims/ibufds_blvds_25.v
+++ b/hdl/spec/sim-old/unisims/ibufds_blvds_25.v
--- a/hdl/spec/sim-old/unisims/ibufds_diff_out.v
+++ b/hdl/spec/sim-old/unisims/ibufds_diff_out.v
--- a/hdl/spec/sim-old/unisims/ibufds_dly_adj.v
+++ b/hdl/spec/sim-old/unisims/ibufds_dly_adj.v
--- a/hdl/spec/sim-old/unisims/ibufds_ldt_25.v
+++ b/hdl/spec/sim-old/unisims/ibufds_ldt_25.v
--- a/hdl/spec/sim-old/unisims/ibufds_lvds_25.v
+++ b/hdl/spec/sim-old/unisims/ibufds_lvds_25.v
--- a/hdl/spec/sim-old/unisims/ibufds_lvds_25_dci.v
+++ b/hdl/spec/sim-old/unisims/ibufds_lvds_25_dci.v
--- a/hdl/spec/sim-old/unisims/ibufds_lvds_33.v
+++ b/hdl/spec/sim-old/unisims/ibufds_lvds_33.v
--- a/hdl/spec/sim-old/unisims/ibufds_lvds_33_dci.v
+++ b/hdl/spec/sim-old/unisims/ibufds_lvds_33_dci.v
--- a/hdl/spec/sim-old/unisims/ibufds_lvdsext_25.v
+++ b/hdl/spec/sim-old/unisims/ibufds_lvdsext_25.v
--- a/hdl/spec/sim-old/unisims/ibufds_lvdsext_25_dci.v
+++ b/hdl/spec/sim-old/unisims/ibufds_lvdsext_25_dci.v
--- a/hdl/spec/sim-old/unisims/ibufds_lvdsext_33.v
+++ b/hdl/spec/sim-old/unisims/ibufds_lvdsext_33.v
--- a/hdl/spec/sim-old/unisims/ibufds_lvdsext_33_dci.v
+++ b/hdl/spec/sim-old/unisims/ibufds_lvdsext_33_dci.v
--- a/hdl/spec/sim-old/unisims/ibufds_lvpecl_25.v
+++ b/hdl/spec/sim-old/unisims/ibufds_lvpecl_25.v
--- a/hdl/spec/sim-old/unisims/ibufds_lvpecl_33.v
+++ b/hdl/spec/sim-old/unisims/ibufds_lvpecl_33.v
--- a/hdl/spec/sim-old/unisims/ibufds_ulvds_25.v
+++ b/hdl/spec/sim-old/unisims/ibufds_ulvds_25.v
--- a/hdl/spec/sim-old/unisims/ibufg.v
+++ b/hdl/spec/sim-old/unisims/ibufg.v
--- a/hdl/spec/sim-old/unisims/ibufg_agp.v
+++ b/hdl/spec/sim-old/unisims/ibufg_agp.v
--- a/hdl/spec/sim-old/unisims/ibufg_ctt.v
+++ b/hdl/spec/sim-old/unisims/ibufg_ctt.v
--- a/hdl/spec/sim-old/unisims/ibufg_gtl.v
+++ b/hdl/spec/sim-old/unisims/ibufg_gtl.v
--- a/hdl/spec/sim-old/unisims/ibufg_gtl_dci.v
+++ b/hdl/spec/sim-old/unisims/ibufg_gtl_dci.v
--- a/hdl/spec/sim-old/unisims/ibufg_gtlp.v
+++ b/hdl/spec/sim-old/unisims/ibufg_gtlp.v
--- a/hdl/spec/sim-old/unisims/ibufg_gtlp_dci.v
+++ b/hdl/spec/sim-old/unisims/ibufg_gtlp_dci.v
--- a/hdl/spec/sim-old/unisims/ibufg_hstl_i.v
+++ b/hdl/spec/sim-old/unisims/ibufg_hstl_i.v
--- a/hdl/spec/sim-old/unisims/ibufg_hstl_i_18.v
+++ b/hdl/spec/sim-old/unisims/ibufg_hstl_i_18.v
--- a/hdl/spec/sim-old/unisims/ibufg_hstl_i_dci.v
+++ b/hdl/spec/sim-old/unisims/ibufg_hstl_i_dci.v
--- a/hdl/spec/sim-old/unisims/ibufg_hstl_i_dci_18.v
+++ b/hdl/spec/sim-old/unisims/ibufg_hstl_i_dci_18.v
--- a/hdl/spec/sim-old/unisims/ibufg_hstl_ii.v
+++ b/hdl/spec/sim-old/unisims/ibufg_hstl_ii.v
--- a/hdl/spec/sim-old/unisims/ibufg_hstl_ii_18.v
+++ b/hdl/spec/sim-old/unisims/ibufg_hstl_ii_18.v
--- a/hdl/spec/sim-old/unisims/ibufg_hstl_ii_dci.v
+++ b/hdl/spec/sim-old/unisims/ibufg_hstl_ii_dci.v
--- a/hdl/spec/sim-old/unisims/ibufg_hstl_ii_dci_18.v
+++ b/hdl/spec/sim-old/unisims/ibufg_hstl_ii_dci_18.v
--- a/hdl/spec/sim-old/unisims/ibufg_hstl_iii.v
+++ b/hdl/spec/sim-old/unisims/ibufg_hstl_iii.v
--- a/hdl/spec/sim-old/unisims/ibufg_hstl_iii_18.v
+++ b/hdl/spec/sim-old/unisims/ibufg_hstl_iii_18.v
--- a/hdl/spec/sim-old/unisims/ibufg_hstl_iii_dci.v
+++ b/hdl/spec/sim-old/unisims/ibufg_hstl_iii_dci.v
--- a/hdl/spec/sim-old/unisims/ibufg_hstl_iii_dci_18.v
+++ b/hdl/spec/sim-old/unisims/ibufg_hstl_iii_dci_18.v
--- a/hdl/spec/sim-old/unisims/ibufg_hstl_iv.v
+++ b/hdl/spec/sim-old/unisims/ibufg_hstl_iv.v
--- a/hdl/spec/sim-old/unisims/ibufg_hstl_iv_18.v
+++ b/hdl/spec/sim-old/unisims/ibufg_hstl_iv_18.v
--- a/hdl/spec/sim-old/unisims/ibufg_hstl_iv_dci.v
+++ b/hdl/spec/sim-old/unisims/ibufg_hstl_iv_dci.v
--- a/hdl/spec/sim-old/unisims/ibufg_hstl_iv_dci_18.v
+++ b/hdl/spec/sim-old/unisims/ibufg_hstl_iv_dci_18.v
--- a/hdl/spec/sim-old/unisims/ibufg_lvcmos12.v
+++ b/hdl/spec/sim-old/unisims/ibufg_lvcmos12.v
--- a/hdl/spec/sim-old/unisims/ibufg_lvcmos15.v
+++ b/hdl/spec/sim-old/unisims/ibufg_lvcmos15.v
--- a/hdl/spec/sim-old/unisims/ibufg_lvcmos18.v
+++ b/hdl/spec/sim-old/unisims/ibufg_lvcmos18.v
--- a/hdl/spec/sim-old/unisims/ibufg_lvcmos2.v
+++ b/hdl/spec/sim-old/unisims/ibufg_lvcmos2.v
--- a/hdl/spec/sim-old/unisims/ibufg_lvcmos25.v
+++ b/hdl/spec/sim-old/unisims/ibufg_lvcmos25.v
--- a/hdl/spec/sim-old/unisims/ibufg_lvcmos33.v
+++ b/hdl/spec/sim-old/unisims/ibufg_lvcmos33.v
--- a/hdl/spec/sim-old/unisims/ibufg_lvdci_15.v
+++ b/hdl/spec/sim-old/unisims/ibufg_lvdci_15.v
--- a/hdl/spec/sim-old/unisims/ibufg_lvdci_18.v
+++ b/hdl/spec/sim-old/unisims/ibufg_lvdci_18.v
--- a/hdl/spec/sim-old/unisims/ibufg_lvdci_25.v
+++ b/hdl/spec/sim-old/unisims/ibufg_lvdci_25.v
--- a/hdl/spec/sim-old/unisims/ibufg_lvdci_33.v
+++ b/hdl/spec/sim-old/unisims/ibufg_lvdci_33.v
--- a/hdl/spec/sim-old/unisims/ibufg_lvdci_dv2_15.v
+++ b/hdl/spec/sim-old/unisims/ibufg_lvdci_dv2_15.v
--- a/hdl/spec/sim-old/unisims/ibufg_lvdci_dv2_18.v
+++ b/hdl/spec/sim-old/unisims/ibufg_lvdci_dv2_18.v
--- a/hdl/spec/sim-old/unisims/ibufg_lvdci_dv2_25.v
+++ b/hdl/spec/sim-old/unisims/ibufg_lvdci_dv2_25.v
--- a/hdl/spec/sim-old/unisims/ibufg_lvdci_dv2_33.v
+++ b/hdl/spec/sim-old/unisims/ibufg_lvdci_dv2_33.v
--- a/hdl/spec/sim-old/unisims/ibufg_lvds.v
+++ b/hdl/spec/sim-old/unisims/ibufg_lvds.v
--- a/hdl/spec/sim-old/unisims/ibufg_lvpecl.v
+++ b/hdl/spec/sim-old/unisims/ibufg_lvpecl.v
--- a/hdl/spec/sim-old/unisims/ibufg_lvttl.v
+++ b/hdl/spec/sim-old/unisims/ibufg_lvttl.v
--- a/hdl/spec/sim-old/unisims/ibufg_pci33_3.v
+++ b/hdl/spec/sim-old/unisims/ibufg_pci33_3.v
--- a/hdl/spec/sim-old/unisims/ibufg_pci33_5.v
+++ b/hdl/spec/sim-old/unisims/ibufg_pci33_5.v
--- a/hdl/spec/sim-old/unisims/ibufg_pci66_3.v
+++ b/hdl/spec/sim-old/unisims/ibufg_pci66_3.v
--- a/hdl/spec/sim-old/unisims/ibufg_pcix.v
+++ b/hdl/spec/sim-old/unisims/ibufg_pcix.v
--- a/hdl/spec/sim-old/unisims/ibufg_pcix66_3.v
+++ b/hdl/spec/sim-old/unisims/ibufg_pcix66_3.v
--- a/hdl/spec/sim-old/unisims/ibufg_sstl18_i.v
+++ b/hdl/spec/sim-old/unisims/ibufg_sstl18_i.v
--- a/hdl/spec/sim-old/unisims/ibufg_sstl18_i_dci.v
+++ b/hdl/spec/sim-old/unisims/ibufg_sstl18_i_dci.v
--- a/hdl/spec/sim-old/unisims/ibufg_sstl18_ii.v
+++ b/hdl/spec/sim-old/unisims/ibufg_sstl18_ii.v
--- a/hdl/spec/sim-old/unisims/ibufg_sstl18_ii_dci.v
+++ b/hdl/spec/sim-old/unisims/ibufg_sstl18_ii_dci.v
--- a/hdl/spec/sim-old/unisims/ibufg_sstl2_i.v
+++ b/hdl/spec/sim-old/unisims/ibufg_sstl2_i.v
--- a/hdl/spec/sim-old/unisims/ibufg_sstl2_i_dci.v
+++ b/hdl/spec/sim-old/unisims/ibufg_sstl2_i_dci.v
--- a/hdl/spec/sim-old/unisims/ibufg_sstl2_ii.v
+++ b/hdl/spec/sim-old/unisims/ibufg_sstl2_ii.v
--- a/hdl/spec/sim-old/unisims/ibufg_sstl2_ii_dci.v
+++ b/hdl/spec/sim-old/unisims/ibufg_sstl2_ii_dci.v
--- a/hdl/spec/sim-old/unisims/ibufg_sstl3_i.v
+++ b/hdl/spec/sim-old/unisims/ibufg_sstl3_i.v
--- a/hdl/spec/sim-old/unisims/ibufg_sstl3_i_dci.v
+++ b/hdl/spec/sim-old/unisims/ibufg_sstl3_i_dci.v
--- a/hdl/spec/sim-old/unisims/ibufg_sstl3_ii.v
+++ b/hdl/spec/sim-old/unisims/ibufg_sstl3_ii.v
--- a/hdl/spec/sim-old/unisims/ibufg_sstl3_ii_dci.v
+++ b/hdl/spec/sim-old/unisims/ibufg_sstl3_ii_dci.v
--- a/hdl/spec/sim-old/unisims/ibufgds.v
+++ b/hdl/spec/sim-old/unisims/ibufgds.v
--- a/hdl/spec/sim-old/unisims/ibufgds_blvds_25.v
+++ b/hdl/spec/sim-old/unisims/ibufgds_blvds_25.v
--- a/hdl/spec/sim-old/unisims/ibufgds_diff_out.v
+++ b/hdl/spec/sim-old/unisims/ibufgds_diff_out.v
--- a/hdl/spec/sim-old/unisims/ibufgds_ldt_25.v
+++ b/hdl/spec/sim-old/unisims/ibufgds_ldt_25.v
--- a/hdl/spec/sim-old/unisims/ibufgds_lvds_25.v
+++ b/hdl/spec/sim-old/unisims/ibufgds_lvds_25.v
--- a/hdl/spec/sim-old/unisims/ibufgds_lvds_25_dci.v
+++ b/hdl/spec/sim-old/unisims/ibufgds_lvds_25_dci.v
--- a/hdl/spec/sim-old/unisims/ibufgds_lvds_33.v
+++ b/hdl/spec/sim-old/unisims/ibufgds_lvds_33.v
--- a/hdl/spec/sim-old/unisims/ibufgds_lvds_33_dci.v
+++ b/hdl/spec/sim-old/unisims/ibufgds_lvds_33_dci.v
--- a/hdl/spec/sim-old/unisims/ibufgds_lvdsext_25.v
+++ b/hdl/spec/sim-old/unisims/ibufgds_lvdsext_25.v
--- a/hdl/spec/sim-old/unisims/ibufgds_lvdsext_25_dci.v
+++ b/hdl/spec/sim-old/unisims/ibufgds_lvdsext_25_dci.v
--- a/hdl/spec/sim-old/unisims/ibufgds_lvdsext_33.v
+++ b/hdl/spec/sim-old/unisims/ibufgds_lvdsext_33.v
--- a/hdl/spec/sim-old/unisims/ibufgds_lvdsext_33_dci.v
+++ b/hdl/spec/sim-old/unisims/ibufgds_lvdsext_33_dci.v
--- a/hdl/spec/sim-old/unisims/ibufgds_lvpecl_25.v
+++ b/hdl/spec/sim-old/unisims/ibufgds_lvpecl_25.v
--- a/hdl/spec/sim-old/unisims/ibufgds_lvpecl_33.v
+++ b/hdl/spec/sim-old/unisims/ibufgds_lvpecl_33.v
--- a/hdl/spec/sim-old/unisims/ibufgds_ulvds_25.v
+++ b/hdl/spec/sim-old/unisims/ibufgds_ulvds_25.v
--- a/hdl/spec/sim-old/unisims/icap_spartan3a.v
+++ b/hdl/spec/sim-old/unisims/icap_spartan3a.v
--- a/hdl/spec/sim-old/unisims/icap_virtex2.v
+++ b/hdl/spec/sim-old/unisims/icap_virtex2.v
--- a/hdl/spec/sim-old/unisims/icap_virtex4.v
+++ b/hdl/spec/sim-old/unisims/icap_virtex4.v
--- a/hdl/spec/sim-old/unisims/icap_virtex5.v
+++ b/hdl/spec/sim-old/unisims/icap_virtex5.v
--- a/hdl/spec/sim-old/unisims/iddr.v
+++ b/hdl/spec/sim-old/unisims/iddr.v
--- a/hdl/spec/sim-old/unisims/iddr2.v
+++ b/hdl/spec/sim-old/unisims/iddr2.v
--- a/hdl/spec/sim-old/unisims/iddr_2clk.v
+++ b/hdl/spec/sim-old/unisims/iddr_2clk.v
--- a/hdl/spec/sim-old/unisims/idelay.v
+++ b/hdl/spec/sim-old/unisims/idelay.v
--- a/hdl/spec/sim-old/unisims/idelayctrl.v
+++ b/hdl/spec/sim-old/unisims/idelayctrl.v
--- a/hdl/spec/sim-old/unisims/ifddrcpe.v
+++ b/hdl/spec/sim-old/unisims/ifddrcpe.v
--- a/hdl/spec/sim-old/unisims/ifddrrse.v
+++ b/hdl/spec/sim-old/unisims/ifddrrse.v
--- a/hdl/spec/sim-old/unisims/inv.v
+++ b/hdl/spec/sim-old/unisims/inv.v
--- a/hdl/spec/sim-old/unisims/iobuf.v
+++ b/hdl/spec/sim-old/unisims/iobuf.v
--- a/hdl/spec/sim-old/unisims/iobuf_agp.v
+++ b/hdl/spec/sim-old/unisims/iobuf_agp.v
--- a/hdl/spec/sim-old/unisims/iobuf_ctt.v
+++ b/hdl/spec/sim-old/unisims/iobuf_ctt.v
--- a/hdl/spec/sim-old/unisims/iobuf_f_12.v
+++ b/hdl/spec/sim-old/unisims/iobuf_f_12.v
--- a/hdl/spec/sim-old/unisims/iobuf_f_16.v
+++ b/hdl/spec/sim-old/unisims/iobuf_f_16.v
--- a/hdl/spec/sim-old/unisims/iobuf_f_2.v
+++ b/hdl/spec/sim-old/unisims/iobuf_f_2.v
--- a/hdl/spec/sim-old/unisims/iobuf_f_24.v
+++ b/hdl/spec/sim-old/unisims/iobuf_f_24.v
--- a/hdl/spec/sim-old/unisims/iobuf_f_4.v
+++ b/hdl/spec/sim-old/unisims/iobuf_f_4.v
--- a/hdl/spec/sim-old/unisims/iobuf_f_6.v
+++ b/hdl/spec/sim-old/unisims/iobuf_f_6.v
--- a/hdl/spec/sim-old/unisims/iobuf_f_8.v
+++ b/hdl/spec/sim-old/unisims/iobuf_f_8.v
--- a/hdl/spec/sim-old/unisims/iobuf_gtl.v
+++ b/hdl/spec/sim-old/unisims/iobuf_gtl.v
--- a/hdl/spec/sim-old/unisims/iobuf_gtl_dci.v
+++ b/hdl/spec/sim-old/unisims/iobuf_gtl_dci.v
--- a/hdl/spec/sim-old/unisims/iobuf_gtlp.v
+++ b/hdl/spec/sim-old/unisims/iobuf_gtlp.v
--- a/hdl/spec/sim-old/unisims/iobuf_gtlp_dci.v
+++ b/hdl/spec/sim-old/unisims/iobuf_gtlp_dci.v
--- a/hdl/spec/sim-old/unisims/iobuf_hstl_i.v
+++ b/hdl/spec/sim-old/unisims/iobuf_hstl_i.v
--- a/hdl/spec/sim-old/unisims/iobuf_hstl_i_18.v
+++ b/hdl/spec/sim-old/unisims/iobuf_hstl_i_18.v
--- a/hdl/spec/sim-old/unisims/iobuf_hstl_ii.v
+++ b/hdl/spec/sim-old/unisims/iobuf_hstl_ii.v
--- a/hdl/spec/sim-old/unisims/iobuf_hstl_ii_18.v
+++ b/hdl/spec/sim-old/unisims/iobuf_hstl_ii_18.v
--- a/hdl/spec/sim-old/unisims/iobuf_hstl_ii_dci.v
+++ b/hdl/spec/sim-old/unisims/iobuf_hstl_ii_dci.v
--- a/hdl/spec/sim-old/unisims/iobuf_hstl_ii_dci_18.v
+++ b/hdl/spec/sim-old/unisims/iobuf_hstl_ii_dci_18.v
--- a/hdl/spec/sim-old/unisims/iobuf_hstl_iii.v
+++ b/hdl/spec/sim-old/unisims/iobuf_hstl_iii.v
--- a/hdl/spec/sim-old/unisims/iobuf_hstl_iii_18.v
+++ b/hdl/spec/sim-old/unisims/iobuf_hstl_iii_18.v
--- a/hdl/spec/sim-old/unisims/iobuf_hstl_iv.v
+++ b/hdl/spec/sim-old/unisims/iobuf_hstl_iv.v
--- a/hdl/spec/sim-old/unisims/iobuf_hstl_iv_18.v
+++ b/hdl/spec/sim-old/unisims/iobuf_hstl_iv_18.v
--- a/hdl/spec/sim-old/unisims/iobuf_hstl_iv_dci.v
+++ b/hdl/spec/sim-old/unisims/iobuf_hstl_iv_dci.v
--- a/hdl/spec/sim-old/unisims/iobuf_hstl_iv_dci_18.v
+++ b/hdl/spec/sim-old/unisims/iobuf_hstl_iv_dci_18.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos12.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos12.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos12_f_2.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos12_f_2.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos12_f_4.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos12_f_4.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos12_f_6.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos12_f_6.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos12_f_8.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos12_f_8.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos12_s_2.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos12_s_2.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos12_s_4.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos12_s_4.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos12_s_6.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos12_s_6.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos12_s_8.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos12_s_8.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos15.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos15.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos15_f_12.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos15_f_12.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos15_f_16.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos15_f_16.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos15_f_2.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos15_f_2.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos15_f_4.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos15_f_4.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos15_f_6.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos15_f_6.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos15_f_8.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos15_f_8.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos15_s_12.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos15_s_12.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos15_s_16.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos15_s_16.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos15_s_2.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos15_s_2.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos15_s_4.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos15_s_4.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos15_s_6.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos15_s_6.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos15_s_8.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos15_s_8.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos18.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos18.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos18_f_12.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos18_f_12.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos18_f_16.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos18_f_16.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos18_f_2.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos18_f_2.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos18_f_4.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos18_f_4.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos18_f_6.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos18_f_6.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos18_f_8.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos18_f_8.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos18_s_12.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos18_s_12.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos18_s_16.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos18_s_16.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos18_s_2.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos18_s_2.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos18_s_4.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos18_s_4.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos18_s_6.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos18_s_6.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos18_s_8.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos18_s_8.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos2.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos2.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos25.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos25.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos25_f_12.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos25_f_12.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos25_f_16.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos25_f_16.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos25_f_2.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos25_f_2.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos25_f_24.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos25_f_24.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos25_f_4.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos25_f_4.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos25_f_6.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos25_f_6.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos25_f_8.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos25_f_8.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos25_s_12.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos25_s_12.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos25_s_16.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos25_s_16.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos25_s_2.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos25_s_2.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos25_s_24.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos25_s_24.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos25_s_4.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos25_s_4.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos25_s_6.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos25_s_6.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos25_s_8.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos25_s_8.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos33.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos33.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos33_f_12.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos33_f_12.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos33_f_16.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos33_f_16.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos33_f_2.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos33_f_2.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos33_f_24.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos33_f_24.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos33_f_4.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos33_f_4.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos33_f_6.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos33_f_6.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos33_f_8.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos33_f_8.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos33_s_12.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos33_s_12.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos33_s_16.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos33_s_16.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos33_s_2.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos33_s_2.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos33_s_24.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos33_s_24.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos33_s_4.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos33_s_4.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos33_s_6.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos33_s_6.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvcmos33_s_8.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvcmos33_s_8.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvdci_15.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvdci_15.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvdci_18.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvdci_18.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvdci_25.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvdci_25.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvdci_33.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvdci_33.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvdci_dv2_15.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvdci_dv2_15.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvdci_dv2_18.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvdci_dv2_18.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvdci_dv2_25.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvdci_dv2_25.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvdci_dv2_33.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvdci_dv2_33.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvds.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvds.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvpecl.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvpecl.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvttl.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvttl.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvttl_f_12.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvttl_f_12.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvttl_f_16.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvttl_f_16.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvttl_f_2.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvttl_f_2.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvttl_f_24.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvttl_f_24.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvttl_f_4.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvttl_f_4.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvttl_f_6.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvttl_f_6.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvttl_f_8.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvttl_f_8.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvttl_s_12.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvttl_s_12.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvttl_s_16.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvttl_s_16.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvttl_s_2.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvttl_s_2.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvttl_s_24.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvttl_s_24.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvttl_s_4.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvttl_s_4.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvttl_s_6.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvttl_s_6.v
--- a/hdl/spec/sim-old/unisims/iobuf_lvttl_s_8.v
+++ b/hdl/spec/sim-old/unisims/iobuf_lvttl_s_8.v
--- a/hdl/spec/sim-old/unisims/iobuf_pci33_3.v
+++ b/hdl/spec/sim-old/unisims/iobuf_pci33_3.v
--- a/hdl/spec/sim-old/unisims/iobuf_pci33_5.v
+++ b/hdl/spec/sim-old/unisims/iobuf_pci33_5.v
--- a/hdl/spec/sim-old/unisims/iobuf_pci66_3.v
+++ b/hdl/spec/sim-old/unisims/iobuf_pci66_3.v
--- a/hdl/spec/sim-old/unisims/iobuf_pcix.v
+++ b/hdl/spec/sim-old/unisims/iobuf_pcix.v
--- a/hdl/spec/sim-old/unisims/iobuf_pcix66_3.v
+++ b/hdl/spec/sim-old/unisims/iobuf_pcix66_3.v
--- a/hdl/spec/sim-old/unisims/iobuf_s_12.v
+++ b/hdl/spec/sim-old/unisims/iobuf_s_12.v
--- a/hdl/spec/sim-old/unisims/iobuf_s_16.v
+++ b/hdl/spec/sim-old/unisims/iobuf_s_16.v
--- a/hdl/spec/sim-old/unisims/iobuf_s_2.v
+++ b/hdl/spec/sim-old/unisims/iobuf_s_2.v
--- a/hdl/spec/sim-old/unisims/iobuf_s_24.v
+++ b/hdl/spec/sim-old/unisims/iobuf_s_24.v
--- a/hdl/spec/sim-old/unisims/iobuf_s_4.v
+++ b/hdl/spec/sim-old/unisims/iobuf_s_4.v
--- a/hdl/spec/sim-old/unisims/iobuf_s_6.v
+++ b/hdl/spec/sim-old/unisims/iobuf_s_6.v
--- a/hdl/spec/sim-old/unisims/iobuf_s_8.v
+++ b/hdl/spec/sim-old/unisims/iobuf_s_8.v
--- a/hdl/spec/sim-old/unisims/iobuf_sstl18_i.v
+++ b/hdl/spec/sim-old/unisims/iobuf_sstl18_i.v
--- a/hdl/spec/sim-old/unisims/iobuf_sstl18_ii.v
+++ b/hdl/spec/sim-old/unisims/iobuf_sstl18_ii.v
--- a/hdl/spec/sim-old/unisims/iobuf_sstl18_ii_dci.v
+++ b/hdl/spec/sim-old/unisims/iobuf_sstl18_ii_dci.v
--- a/hdl/spec/sim-old/unisims/iobuf_sstl2_i.v
+++ b/hdl/spec/sim-old/unisims/iobuf_sstl2_i.v
--- a/hdl/spec/sim-old/unisims/iobuf_sstl2_ii.v
+++ b/hdl/spec/sim-old/unisims/iobuf_sstl2_ii.v
--- a/hdl/spec/sim-old/unisims/iobuf_sstl2_ii_dci.v
+++ b/hdl/spec/sim-old/unisims/iobuf_sstl2_ii_dci.v
--- a/hdl/spec/sim-old/unisims/iobuf_sstl3_i.v
+++ b/hdl/spec/sim-old/unisims/iobuf_sstl3_i.v
--- a/hdl/spec/sim-old/unisims/iobuf_sstl3_ii.v
+++ b/hdl/spec/sim-old/unisims/iobuf_sstl3_ii.v
--- a/hdl/spec/sim-old/unisims/iobuf_sstl3_ii_dci.v
+++ b/hdl/spec/sim-old/unisims/iobuf_sstl3_ii_dci.v
--- a/hdl/spec/sim-old/unisims/iobufds.v
+++ b/hdl/spec/sim-old/unisims/iobufds.v
--- a/hdl/spec/sim-old/unisims/iobufds_blvds_25.v
+++ b/hdl/spec/sim-old/unisims/iobufds_blvds_25.v
--- a/hdl/spec/sim-old/unisims/iodelay.v
+++ b/hdl/spec/sim-old/unisims/iodelay.v
--- a/hdl/spec/sim-old/unisims/iserdes.v
+++ b/hdl/spec/sim-old/unisims/iserdes.v
--- a/hdl/spec/sim-old/unisims/iserdes_nodelay.v
+++ b/hdl/spec/sim-old/unisims/iserdes_nodelay.v
--- a/hdl/spec/sim-old/unisims/jtag_sim_spartan3a.v
+++ b/hdl/spec/sim-old/unisims/jtag_sim_spartan3a.v
--- a/hdl/spec/sim-old/unisims/jtag_sim_virtex4.v
+++ b/hdl/spec/sim-old/unisims/jtag_sim_virtex4.v
--- a/hdl/spec/sim-old/unisims/jtag_sim_virtex5.v
+++ b/hdl/spec/sim-old/unisims/jtag_sim_virtex5.v
--- a/hdl/spec/sim-old/unisims/jtagppc.v
+++ b/hdl/spec/sim-old/unisims/jtagppc.v
--- a/hdl/spec/sim-old/unisims/jtagppc440.v
+++ b/hdl/spec/sim-old/unisims/jtagppc440.v
--- a/hdl/spec/sim-old/unisims/keeper.v
+++ b/hdl/spec/sim-old/unisims/keeper.v
--- a/hdl/spec/sim-old/unisims/key_clear.v
+++ b/hdl/spec/sim-old/unisims/key_clear.v
--- a/hdl/spec/sim-old/unisims/ld.v
+++ b/hdl/spec/sim-old/unisims/ld.v
--- a/hdl/spec/sim-old/unisims/ld_1.v
+++ b/hdl/spec/sim-old/unisims/ld_1.v
--- a/hdl/spec/sim-old/unisims/ldc.v
+++ b/hdl/spec/sim-old/unisims/ldc.v
--- a/hdl/spec/sim-old/unisims/ldc_1.v
+++ b/hdl/spec/sim-old/unisims/ldc_1.v
--- a/hdl/spec/sim-old/unisims/ldce.v
+++ b/hdl/spec/sim-old/unisims/ldce.v
--- a/hdl/spec/sim-old/unisims/ldce_1.v
+++ b/hdl/spec/sim-old/unisims/ldce_1.v
--- a/hdl/spec/sim-old/unisims/ldcp.v
+++ b/hdl/spec/sim-old/unisims/ldcp.v
--- a/hdl/spec/sim-old/unisims/ldcp_1.v
+++ b/hdl/spec/sim-old/unisims/ldcp_1.v
--- a/hdl/spec/sim-old/unisims/ldcpe.v
+++ b/hdl/spec/sim-old/unisims/ldcpe.v
--- a/hdl/spec/sim-old/unisims/ldcpe_1.v
+++ b/hdl/spec/sim-old/unisims/ldcpe_1.v
--- a/hdl/spec/sim-old/unisims/lde.v
+++ b/hdl/spec/sim-old/unisims/lde.v
--- a/hdl/spec/sim-old/unisims/lde_1.v
+++ b/hdl/spec/sim-old/unisims/lde_1.v
--- a/hdl/spec/sim-old/unisims/ldp.v
+++ b/hdl/spec/sim-old/unisims/ldp.v
--- a/hdl/spec/sim-old/unisims/ldp_1.v
+++ b/hdl/spec/sim-old/unisims/ldp_1.v
--- a/hdl/spec/sim-old/unisims/ldpe.v
+++ b/hdl/spec/sim-old/unisims/ldpe.v
--- a/hdl/spec/sim-old/unisims/ldpe_1.v
+++ b/hdl/spec/sim-old/unisims/ldpe_1.v
--- a/hdl/spec/sim-old/unisims/lut1.v
+++ b/hdl/spec/sim-old/unisims/lut1.v
--- a/hdl/spec/sim-old/unisims/lut1_d.v
+++ b/hdl/spec/sim-old/unisims/lut1_d.v
--- a/hdl/spec/sim-old/unisims/lut1_l.v
+++ b/hdl/spec/sim-old/unisims/lut1_l.v
--- a/hdl/spec/sim-old/unisims/lut2.v
+++ b/hdl/spec/sim-old/unisims/lut2.v
--- a/hdl/spec/sim-old/unisims/lut2_d.v
+++ b/hdl/spec/sim-old/unisims/lut2_d.v
--- a/hdl/spec/sim-old/unisims/lut2_l.v
+++ b/hdl/spec/sim-old/unisims/lut2_l.v
--- a/hdl/spec/sim-old/unisims/lut3.v
+++ b/hdl/spec/sim-old/unisims/lut3.v
--- a/hdl/spec/sim-old/unisims/lut3_d.v
+++ b/hdl/spec/sim-old/unisims/lut3_d.v
--- a/hdl/spec/sim-old/unisims/lut3_l.v
+++ b/hdl/spec/sim-old/unisims/lut3_l.v
--- a/hdl/spec/sim-old/unisims/lut4.v
+++ b/hdl/spec/sim-old/unisims/lut4.v
--- a/hdl/spec/sim-old/unisims/lut4_d.v
+++ b/hdl/spec/sim-old/unisims/lut4_d.v
--- a/hdl/spec/sim-old/unisims/lut4_l.v
+++ b/hdl/spec/sim-old/unisims/lut4_l.v
--- a/hdl/spec/sim-old/unisims/lut5.v
+++ b/hdl/spec/sim-old/unisims/lut5.v
--- a/hdl/spec/sim-old/unisims/lut5_d.v
+++ b/hdl/spec/sim-old/unisims/lut5_d.v
--- a/hdl/spec/sim-old/unisims/lut5_l.v
+++ b/hdl/spec/sim-old/unisims/lut5_l.v
--- a/hdl/spec/sim-old/unisims/lut6.v
+++ b/hdl/spec/sim-old/unisims/lut6.v
--- a/hdl/spec/sim-old/unisims/lut6_2.v
+++ b/hdl/spec/sim-old/unisims/lut6_2.v
--- a/hdl/spec/sim-old/unisims/lut6_d.v
+++ b/hdl/spec/sim-old/unisims/lut6_d.v
--- a/hdl/spec/sim-old/unisims/lut6_l.v
+++ b/hdl/spec/sim-old/unisims/lut6_l.v
--- a/hdl/spec/sim-old/unisims/mult18x18.v
+++ b/hdl/spec/sim-old/unisims/mult18x18.v
--- a/hdl/spec/sim-old/unisims/mult18x18s.v
+++ b/hdl/spec/sim-old/unisims/mult18x18s.v
--- a/hdl/spec/sim-old/unisims/mult18x18sio.v
+++ b/hdl/spec/sim-old/unisims/mult18x18sio.v
--- a/hdl/spec/sim-old/unisims/mult_and.v
+++ b/hdl/spec/sim-old/unisims/mult_and.v
--- a/hdl/spec/sim-old/unisims/muxcy.v
+++ b/hdl/spec/sim-old/unisims/muxcy.v
--- a/hdl/spec/sim-old/unisims/muxcy_d.v
+++ b/hdl/spec/sim-old/unisims/muxcy_d.v
--- a/hdl/spec/sim-old/unisims/muxcy_l.v
+++ b/hdl/spec/sim-old/unisims/muxcy_l.v
--- a/hdl/spec/sim-old/unisims/muxf5.v
+++ b/hdl/spec/sim-old/unisims/muxf5.v
--- a/hdl/spec/sim-old/unisims/muxf5_d.v
+++ b/hdl/spec/sim-old/unisims/muxf5_d.v
--- a/hdl/spec/sim-old/unisims/muxf5_l.v
+++ b/hdl/spec/sim-old/unisims/muxf5_l.v
--- a/hdl/spec/sim-old/unisims/muxf6.v
+++ b/hdl/spec/sim-old/unisims/muxf6.v
--- a/hdl/spec/sim-old/unisims/muxf6_d.v
+++ b/hdl/spec/sim-old/unisims/muxf6_d.v
--- a/hdl/spec/sim-old/unisims/muxf6_l.v
+++ b/hdl/spec/sim-old/unisims/muxf6_l.v
--- a/hdl/spec/sim-old/unisims/muxf7.v
+++ b/hdl/spec/sim-old/unisims/muxf7.v
--- a/hdl/spec/sim-old/unisims/muxf7_d.v
+++ b/hdl/spec/sim-old/unisims/muxf7_d.v
--- a/hdl/spec/sim-old/unisims/muxf7_l.v
+++ b/hdl/spec/sim-old/unisims/muxf7_l.v
--- a/hdl/spec/sim-old/unisims/muxf8.v
+++ b/hdl/spec/sim-old/unisims/muxf8.v
--- a/hdl/spec/sim-old/unisims/muxf8_d.v
+++ b/hdl/spec/sim-old/unisims/muxf8_d.v
--- a/hdl/spec/sim-old/unisims/muxf8_l.v
+++ b/hdl/spec/sim-old/unisims/muxf8_l.v
--- a/hdl/spec/sim-old/unisims/nand2.v
+++ b/hdl/spec/sim-old/unisims/nand2.v
--- a/hdl/spec/sim-old/unisims/nand2b1.v
+++ b/hdl/spec/sim-old/unisims/nand2b1.v
--- a/hdl/spec/sim-old/unisims/nand2b2.v
+++ b/hdl/spec/sim-old/unisims/nand2b2.v
--- a/hdl/spec/sim-old/unisims/nand3.v
+++ b/hdl/spec/sim-old/unisims/nand3.v
--- a/hdl/spec/sim-old/unisims/nand3b1.v
+++ b/hdl/spec/sim-old/unisims/nand3b1.v
--- a/hdl/spec/sim-old/unisims/nand3b2.v
+++ b/hdl/spec/sim-old/unisims/nand3b2.v
--- a/hdl/spec/sim-old/unisims/nand3b3.v
+++ b/hdl/spec/sim-old/unisims/nand3b3.v
--- a/hdl/spec/sim-old/unisims/nand4.v
+++ b/hdl/spec/sim-old/unisims/nand4.v
--- a/hdl/spec/sim-old/unisims/nand4b1.v
+++ b/hdl/spec/sim-old/unisims/nand4b1.v
--- a/hdl/spec/sim-old/unisims/nand4b2.v
+++ b/hdl/spec/sim-old/unisims/nand4b2.v
--- a/hdl/spec/sim-old/unisims/nand4b3.v
+++ b/hdl/spec/sim-old/unisims/nand4b3.v
--- a/hdl/spec/sim-old/unisims/nand4b4.v
+++ b/hdl/spec/sim-old/unisims/nand4b4.v
--- a/hdl/spec/sim-old/unisims/nand5.v
+++ b/hdl/spec/sim-old/unisims/nand5.v
--- a/hdl/spec/sim-old/unisims/nand5b1.v
+++ b/hdl/spec/sim-old/unisims/nand5b1.v
--- a/hdl/spec/sim-old/unisims/nand5b2.v
+++ b/hdl/spec/sim-old/unisims/nand5b2.v
--- a/hdl/spec/sim-old/unisims/nand5b3.v
+++ b/hdl/spec/sim-old/unisims/nand5b3.v
--- a/hdl/spec/sim-old/unisims/nand5b4.v
+++ b/hdl/spec/sim-old/unisims/nand5b4.v
--- a/hdl/spec/sim-old/unisims/nand5b5.v
+++ b/hdl/spec/sim-old/unisims/nand5b5.v
--- a/hdl/spec/sim-old/unisims/nor2.v
+++ b/hdl/spec/sim-old/unisims/nor2.v
--- a/hdl/spec/sim-old/unisims/nor2b1.v
+++ b/hdl/spec/sim-old/unisims/nor2b1.v
--- a/hdl/spec/sim-old/unisims/nor2b2.v
+++ b/hdl/spec/sim-old/unisims/nor2b2.v
--- a/hdl/spec/sim-old/unisims/nor3.v
+++ b/hdl/spec/sim-old/unisims/nor3.v
--- a/hdl/spec/sim-old/unisims/nor3b1.v
+++ b/hdl/spec/sim-old/unisims/nor3b1.v
--- a/hdl/spec/sim-old/unisims/nor3b2.v
+++ b/hdl/spec/sim-old/unisims/nor3b2.v
--- a/hdl/spec/sim-old/unisims/nor3b3.v
+++ b/hdl/spec/sim-old/unisims/nor3b3.v
--- a/hdl/spec/sim-old/unisims/nor4.v
+++ b/hdl/spec/sim-old/unisims/nor4.v
--- a/hdl/spec/sim-old/unisims/nor4b1.v
+++ b/hdl/spec/sim-old/unisims/nor4b1.v
--- a/hdl/spec/sim-old/unisims/nor4b2.v
+++ b/hdl/spec/sim-old/unisims/nor4b2.v
--- a/hdl/spec/sim-old/unisims/nor4b3.v
+++ b/hdl/spec/sim-old/unisims/nor4b3.v
--- a/hdl/spec/sim-old/unisims/nor4b4.v
+++ b/hdl/spec/sim-old/unisims/nor4b4.v
--- a/hdl/spec/sim-old/unisims/nor5.v
+++ b/hdl/spec/sim-old/unisims/nor5.v
--- a/hdl/spec/sim-old/unisims/nor5b1.v
+++ b/hdl/spec/sim-old/unisims/nor5b1.v
--- a/hdl/spec/sim-old/unisims/nor5b2.v
+++ b/hdl/spec/sim-old/unisims/nor5b2.v
--- a/hdl/spec/sim-old/unisims/nor5b3.v
+++ b/hdl/spec/sim-old/unisims/nor5b3.v
--- a/hdl/spec/sim-old/unisims/nor5b4.v
+++ b/hdl/spec/sim-old/unisims/nor5b4.v
--- a/hdl/spec/sim-old/unisims/nor5b5.v
+++ b/hdl/spec/sim-old/unisims/nor5b5.v
--- a/hdl/spec/sim-old/unisims/obuf.v
+++ b/hdl/spec/sim-old/unisims/obuf.v
--- a/hdl/spec/sim-old/unisims/obuf_agp.v
+++ b/hdl/spec/sim-old/unisims/obuf_agp.v
--- a/hdl/spec/sim-old/unisims/obuf_ctt.v
+++ b/hdl/spec/sim-old/unisims/obuf_ctt.v
--- a/hdl/spec/sim-old/unisims/obuf_f_12.v
+++ b/hdl/spec/sim-old/unisims/obuf_f_12.v
--- a/hdl/spec/sim-old/unisims/obuf_f_16.v
+++ b/hdl/spec/sim-old/unisims/obuf_f_16.v
--- a/hdl/spec/sim-old/unisims/obuf_f_2.v
+++ b/hdl/spec/sim-old/unisims/obuf_f_2.v
--- a/hdl/spec/sim-old/unisims/obuf_f_24.v
+++ b/hdl/spec/sim-old/unisims/obuf_f_24.v
--- a/hdl/spec/sim-old/unisims/obuf_f_4.v
+++ b/hdl/spec/sim-old/unisims/obuf_f_4.v
--- a/hdl/spec/sim-old/unisims/obuf_f_6.v
+++ b/hdl/spec/sim-old/unisims/obuf_f_6.v
--- a/hdl/spec/sim-old/unisims/obuf_f_8.v
+++ b/hdl/spec/sim-old/unisims/obuf_f_8.v
--- a/hdl/spec/sim-old/unisims/obuf_gtl.v
+++ b/hdl/spec/sim-old/unisims/obuf_gtl.v
--- a/hdl/spec/sim-old/unisims/obuf_gtl_dci.v
+++ b/hdl/spec/sim-old/unisims/obuf_gtl_dci.v
--- a/hdl/spec/sim-old/unisims/obuf_gtlp.v
+++ b/hdl/spec/sim-old/unisims/obuf_gtlp.v
--- a/hdl/spec/sim-old/unisims/obuf_gtlp_dci.v
+++ b/hdl/spec/sim-old/unisims/obuf_gtlp_dci.v
--- a/hdl/spec/sim-old/unisims/obuf_hstl_i.v
+++ b/hdl/spec/sim-old/unisims/obuf_hstl_i.v
--- a/hdl/spec/sim-old/unisims/obuf_hstl_i_18.v
+++ b/hdl/spec/sim-old/unisims/obuf_hstl_i_18.v
--- a/hdl/spec/sim-old/unisims/obuf_hstl_i_dci.v
+++ b/hdl/spec/sim-old/unisims/obuf_hstl_i_dci.v
--- a/hdl/spec/sim-old/unisims/obuf_hstl_i_dci_18.v
+++ b/hdl/spec/sim-old/unisims/obuf_hstl_i_dci_18.v
--- a/hdl/spec/sim-old/unisims/obuf_hstl_ii.v
+++ b/hdl/spec/sim-old/unisims/obuf_hstl_ii.v
--- a/hdl/spec/sim-old/unisims/obuf_hstl_ii_18.v
+++ b/hdl/spec/sim-old/unisims/obuf_hstl_ii_18.v
--- a/hdl/spec/sim-old/unisims/obuf_hstl_ii_dci.v
+++ b/hdl/spec/sim-old/unisims/obuf_hstl_ii_dci.v
--- a/hdl/spec/sim-old/unisims/obuf_hstl_ii_dci_18.v
+++ b/hdl/spec/sim-old/unisims/obuf_hstl_ii_dci_18.v
--- a/hdl/spec/sim-old/unisims/obuf_hstl_iii.v
+++ b/hdl/spec/sim-old/unisims/obuf_hstl_iii.v
--- a/hdl/spec/sim-old/unisims/obuf_hstl_iii_18.v
+++ b/hdl/spec/sim-old/unisims/obuf_hstl_iii_18.v
--- a/hdl/spec/sim-old/unisims/obuf_hstl_iii_dci.v
+++ b/hdl/spec/sim-old/unisims/obuf_hstl_iii_dci.v
--- a/hdl/spec/sim-old/unisims/obuf_hstl_iii_dci_18.v
+++ b/hdl/spec/sim-old/unisims/obuf_hstl_iii_dci_18.v
--- a/hdl/spec/sim-old/unisims/obuf_hstl_iv.v
+++ b/hdl/spec/sim-old/unisims/obuf_hstl_iv.v
--- a/hdl/spec/sim-old/unisims/obuf_hstl_iv_18.v
+++ b/hdl/spec/sim-old/unisims/obuf_hstl_iv_18.v
--- a/hdl/spec/sim-old/unisims/obuf_hstl_iv_dci.v
+++ b/hdl/spec/sim-old/unisims/obuf_hstl_iv_dci.v
--- a/hdl/spec/sim-old/unisims/obuf_hstl_iv_dci_18.v
+++ b/hdl/spec/sim-old/unisims/obuf_hstl_iv_dci_18.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos12.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos12.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos12_f_2.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos12_f_2.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos12_f_4.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos12_f_4.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos12_f_6.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos12_f_6.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos12_f_8.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos12_f_8.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos12_s_2.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos12_s_2.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos12_s_4.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos12_s_4.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos12_s_6.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos12_s_6.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos12_s_8.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos12_s_8.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos15.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos15.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos15_f_12.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos15_f_12.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos15_f_16.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos15_f_16.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos15_f_2.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos15_f_2.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos15_f_4.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos15_f_4.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos15_f_6.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos15_f_6.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos15_f_8.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos15_f_8.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos15_s_12.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos15_s_12.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos15_s_16.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos15_s_16.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos15_s_2.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos15_s_2.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos15_s_4.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos15_s_4.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos15_s_6.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos15_s_6.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos15_s_8.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos15_s_8.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos18.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos18.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos18_f_12.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos18_f_12.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos18_f_16.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos18_f_16.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos18_f_2.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos18_f_2.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos18_f_4.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos18_f_4.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos18_f_6.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos18_f_6.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos18_f_8.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos18_f_8.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos18_s_12.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos18_s_12.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos18_s_16.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos18_s_16.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos18_s_2.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos18_s_2.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos18_s_4.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos18_s_4.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos18_s_6.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos18_s_6.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos18_s_8.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos18_s_8.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos2.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos2.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos25.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos25.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos25_f_12.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos25_f_12.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos25_f_16.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos25_f_16.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos25_f_2.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos25_f_2.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos25_f_24.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos25_f_24.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos25_f_4.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos25_f_4.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos25_f_6.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos25_f_6.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos25_f_8.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos25_f_8.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos25_s_12.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos25_s_12.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos25_s_16.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos25_s_16.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos25_s_2.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos25_s_2.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos25_s_24.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos25_s_24.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos25_s_4.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos25_s_4.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos25_s_6.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos25_s_6.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos25_s_8.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos25_s_8.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos33.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos33.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos33_f_12.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos33_f_12.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos33_f_16.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos33_f_16.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos33_f_2.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos33_f_2.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos33_f_24.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos33_f_24.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos33_f_4.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos33_f_4.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos33_f_6.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos33_f_6.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos33_f_8.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos33_f_8.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos33_s_12.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos33_s_12.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos33_s_16.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos33_s_16.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos33_s_2.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos33_s_2.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos33_s_24.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos33_s_24.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos33_s_4.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos33_s_4.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos33_s_6.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos33_s_6.v
--- a/hdl/spec/sim-old/unisims/obuf_lvcmos33_s_8.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvcmos33_s_8.v
--- a/hdl/spec/sim-old/unisims/obuf_lvdci_15.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvdci_15.v
--- a/hdl/spec/sim-old/unisims/obuf_lvdci_18.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvdci_18.v
--- a/hdl/spec/sim-old/unisims/obuf_lvdci_25.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvdci_25.v
--- a/hdl/spec/sim-old/unisims/obuf_lvdci_33.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvdci_33.v
--- a/hdl/spec/sim-old/unisims/obuf_lvdci_dv2_15.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvdci_dv2_15.v
--- a/hdl/spec/sim-old/unisims/obuf_lvdci_dv2_18.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvdci_dv2_18.v
--- a/hdl/spec/sim-old/unisims/obuf_lvdci_dv2_25.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvdci_dv2_25.v
--- a/hdl/spec/sim-old/unisims/obuf_lvdci_dv2_33.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvdci_dv2_33.v
--- a/hdl/spec/sim-old/unisims/obuf_lvds.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvds.v
--- a/hdl/spec/sim-old/unisims/obuf_lvpecl.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvpecl.v
--- a/hdl/spec/sim-old/unisims/obuf_lvttl.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvttl.v
--- a/hdl/spec/sim-old/unisims/obuf_lvttl_f_12.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvttl_f_12.v
--- a/hdl/spec/sim-old/unisims/obuf_lvttl_f_16.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvttl_f_16.v
--- a/hdl/spec/sim-old/unisims/obuf_lvttl_f_2.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvttl_f_2.v
--- a/hdl/spec/sim-old/unisims/obuf_lvttl_f_24.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvttl_f_24.v
--- a/hdl/spec/sim-old/unisims/obuf_lvttl_f_4.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvttl_f_4.v
--- a/hdl/spec/sim-old/unisims/obuf_lvttl_f_6.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvttl_f_6.v
--- a/hdl/spec/sim-old/unisims/obuf_lvttl_f_8.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvttl_f_8.v
--- a/hdl/spec/sim-old/unisims/obuf_lvttl_s_12.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvttl_s_12.v
--- a/hdl/spec/sim-old/unisims/obuf_lvttl_s_16.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvttl_s_16.v
--- a/hdl/spec/sim-old/unisims/obuf_lvttl_s_2.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvttl_s_2.v
--- a/hdl/spec/sim-old/unisims/obuf_lvttl_s_24.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvttl_s_24.v
--- a/hdl/spec/sim-old/unisims/obuf_lvttl_s_4.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvttl_s_4.v
--- a/hdl/spec/sim-old/unisims/obuf_lvttl_s_6.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvttl_s_6.v
--- a/hdl/spec/sim-old/unisims/obuf_lvttl_s_8.v
+++ b/hdl/spec/sim-old/unisims/obuf_lvttl_s_8.v
--- a/hdl/spec/sim-old/unisims/obuf_pci33_3.v
+++ b/hdl/spec/sim-old/unisims/obuf_pci33_3.v
--- a/hdl/spec/sim-old/unisims/obuf_pci33_5.v
+++ b/hdl/spec/sim-old/unisims/obuf_pci33_5.v
--- a/hdl/spec/sim-old/unisims/obuf_pci66_3.v
+++ b/hdl/spec/sim-old/unisims/obuf_pci66_3.v
--- a/hdl/spec/sim-old/unisims/obuf_pcix.v
+++ b/hdl/spec/sim-old/unisims/obuf_pcix.v
--- a/hdl/spec/sim-old/unisims/obuf_pcix66_3.v
+++ b/hdl/spec/sim-old/unisims/obuf_pcix66_3.v
--- a/hdl/spec/sim-old/unisims/obuf_s_12.v
+++ b/hdl/spec/sim-old/unisims/obuf_s_12.v
--- a/hdl/spec/sim-old/unisims/obuf_s_16.v
+++ b/hdl/spec/sim-old/unisims/obuf_s_16.v
--- a/hdl/spec/sim-old/unisims/obuf_s_2.v
+++ b/hdl/spec/sim-old/unisims/obuf_s_2.v
--- a/hdl/spec/sim-old/unisims/obuf_s_24.v
+++ b/hdl/spec/sim-old/unisims/obuf_s_24.v
--- a/hdl/spec/sim-old/unisims/obuf_s_4.v
+++ b/hdl/spec/sim-old/unisims/obuf_s_4.v
--- a/hdl/spec/sim-old/unisims/obuf_s_6.v
+++ b/hdl/spec/sim-old/unisims/obuf_s_6.v
--- a/hdl/spec/sim-old/unisims/obuf_s_8.v
+++ b/hdl/spec/sim-old/unisims/obuf_s_8.v
--- a/hdl/spec/sim-old/unisims/obuf_sstl18_i.v
+++ b/hdl/spec/sim-old/unisims/obuf_sstl18_i.v
--- a/hdl/spec/sim-old/unisims/obuf_sstl18_i_dci.v
+++ b/hdl/spec/sim-old/unisims/obuf_sstl18_i_dci.v
--- a/hdl/spec/sim-old/unisims/obuf_sstl18_ii.v
+++ b/hdl/spec/sim-old/unisims/obuf_sstl18_ii.v
--- a/hdl/spec/sim-old/unisims/obuf_sstl18_ii_dci.v
+++ b/hdl/spec/sim-old/unisims/obuf_sstl18_ii_dci.v
--- a/hdl/spec/sim-old/unisims/obuf_sstl2_i.v
+++ b/hdl/spec/sim-old/unisims/obuf_sstl2_i.v
--- a/hdl/spec/sim-old/unisims/obuf_sstl2_i_dci.v
+++ b/hdl/spec/sim-old/unisims/obuf_sstl2_i_dci.v
--- a/hdl/spec/sim-old/unisims/obuf_sstl2_ii.v
+++ b/hdl/spec/sim-old/unisims/obuf_sstl2_ii.v
--- a/hdl/spec/sim-old/unisims/obuf_sstl2_ii_dci.v
+++ b/hdl/spec/sim-old/unisims/obuf_sstl2_ii_dci.v
--- a/hdl/spec/sim-old/unisims/obuf_sstl3_i.v
+++ b/hdl/spec/sim-old/unisims/obuf_sstl3_i.v
--- a/hdl/spec/sim-old/unisims/obuf_sstl3_i_dci.v
+++ b/hdl/spec/sim-old/unisims/obuf_sstl3_i_dci.v
--- a/hdl/spec/sim-old/unisims/obuf_sstl3_ii.v
+++ b/hdl/spec/sim-old/unisims/obuf_sstl3_ii.v
--- a/hdl/spec/sim-old/unisims/obuf_sstl3_ii_dci.v
+++ b/hdl/spec/sim-old/unisims/obuf_sstl3_ii_dci.v
--- a/hdl/spec/sim-old/unisims/obufds.v
+++ b/hdl/spec/sim-old/unisims/obufds.v
--- a/hdl/spec/sim-old/unisims/obufds_blvds_25.v
+++ b/hdl/spec/sim-old/unisims/obufds_blvds_25.v
--- a/hdl/spec/sim-old/unisims/obufds_ldt_25.v
+++ b/hdl/spec/sim-old/unisims/obufds_ldt_25.v
--- a/hdl/spec/sim-old/unisims/obufds_lvds_25.v
+++ b/hdl/spec/sim-old/unisims/obufds_lvds_25.v
--- a/hdl/spec/sim-old/unisims/obufds_lvds_33.v
+++ b/hdl/spec/sim-old/unisims/obufds_lvds_33.v
--- a/hdl/spec/sim-old/unisims/obufds_lvdsext_25.v
+++ b/hdl/spec/sim-old/unisims/obufds_lvdsext_25.v
--- a/hdl/spec/sim-old/unisims/obufds_lvdsext_33.v
+++ b/hdl/spec/sim-old/unisims/obufds_lvdsext_33.v
--- a/hdl/spec/sim-old/unisims/obufds_lvpecl_25.v
+++ b/hdl/spec/sim-old/unisims/obufds_lvpecl_25.v
--- a/hdl/spec/sim-old/unisims/obufds_lvpecl_33.v
+++ b/hdl/spec/sim-old/unisims/obufds_lvpecl_33.v
--- a/hdl/spec/sim-old/unisims/obufds_ulvds_25.v
+++ b/hdl/spec/sim-old/unisims/obufds_ulvds_25.v
--- a/hdl/spec/sim-old/unisims/obuft.v
+++ b/hdl/spec/sim-old/unisims/obuft.v
--- a/hdl/spec/sim-old/unisims/obuft_agp.v
+++ b/hdl/spec/sim-old/unisims/obuft_agp.v
--- a/hdl/spec/sim-old/unisims/obuft_ctt.v
+++ b/hdl/spec/sim-old/unisims/obuft_ctt.v
--- a/hdl/spec/sim-old/unisims/obuft_f_12.v
+++ b/hdl/spec/sim-old/unisims/obuft_f_12.v
--- a/hdl/spec/sim-old/unisims/obuft_f_16.v
+++ b/hdl/spec/sim-old/unisims/obuft_f_16.v
--- a/hdl/spec/sim-old/unisims/obuft_f_2.v
+++ b/hdl/spec/sim-old/unisims/obuft_f_2.v
--- a/hdl/spec/sim-old/unisims/obuft_f_24.v
+++ b/hdl/spec/sim-old/unisims/obuft_f_24.v
--- a/hdl/spec/sim-old/unisims/obuft_f_4.v
+++ b/hdl/spec/sim-old/unisims/obuft_f_4.v
--- a/hdl/spec/sim-old/unisims/obuft_f_6.v
+++ b/hdl/spec/sim-old/unisims/obuft_f_6.v
--- a/hdl/spec/sim-old/unisims/obuft_f_8.v
+++ b/hdl/spec/sim-old/unisims/obuft_f_8.v
--- a/hdl/spec/sim-old/unisims/obuft_gtl.v
+++ b/hdl/spec/sim-old/unisims/obuft_gtl.v
--- a/hdl/spec/sim-old/unisims/obuft_gtl_dci.v
+++ b/hdl/spec/sim-old/unisims/obuft_gtl_dci.v
--- a/hdl/spec/sim-old/unisims/obuft_gtlp.v
+++ b/hdl/spec/sim-old/unisims/obuft_gtlp.v
--- a/hdl/spec/sim-old/unisims/obuft_gtlp_dci.v
+++ b/hdl/spec/sim-old/unisims/obuft_gtlp_dci.v
--- a/hdl/spec/sim-old/unisims/obuft_hstl_i.v
+++ b/hdl/spec/sim-old/unisims/obuft_hstl_i.v
--- a/hdl/spec/sim-old/unisims/obuft_hstl_i_18.v
+++ b/hdl/spec/sim-old/unisims/obuft_hstl_i_18.v
--- a/hdl/spec/sim-old/unisims/obuft_hstl_i_dci.v
+++ b/hdl/spec/sim-old/unisims/obuft_hstl_i_dci.v
--- a/hdl/spec/sim-old/unisims/obuft_hstl_i_dci_18.v
+++ b/hdl/spec/sim-old/unisims/obuft_hstl_i_dci_18.v
--- a/hdl/spec/sim-old/unisims/obuft_hstl_ii.v
+++ b/hdl/spec/sim-old/unisims/obuft_hstl_ii.v
--- a/hdl/spec/sim-old/unisims/obuft_hstl_ii_18.v
+++ b/hdl/spec/sim-old/unisims/obuft_hstl_ii_18.v
--- a/hdl/spec/sim-old/unisims/obuft_hstl_ii_dci.v
+++ b/hdl/spec/sim-old/unisims/obuft_hstl_ii_dci.v
--- a/hdl/spec/sim-old/unisims/obuft_hstl_ii_dci_18.v
+++ b/hdl/spec/sim-old/unisims/obuft_hstl_ii_dci_18.v