Merge branch '21-update-to-latest-dependency-releases' into 'master'

Resolve "Update to latest dependency releases" Closes #21 See merge request be-cem-edl/fec/hardware-modules/fmc-adc-100m14b4cha!8

Merge branch '21-update-to-latest-dependency-releases' into 'master'
Resolve "Update to latest dependency releases" Closes #21 See merge request be-cem-edl/fec/hardware-modules/fmc-adc-100m14b4cha!8
b9e80f30 · Federico Vaga · d5b74fb1 · 200e3529 · f692bc83 · 1621d6d1
Commit b9e80f30 authored Dec 08, 2022 by Federico Vaga
11 changed files
--- a/ddr3-sp6-core @ f692bc83
+++ b/ddr3-sp6-core @ f692bc83
-Subproject commit 2b8c861b05504e2ebcc94c8f9f4746798a2c2a8a
+Subproject commit f692bc83f42ffd54496f9e0da571c6f9dfcf2335
--- a/general-cores @ 1621d6d1
+++ b/general-cores @ 1621d6d1
-Subproject commit a0aeffbb14ab570069ef667d07889c7fe004a2bf
+Subproject commit 1621d6d1f0c3040284136ce4b3b662269d6868d0
--- a/gn4124-core @ d265dc5d
+++ b/gn4124-core @ d265dc5d
-Subproject commit 461b30fe1f5e4e0c99f2265cdbf5843d31e31a4b
+Subproject commit d265dc5d0cbfe84bd5d310982e1a319a26bb53b2
--- a/spec @ affb718e
+++ b/spec @ affb718e
-Subproject commit fd485c8b31b50a681f1a72504f6969384cfb1d4f
+Subproject commit affb718e16fd0336f262441bf9f7ae7e570d55c6
--- a/svec @ c91efa5e
+++ b/svec @ c91efa5e
-Subproject commit b01a5edccae9b86b572d567e3ad5fdd377c4d03e
+Subproject commit c91efa5e378b0b65a0f4fff9729079007d99ba57
--- a/vme64x-core @ a0ca042e
+++ b/vme64x-core @ a0ca042e
-Subproject commit 8e083d62a59611f4e2e55c53cf06c20593a2aa17
+Subproject commit a0ca042e1f3c19a81c3594477c0c811ac761aaa4
--- a/wr-cores @ 63d6e85c
+++ b/wr-cores @ 63d6e85c
-Subproject commit 3884a65545907de3a0d41d549a4be9e6cccb4916
+Subproject commit 63d6e85c292e57360fe106acfd08de66d3c0acb7
--- a/hdl/syn/.gitlab-ci.yml
+++ b/hdl/syn/.gitlab-ci.yml
@@ -14,6 +14,12 @@
    - cd hdl/syn/"$SYN_NAME"/
    - hdlmake
    - make
+    - |
+      if [[ $(cat *.par | grep -c "All constraints were met") = 0 ]]
+      then
+        echo -e "\e[31mTiming errors detected in PAR report. Aborting...\e[0m"
+        exit 1
+      fi
  artifacts:
    name: "$SYN_NAME-synthesis-$CI_JOB_NAME-$CI_COMMIT_REF_NAME"
    paths:

--- a/hdl/syn/svec_ref_design_wr/Manifest.py
+++ b/hdl/syn/svec_ref_design_wr/Manifest.py
@@ -18,6 +18,11 @@ syn_tool    = "ise"
 if locals().get('fetchto', None) is None:
    fetchto="../../ip_cores"

+# Ideally this should be done by hdlmake itself, to allow downstream Manifests to be able to use the
+# fetchto variable independent of where those Manifests reside in the filesystem.
+import os
+fetchto = os.path.abspath(fetchto)
+
 files = [
    syn_top + "_wr.ucf",
    "buildinfo_pkg.vhd",

--- a/hdl/syn/svec_ref_design_wr/svec_ref_fmc_adc_100Ms_wr.ucf
+++ b/hdl/syn/svec_ref_design_wr/svec_ref_fmc_adc_100Ms_wr.ucf
@@ -175,6 +175,9 @@ NET  "gen_fmc_mezzanine[?].*/*/cmp_ext_trig_sync/gc_sync_ffs_in" MAXDELAY = 2.0
 INST "gen_fmc_mezzanine[0].*/*/cmp_ext_trig_sync/sync0"       RLOC_ORIGIN = X66Y189;
 INST "gen_fmc_mezzanine[1].*/*/cmp_ext_trig_sync/sync0"       RLOC_ORIGIN = X69Y2;

+# Needed for the DDR
+NET "inst_svec_base/gen_with_ddr?.cmp_ddr_ctrl_bank/*/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
+
 #----------------------------------------
 # IOB exceptions
 #----------------------------------------

--- a/hdl/testbench/svec_ref_design/Manifest.py
+++ b/hdl/testbench/svec_ref_design/Manifest.py
@@ -16,6 +16,11 @@ vcom_opt = "-93 -mixedsvvh"
 if locals().get('fetchto', None) is None:
    fetchto="../../ip_cores"

+# Ideally this should be done by hdlmake itself, to allow downstream Manifests to be able to use the
+# fetchto variable independent of where those Manifests reside in the filesystem.
+import os
+fetchto = os.path.abspath(fetchto)
+
 include_dirs = [
    "../include",
    fetchto + "/general-cores/sim/",