Merge branch 'release/v5.0.1'

b9c93121 · Federico Vaga · a3a2724b · aaa717f4 · b9c93121 · b9c93121
Commit b9c93121 authored Jun 11, 2021 by Federico Vaga
9 changed files
--- a/CHANGELOG.rst
+++ b/CHANGELOG.rst
@@ -6,6 +6,15 @@
 Changelog
 =========

+5.0.0 - 2021-06-11
+==================
+Fixed
+-----
+- sw: concurrent DMA transfers are possible thanks to a wait and retry algorithm
+- sw: wait 400ms before reading the temperature the first time (the hardware
+  takes time to setup the thermometers)
+- doc: use cheby files from hdl instead of special implementations
+
 5.0.0 - 2021-02-11
 ==================
 Changes

--- a/doc/gateware/regs/Makefile
+++ b/doc/gateware/regs/Makefile
@@ -2,16 +2,23 @@
 #
 # SPDX-License-Identifier: CC0-1.0

-SOURCES = $(wildcard *.cheby) ../../../hdl/cheby/fmc_adc_mezzanine_mmap.cheby
-TARGETS = $(SOURCES:.cheby=.htm)
+all: spec_base_regs.htm svec_base_regs.htm svec_ref_fmc_adc_100Ms_mmap.htm spec_ref_fmc_adc_100Ms_mmap.htm

-all: $(TARGETS)
+.PHONY: clean

-.PHONY: $(TARGETS) clean
+CHEBY_BUILD=(cd $(dir $<); cheby -i $(notdir $<) --gen-doc --doc html) > $@

-$(TARGETS): %.htm : %.cheby
-	@echo -e "\n\033[34m\033[1m-> Processing file $<\033[0m"
-	@cheby -i $< --gen-doc=$(shell basename $@) --doc html
+spec_ref_fmc_adc_100Ms_mmap.htm: ../../../hdl/cheby/spec_ref_fmc_adc_100Ms_mmap.cheby
+	$(CHEBY_BUILD)
+
+svec_ref_fmc_adc_100Ms_mmap.htm: ../../../hdl/cheby/svec_ref_fmc_adc_100Ms_mmap.cheby
+	$(CHEBY_BUILD)
+
+svec_base_regs.htm: ../../../hdl/ip_cores/svec/hdl/rtl/svec_base_regs.cheby
+	$(CHEBY_BUILD)
+
+spec_base_regs.htm: ../../../hdl/ip_cores/spec/hdl/rtl/spec_base_regs.cheby
+	$(CHEBY_BUILD)

 clean:
 	@rm -f *.md *.rst *.htm
--- a/doc/gateware/regs/spec_ref_fmc_adc_100Ms_doc.cheby
+++ b/doc/gateware/regs/spec_ref_fmc_adc_100Ms_doc.cheby
-# SPDX-FileCopyrightText: 2020 CERN (home.cern)
-#
-# SPDX-License-Identifier: CC-BY-SA-4.0
-
-memory-map:
-  name: spec_ref_fmc_adc_100m_doc
-  bus: wb-32-be
-  description: SPEC FMC-ADC-100M full memory map
-  children:
-    - submap:
-        name: spec_base_mmap
-        address: 0x0000
-        description: SPEC base memory map
-        filename: ../../../hdl/ip_cores/spec/hdl/rtl/spec_base_regs.cheby
-    - submap:
-        name: metadata
-        address: 0x2000
-        size: 0x40
-        interface: wb-32-be
-        x-hdl:
-          busgroup: True
-        description: a ROM containing the application metadata
-    - submap:
-        name: fmc_adc_mezzanine
-        address: 0x4000
-        description: FMC ADC Mezzanine
-        filename: ../../../hdl/cheby/fmc_adc_mezzanine_mmap.cheby
--- a/doc/gateware/regs/svec_ref_fmc_adc_100Ms_doc.cheby
+++ b/doc/gateware/regs/svec_ref_fmc_adc_100Ms_doc.cheby
-# SPDX-FileCopyrightText: 2020 CERN (home.cern)
-#
-# SPDX-License-Identifier: CC-BY-SA-4.0
-
-memory-map:
-  name: svec_ref_fmc_adc_100m_doc
-  bus: wb-32-be
-  description: SVEC FMC-ADC-100M full memory map
-  children:
-    - submap:
-        name: svec_base_mmap
-        address: 0x0000
-        description: SVEC base memory map
-        filename: ../../../hdl/ip_cores/svec/hdl/rtl/svec_base_regs.cheby
-    - submap:
-        name: metadata
-        address: 0x2000
-        size: 0x40
-        interface: wb-32-be
-        x-hdl:
-          busgroup: True
-        description: a ROM containing the application metadata
-    - submap:
-        name: fmc1_adc_mezzanine
-        address: 0x4000
-        description: FMC ADC Mezzanine slot 1
-        filename: ../../../hdl/cheby/fmc_adc_mezzanine_mmap.cheby
-    - submap:
-        name: fmc2_adc_mezzanine
-        address: 0x6000
-        description: FMC ADC Mezzanine slot 2
-        filename: ../../../hdl/cheby/fmc_adc_mezzanine_mmap.cheby
--- a/doc/gateware/spec_ref_fmc_adc_100M.rst
+++ b/doc/gateware/spec_ref_fmc_adc_100M.rst
@@ -6,5 +6,17 @@
 SPEC FMC ADC 100M
 =================

+The memory map is divided in two parts: the `Carrier`_ part common to all SPEC
+designs, and the `FMC-ADC-100M`_ part specific to the FMC-ADC-100M mezzanine.
+
+Carrier
+=======
+
+.. raw:: html
+   :file: regs/spec_base_regs.htm
+
+FMC-ADC-100M
+============
+
 .. raw:: html
-   :file: regs/spec_ref_fmc_adc_100Ms_doc.htm
+   :file: regs/spec_ref_fmc_adc_100Ms_mmap.htm
--- a/doc/gateware/svec_ref_fmc_adc_100M.rst
+++ b/doc/gateware/svec_ref_fmc_adc_100M.rst
@@ -6,5 +6,17 @@
 SVEC FMC ADC 100M
 =================

+The memory map is divided in two parts: the `Carrier`_ part common to all SPEC
+designs, and the `FMC-ADC-100M`_ part specific to the FMC-ADC-100M mezzanine.
+
+Carrier
+=======
+
+.. raw:: html
+   :file: regs/svec_base_regs.htm
+
+FMC-ADC-100M
+============
+
 .. raw:: html
-   :file: regs/svec_ref_fmc_adc_100Ms_doc.htm
+   :file: regs/svec_ref_fmc_adc_100Ms_mmap.htm
--- a/hdl/rtl/fmc_adc_100Ms_core.vhd
+++ b/hdl/rtl/fmc_adc_100Ms_core.vhd
@@ -610,6 +610,8 @@ begin
      data_i      => csr_regout.downsample,
      data_o      => downsample_factor);

+  --  Sync data to the current value register.
+  --  So, timing and loss of samples are not important.
  cmp_ch_sta_sync : gc_sync_word_wr
    generic map (
      g_AUTO_WR => TRUE,

--- a/software/kernel/fa-calibration.c
+++ b/software/kernel/fa-calibration.c
@@ -487,8 +487,13 @@ int fa_calib_init(struct fa_dev *fa)

 	fa_calib_write(fa, &calib);

-	/* Prepare the timely recalibration */
+	/* First calibration.
+	   The board has just been reset by the carrier before calling this
+	   driver and reading the temperature read needs at least 350ms */
+	msleep(400);
 	fa_calib_config(fa);
+
+	/* Prepare the timely recalibration */
 	if (fa_calib_is_compensation_on(fa) && fa_calib_temp_period) {
 		setup_timer(&fa->calib_timer, fa_calib_gain_update, (unsigned long)fa);
 		mod_timer(&fa->calib_timer,

--- a/software/kernel/fa-dma.c
+++ b/software/kernel/fa-dma.c
@@ -112,21 +112,28 @@ int fa_dma_request_channel(struct fa_dev *fa)
 * DMA channels. Then we will request a channel only once at probe like
 * on SPEC
 */
-static int fa_dma_request_channel_svec(struct fa_dev *fa)
+static int fa_dma_request_channel_svec(struct fa_dev *fa,
+									   unsigned int timeout_ms)
 {
+	unsigned long j = jiffies + msecs_to_jiffies(timeout_ms);
 	dma_cap_mask_t dma_mask;

-        if (!fa_is_flag_set(fa, FMC_ADC_SVEC))
+	if (!fa_is_flag_set(fa, FMC_ADC_SVEC))
 		return 0;

 	dma_cap_zero(dma_mask);
 	dma_cap_set(DMA_SLAVE, dma_mask);
 	dma_cap_set(DMA_PRIVATE, dma_mask);
-	fa->dchan = dma_request_channel(dma_mask,
-					fa_dmaengine_filter_svec, fa);
-	if (!fa->dchan)
-		return -ENODEV;
-	return 0;
+
+	do {
+		fa->dchan = dma_request_channel(dma_mask,
+										fa_dmaengine_filter_svec, fa);
+		if (fa->dchan)
+			return 0;
+		cpu_relax();
+	} while (!fa->dchan && time_after(jiffies, j) == 0);
+
+	return -ETIMEDOUT;
 }

 static void __fa_dma_release_channel(struct fa_dev *fa)
@@ -597,7 +604,7 @@ static int fa_dma_start_svec(struct zio_cset *cset)
 	struct zfad_block *zfad_block = cset->interleave->priv_d;
 	int err, i;

-        err = fa_dma_request_channel_svec(fa);
+	err = fa_dma_request_channel_svec(fa, 60000);
 	if (err)
 		return err;