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FMC ADC 100M 14b 4cha
Commit b5b291e7 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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doc: SPEC and SVEC crossbar is generated by cheby now 

Signed-off-by: Dimitris Lampridis's avatarDimitris Lampridis <dimitris.lampridis@cern.ch>
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doc/gateware/index.rst
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......@@ -90,9 +90,9 @@ Wishbone bus (*main* bus). The ADC samples are written and read
to/from the DDR memory using separate Wishbone bus interconnects. Due
to its size, the DDR memory is not mapped on the *main* Wishbone bus
and can only be accessed through DMA. The following figure illustrates
the fmc-adc gateware architecture on the SPEC carrier. A crossbar from
the `General Cores`_ library is used to map the slaves in the Wishbone
address space.
the fmc-adc gateware architecture on the SPEC carrier. A crossbar that
is automatically generated by `cheby` is used to map the slaves in the
Wishbone address space.
.. figure:: ../fig/spec_fw_arch.svg
:alt: SPEC FMC-ADC gateware architecture
......@@ -145,9 +145,9 @@ SVEC (VME64x carrier)
In the VME64x version of the gateware, all blocks are connected to the
VME64x core using a single Wishbone bus. Here the DDR memory is not
accessed through DMA, but using a indirect addressing scheme explained
later in `DDR Memory Controller <#DDR-Memory-Controller>`__. A crossbar
from the general-cores\ `:sup:`11` <#FOOT11>`__ library is used to map
the slaves in the Wishbone address space.
later in `DDR Memory Controller <#DDR-Memory-Controller>`__. A crossbar that
is automatically generated by `cheby` is used to map the slaves in the
Wishbone address space.
.. figure:: ../fig/svec_fw_arch.svg
:alt:
......
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