Skip to content

F
FMC ADC 100M 14b 4cha
Commit b45ac230 authored by Federico Vaga's avatar Federico Vaga
Browse files
Options

Merge remote-tracking branch 'origin/develop' into develop

parents 7ab1e9a1 0ea58655
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 237 additions and 82 deletions
doc/gateware/index.rst
View file @ b45ac230
......@@ -377,7 +377,7 @@ Mezzanine 1-wire Master
~~~~~~~~~~~~~~~~~~~~~~~
.. note::
FIXME talk about the themometer core in general-cores
FIXME talk about the thermometer core in general-cores
Mezzanine I2C Master
~~~~~~~~~~~~~~~~~~~~
......@@ -470,8 +470,8 @@ register enables the sampling clock (Si570 chip), and the other
internal components. Also, in order to use the input offset DACs, the
``OFFSET_DAC_CLR_N`` field must be set to one.
The field ``MAN_BITSLIP`` allows to ’manually’ control the ADC data
alignment in the de-serialiser. The fields ``TRIG_LED`` and
The field ``SERDES_CALIB`` allows to ’manually’ restart the timing
calibration and alignment in the de-serialiser. The fields ``TRIG_LED`` and
``ACQ_LED`` allows to control the FMC front panel LEDs. Those four
fields are for test purpose only and must stay zero in normal
operation.
......@@ -1047,6 +1047,9 @@ state.
The start of an acquisition is prohibited if either the number of
shots or the number of post-trigger samples is equal to zero.
.. note::
Acquired data are always stored to be read in little endian.
Single-shot Mode
----------------
......
hdl/cheby/fmc_adc_100Ms_csr.cheby
View file @ b45ac230
......@@ -41,11 +41,9 @@ memory-map:
range: 3
description: Offset DACs clear (active low)
- field:
name: man_bitslip
name: serdes_calib
range: 4
description: Manual serdes bitslip (ignore on read)
x-hdl:
type: wire
description: Initial serdes calibration
- field:
name: trig_led
range: 6
......
hdl/cheby/fmc_adc_100Ms_csr.vhd
View file @ b45ac230
......@@ -15,7 +15,7 @@ package fmc_adc_100ms_csr_pkg is
ctl_fsm_cmd : std_logic_vector(1 downto 0);
ctl_fmc_clk_oe : std_logic;
ctl_offset_dac_clr_n : std_logic;
ctl_man_bitslip : std_logic;
ctl_serdes_calib : std_logic;
ctl_trig_led : std_logic;
ctl_acq_led : std_logic;
ctl_clear_trig_stat : std_logic;
......@@ -47,7 +47,6 @@ package fmc_adc_100ms_csr_pkg is
type t_fmc_adc_100ms_csr_slave_out is record
ctl_fsm_cmd : std_logic_vector(1 downto 0);
ctl_man_bitslip : std_logic;
ctl_clear_trig_stat : std_logic;
ctl_calib_apply : std_logic;
sta_fsm : std_logic_vector(2 downto 0);
......@@ -120,6 +119,7 @@ architecture syn of fmc_adc_100ms_csr is
signal wb_wip : std_logic;
signal ctl_fmc_clk_oe_reg : std_logic;
signal ctl_offset_dac_clr_n_reg : std_logic;
signal ctl_serdes_calib_reg : std_logic;
signal ctl_trig_led_reg : std_logic;
signal ctl_acq_led_reg : std_logic;
signal ctl_wreq : std_logic;
......@@ -250,7 +250,7 @@ begin
fmc_adc_100ms_csr_o.ctl_fsm_cmd <= wr_dat_d0(1 downto 0);
fmc_adc_100ms_csr_o.ctl_fmc_clk_oe <= ctl_fmc_clk_oe_reg;
fmc_adc_100ms_csr_o.ctl_offset_dac_clr_n <= ctl_offset_dac_clr_n_reg;
fmc_adc_100ms_csr_o.ctl_man_bitslip <= wr_dat_d0(4);
fmc_adc_100ms_csr_o.ctl_serdes_calib <= ctl_serdes_calib_reg;
fmc_adc_100ms_csr_o.ctl_trig_led <= ctl_trig_led_reg;
fmc_adc_100ms_csr_o.ctl_acq_led <= ctl_acq_led_reg;
fmc_adc_100ms_csr_o.ctl_clear_trig_stat <= wr_dat_d0(8);
......@@ -260,6 +260,7 @@ begin
if rst_n_i = '0' then
ctl_fmc_clk_oe_reg <= '0';
ctl_offset_dac_clr_n_reg <= '0';
ctl_serdes_calib_reg <= '0';
ctl_trig_led_reg <= '0';
ctl_acq_led_reg <= '0';
ctl_wack <= '0';
......@@ -267,6 +268,7 @@ begin
if ctl_wreq = '1' then
ctl_fmc_clk_oe_reg <= wr_dat_d0(2);
ctl_offset_dac_clr_n_reg <= wr_dat_d0(3);
ctl_serdes_calib_reg <= wr_dat_d0(4);
ctl_trig_led_reg <= wr_dat_d0(6);
ctl_acq_led_reg <= wr_dat_d0(7);
end if;
......@@ -624,7 +626,7 @@ begin
end process;
-- Process for read requests.
process (rd_adr_d0, rd_req_d0, fmc_adc_100ms_csr_i.ctl_fsm_cmd, ctl_fmc_clk_oe_reg, ctl_offset_dac_clr_n_reg, fmc_adc_100ms_csr_i.ctl_man_bitslip, ctl_trig_led_reg, ctl_acq_led_reg, fmc_adc_100ms_csr_i.ctl_clear_trig_stat, fmc_adc_100ms_csr_i.ctl_calib_apply, fmc_adc_100ms_csr_i.sta_fsm, fmc_adc_100ms_csr_i.sta_serdes_pll, fmc_adc_100ms_csr_i.sta_serdes_synced, fmc_adc_100ms_csr_i.sta_acq_cfg, fmc_adc_100ms_csr_i.sta_fmc_nr, fmc_adc_100ms_csr_i.sta_calib_busy, fmc_adc_100ms_csr_i.trig_stat_ext, fmc_adc_100ms_csr_i.trig_stat_sw, fmc_adc_100ms_csr_i.trig_stat_time, fmc_adc_100ms_csr_i.trig_stat_ch1, fmc_adc_100ms_csr_i.trig_stat_ch2, fmc_adc_100ms_csr_i.trig_stat_ch3, fmc_adc_100ms_csr_i.trig_stat_ch4, trig_en_ext_reg, fmc_adc_100ms_csr_i.trig_en_sw, trig_en_time_reg, fmc_adc_100ms_csr_i.trig_en_aux_time, trig_en_ch1_reg, trig_en_ch2_reg, trig_en_ch3_reg, trig_en_ch4_reg, trig_pol_ext_reg, trig_pol_ch1_reg, trig_pol_ch2_reg, trig_pol_ch3_reg, trig_pol_ch4_reg, ext_trig_dly_reg, shots_nbr_reg, fmc_adc_100ms_csr_i.shots_remain, fmc_adc_100ms_csr_i.multi_depth, fmc_adc_100ms_csr_i.trig_pos, fmc_adc_100ms_csr_i.fs_freq, downsample_reg, pre_samples_reg, post_samples_reg, fmc_adc_100ms_csr_i.samples_cnt, fmc_adc_ch1_i.dat, fmc_adc_ch1_rack, fmc_adc_ch2_i.dat, fmc_adc_ch2_rack, fmc_adc_ch3_i.dat, fmc_adc_ch3_rack, fmc_adc_ch4_i.dat, fmc_adc_ch4_rack) begin
process (rd_adr_d0, rd_req_d0, fmc_adc_100ms_csr_i.ctl_fsm_cmd, ctl_fmc_clk_oe_reg, ctl_offset_dac_clr_n_reg, ctl_serdes_calib_reg, ctl_trig_led_reg, ctl_acq_led_reg, fmc_adc_100ms_csr_i.ctl_clear_trig_stat, fmc_adc_100ms_csr_i.ctl_calib_apply, fmc_adc_100ms_csr_i.sta_fsm, fmc_adc_100ms_csr_i.sta_serdes_pll, fmc_adc_100ms_csr_i.sta_serdes_synced, fmc_adc_100ms_csr_i.sta_acq_cfg, fmc_adc_100ms_csr_i.sta_fmc_nr, fmc_adc_100ms_csr_i.sta_calib_busy, fmc_adc_100ms_csr_i.trig_stat_ext, fmc_adc_100ms_csr_i.trig_stat_sw, fmc_adc_100ms_csr_i.trig_stat_time, fmc_adc_100ms_csr_i.trig_stat_ch1, fmc_adc_100ms_csr_i.trig_stat_ch2, fmc_adc_100ms_csr_i.trig_stat_ch3, fmc_adc_100ms_csr_i.trig_stat_ch4, trig_en_ext_reg, fmc_adc_100ms_csr_i.trig_en_sw, trig_en_time_reg, fmc_adc_100ms_csr_i.trig_en_aux_time, trig_en_ch1_reg, trig_en_ch2_reg, trig_en_ch3_reg, trig_en_ch4_reg, trig_pol_ext_reg, trig_pol_ch1_reg, trig_pol_ch2_reg, trig_pol_ch3_reg, trig_pol_ch4_reg, ext_trig_dly_reg, shots_nbr_reg, fmc_adc_100ms_csr_i.shots_remain, fmc_adc_100ms_csr_i.multi_depth, fmc_adc_100ms_csr_i.trig_pos, fmc_adc_100ms_csr_i.fs_freq, downsample_reg, pre_samples_reg, post_samples_reg, fmc_adc_100ms_csr_i.samples_cnt, fmc_adc_ch1_i.dat, fmc_adc_ch1_rack, fmc_adc_ch2_i.dat, fmc_adc_ch2_rack, fmc_adc_ch3_i.dat, fmc_adc_ch3_rack, fmc_adc_ch4_i.dat, fmc_adc_ch4_rack) begin
-- By default ack read requests
rd_dat_d0 <= (others => 'X');
fmc_adc_ch1_re <= '0';
......@@ -640,7 +642,7 @@ begin
rd_dat_d0(1 downto 0) <= fmc_adc_100ms_csr_i.ctl_fsm_cmd;
rd_dat_d0(2) <= ctl_fmc_clk_oe_reg;
rd_dat_d0(3) <= ctl_offset_dac_clr_n_reg;
rd_dat_d0(4) <= fmc_adc_100ms_csr_i.ctl_man_bitslip;
rd_dat_d0(4) <= ctl_serdes_calib_reg;
rd_dat_d0(5) <= '0';
rd_dat_d0(6) <= ctl_trig_led_reg;
rd_dat_d0(7) <= ctl_acq_led_reg;
......
hdl/rtl/fmc_adc_100Ms_core.vhd
View file @ b45ac230
......@@ -153,8 +153,7 @@ architecture rtl of fmc_adc_100Ms_core is
-- SerDes
signal serdes_out_data : std_logic_vector(63 downto 0);
signal serdes_out_data_synced : std_logic_vector(63 downto 0);
signal serdes_man_bitslip : std_logic;
signal serdes_man_bitslip_sync : std_logic;
signal serdes_calib_sync : std_logic;
signal serdes_locked : std_logic;
signal serdes_locked_sync : std_logic;
signal serdes_synced : std_logic;
......@@ -430,8 +429,8 @@ begin
port map (
clk_i => fs_clk,
rst_n_a_i => '1',
d_i => serdes_man_bitslip,
q_o => serdes_man_bitslip_sync);
d_i => csr_regout.ctl_serdes_calib,
q_o => serdes_calib_sync);
cmp_adc_serdes : entity work.ltc2174_2l16b_receiver
generic map (
......@@ -446,7 +445,7 @@ begin
adc_outb_p_i => adc_outb_p_i,
adc_outb_n_i => adc_outb_n_i,
serdes_arst_i => serdes_arst,
serdes_bslip_i => serdes_man_bitslip_sync,
serdes_calib_i => serdes_calib_sync,
serdes_locked_o => serdes_locked,
serdes_synced_o => serdes_synced,
adc_data_o => serdes_out_data,
......@@ -487,7 +486,6 @@ begin
fmc_adc_ch4_o => wb_channel_in(4));
csr_regin.ctl_fsm_cmd <= fsm_cmd;
csr_regin.ctl_man_bitslip <= serdes_man_bitslip;
csr_regin.ctl_clear_trig_stat <= trig_storage_clear;
csr_regin.ctl_calib_apply <= sync_calib_apply;
......@@ -533,12 +531,10 @@ begin
if rising_edge(sys_clk_i) then
if ctl_reg_wr = '1' then
fsm_cmd <= csr_regout.ctl_fsm_cmd;
serdes_man_bitslip <= csr_regout.ctl_man_bitslip;
trig_storage_clear <= csr_regout.ctl_clear_trig_stat;
sync_calib_apply <= csr_regout.ctl_calib_apply;
else
fsm_cmd <= (others => '0');
serdes_man_bitslip <= '0';
trig_storage_clear <= '0';
sync_calib_apply <= '0';
end if;
......
hdl/rtl/fmc_adc_mezzanine.vhd
View file @ b45ac230
......@@ -69,11 +69,11 @@ entity fmc_adc_mezzanine is
acq_cfg_ok_o : out std_logic;
-- Auxiliary trigger input wishbone interface
wb_trigin_slave_i : in t_wishbone_slave_in;
wb_trigin_slave_i : in t_wishbone_slave_in := c_DUMMY_WB_SLAVE_IN;
wb_trigin_slave_o : out t_wishbone_slave_out;
-- Trigout wishbone interface
wb_trigout_slave_i : in t_wishbone_slave_in;
wb_trigout_slave_i : in t_wishbone_slave_in := c_DUMMY_WB_SLAVE_IN;
wb_trigout_slave_o : out t_wishbone_slave_out;
-- FMC interface
......
hdl/testbench/include/fmc_adc_100Ms_csr.v
View file @ b45ac230
......@@ -10,8 +10,8 @@
`define FMC_ADC_100MS_CSR_CTL_FMC_CLK_OE 'h4
`define FMC_ADC_100MS_CSR_CTL_OFFSET_DAC_CLR_N_OFFSET 3
`define FMC_ADC_100MS_CSR_CTL_OFFSET_DAC_CLR_N 'h8
`define FMC_ADC_100MS_CSR_CTL_MAN_BITSLIP_OFFSET 4
`define FMC_ADC_100MS_CSR_CTL_MAN_BITSLIP 'h10
`define FMC_ADC_100MS_CSR_CTL_SERDES_CALIB_OFFSET 4
`define FMC_ADC_100MS_CSR_CTL_SERDES_CALIB 'h10
`define FMC_ADC_100MS_CSR_CTL_TRIG_LED_OFFSET 6
`define FMC_ADC_100MS_CSR_CTL_TRIG_LED 'h40
`define FMC_ADC_100MS_CSR_CTL_ACQ_LED_OFFSET 7
......
hdl/top/svec_ref_design/svec_ref_fmc_adc_100Ms.vhd
View file @ b45ac230
......@@ -531,10 +531,11 @@ begin -- architecture arch
d_i => fmc_irq(I),
q_o => irq_vector(I));
cmp_fmc_adc_mezzanine : fmc_adc_mezzanine
cmp_fmc_adc_mezzanine : entity work.fmc_adc_mezzanine
generic map (
g_MULTISHOT_RAM_SIZE => g_MULTISHOT_RAM_SIZE,
g_SPARTAN6_USE_PLL => TRUE,
g_BYTE_SWAP => TRUE,
g_FMC_ADC_NR => I,
g_WB_MODE => PIPELINED,
g_WB_GRANULARITY => BYTE)
......
software/kernel/fa-core.c
View file @ b45ac230
......@@ -76,17 +76,20 @@ int fa_adc_output_randomizer_set(struct fa_dev *fa, bool enable)
uint32_t tx, rx;
int err;
/* Read register A1 */
tx = 0x8000;
tx |= (1 << 8);
err = fa_spi_xfer(fa, FA_SPI_SS_ADC, 16, tx, &rx);
if (err)
return err;
/* Set or clear RAND bit */
if (enable)
rx |= BIT(6);
else
rx &= ~BIT(6);
/* Write back A1 */
tx = 0x0000;
tx |= (1 << 8);
tx |= (rx & 0xFF);
......@@ -106,6 +109,7 @@ bool fa_adc_is_output_randomizer(struct fa_dev *fa)
uint32_t tx, rx;
int err;
/* Read register A1 */
tx = 0x8000;
tx |= (1 << 8);
err = fa_spi_xfer(fa, FA_SPI_SS_ADC, 16, tx, &rx);
......
software/kernel/spi.c
View file @ b45ac230
......@@ -82,6 +82,9 @@ int fa_spi_init(struct fa_dev *fa)
/* Force 2's complement data output (register 1, bit 5) */
fa_spi_xfer(fa, FA_SPI_SS_ADC, 16, BIT(8) | BIT(5), &rx);
/* 2 lanes, 14-bit serializaion (register 2) */
fa_spi_xfer(fa, FA_SPI_SS_ADC, 16, (2 << 8) | 0x1, &rx);
return 0;
}
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment