Merge branch 'release/v6.0.2'

b06636f5 · Federico Vaga · 1f364f43 · 25a75922 · b06636f5 · b06636f5
Commit b06636f5 authored Apr 05, 2022 by Federico Vaga
24 changed files
--- a/CHANGELOG.rst
+++ b/CHANGELOG.rst
@@ -6,6 +6,16 @@
 Changelog
 =========
+6.0.2 - 2022-04-05
+==================
+Changed
+-------
+- hdl: white-rabbit core update
+Fixed
+-----
+- hdl: digital noise on SVEC cards by chaning clocking schema
 6.0.1 - 2022-01-11
 ==================
 Changed

--- a/doc/conf.py
+++ b/doc/conf.py
-# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+# SPDX-FileCopyrightText: 2022 CERN (home.cern)
 #
 # SPDX-License-Identifier: CC0-1.0
@@ -22,7 +22,7 @@
 # -- Project information -----------------------------------------------------
 project = 'FMC-ADC-100M-14B-4CHA'
-copyright = u'2013-2021, CERN, documentation released under CC-BY-SA-4.0'
+copyright = u'2022, CERN, documentation released under CC-BY-SA-4.0'
 author = 'Matthieu Cattin, Dimitris Lampridis <dimitrios.lampridis@cern.ch>, Federico Vaga <federico.vaga@cern.ch>'
 # The suffix(es) of source filenames.

--- a/doc/gateware/regs/Makefile
+++ b/doc/gateware/regs/Makefile
@@ -4,12 +4,21 @@
 TOP_DIR = ../../..
-all: spec_base_regs.htm svec_base_regs.htm svec_ref_fmc_adc_100Ms_mmap.htm spec_ref_fmc_adc_100Ms_mmap.htm
+HTML := spec_base_regs.htm
+HTML += svec_base_regs.htm
+HTML += svec_ref_fmc_adc_100Ms_mmap.htm
+HTML += spec_ref_fmc_adc_100Ms_mmap.htm
+HTML += fmc_adc_mezzanine_mmap.htm
+all: $(HTML)
 .PHONY: clean
 CHEBY_BUILD=(cd $(dir $<); cheby -i $(notdir $<) --gen-doc --doc html) > $@
+fmc_adc_mezzanine_mmap.htm: $(TOP_DIR)/hdl/cheby/fmc_adc_mezzanine_mmap.cheby
+	$(CHEBY_BUILD)
 spec_ref_fmc_adc_100Ms_mmap.htm: $(TOP_DIR)/hdl/cheby/spec_ref_fmc_adc_100Ms_mmap.cheby
 	$(CHEBY_BUILD)

--- a/doc/software/driver.rst
+++ b/doc/software/driver.rst
@@ -30,11 +30,13 @@ Compile And Install
 The compile and install the fmcadc100m14b4ch device driver you need
 first to export the path to its direct dependencies, and then you
-execute ``make``. This driver depends on the `zio`_ framework and `fmc`_ library; on a VME system it depends also on the VME bridge driver from CERN BE-CO.
+execute ``make``. This driver depends on the `zio`_ framework and
+`fmc`_ library; on a VME system it depends also on the VME bridge
+driver from CERN BE-CEM.
 ::
-      $ cd /path/to/fmc-adc-100m14b4cha-sw/kernel
+      $ cd /path/to/fmc-adc-100m14b4cha/software/kernel
      $ export LINUX=/path/to/linux/sources
      $ export ZIO=/path/to/zio
      $ export FMC=/path/to/fmc-sw
@@ -106,18 +108,18 @@ temp_calib_period=NUMBER
 Device Abstraction
 ==================
-This driver is based on the ZIO framework and the fmc-bus. It supports
+This driver is based on the ZIO framework. It supports initial setup
-initial setup of the board; it allows users to manually configure the
+of the board; it allows users to manually configure the board, to
-board, to start and stop acquisitions, to force trigger, to read
+start and stop acquisitions, to force trigger, to read acquisition
-acquisition time-stamps and to read acquired samples.
+time-stamps and to read acquired samples.
 The driver is designed as a ZIO driver. ZIO is a framework for
 input/output hosted on http://www.ohwr.org/projects/zio.
 ZIO devices are organized as csets (channel sets), and each of them
-includes channels. This device offers one cset and four channels.
+includes channels. All channels belonging to the same cset trigger
-However, the device can only stores interleaved data for all four
+together. This device offers one cset with four channels.  However,
-channels.
+the device can only stores interleaved data for all four channels.
 The current approach to this is defining 5 channels: channels 0 to 3 are
 the actual input connectors, and their software counterpart is used to
@@ -174,7 +176,7 @@ The Channel Set
 The ADC has 1 Channel Set named ``cset0``. Its attributes are used to
 control the ADC state machine, the channel parameters and so on.
-Some attributes are channel-specific, and one may thing they should live
+Some attributes are channel-specific, and one may think they should live
 at channel-level. Unfortunately, ZIO currently lacks the mechanisms to
 convey channel attributes in the meta-data associated with an
 interleaved acquisition (where several channels coexist), and for this
@@ -520,10 +522,7 @@ write-only device files (in this case they are both read-only).
 If more than one board is probed for, you'll have two or more similar
 pairs of devices, differing in the dev_id field, i.e. the ``0200`` shown
-above. The dev_id field is built using the PCI bus and the devfn octet;
+above. The dev_id field is assigned by the Linux kernel platform subsystem.
-the example above refers to slot 0 of bus 2. (Most of the time each
-PCI-E physical slot is mapped as a bus, so the slot number is usually
-zero).
 The ADC hardware does not allow to read data from a specific channel;
 data is only transferred as an interleaved block of samples. Neither the

--- a/hdl/cheby/fmc_adc_100Ms_channel_regs.vhd
+++ b/hdl/cheby/fmc_adc_100Ms_channel_regs.vhd
@@ -2,9 +2,10 @@
 --
 -- SPDX-License-Identifier: CC-BY-SA-4.0 OR CERN-OHL-W-2.0+ OR GPL-2.0-or-later
-- Do not edit; this file was generated by Cheby using these options:
+-- Do not edit.  Generated by cheby 1.5.dev0 using these options:
 --  -i fmc_adc_100Ms_channel_regs.cheby --gen-hdl=fmc_adc_100Ms_channel_regs.vhd
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -26,6 +27,7 @@ package fmc_adc_100ms_channel_regs_pkg is
    sta_val          : std_logic_vector(15 downto 0);
  end record t_fmc_adc_100ms_ch_slave_out;
  subtype t_fmc_adc_100ms_ch_master_in is t_fmc_adc_100ms_ch_slave_out;
 end fmc_adc_100ms_channel_regs_pkg;
 library ieee;
@@ -78,7 +80,6 @@ architecture syn of fmc_adc_100ms_channel_regs is
  signal wr_req_d0                      : std_logic;
  signal wr_adr_d0                      : std_logic_vector(4 downto 2);
  signal wr_dat_d0                      : std_logic_vector(31 downto 0);
-  signal wr_sel_d0                      : std_logic_vector(3 downto 0);
 begin
  -- WB decode signals
@@ -125,7 +126,6 @@ begin
        wr_req_d0 <= wr_req_int;
        wr_adr_d0 <= adr_int;
        wr_dat_d0 <= wb_i.dat;
-        wr_sel_d0 <= wb_i.sel;
      end if;
    end if;
  end process;
@@ -219,7 +219,8 @@ begin
  end process;
  -- Process for write requests.
-  process (wr_adr_d0, wr_req_d0, ctl_wack, calib_wack, sat_wack, trig_thres_wack, trig_dly_wack) begin
+  process (wr_adr_d0, wr_req_d0, ctl_wack, calib_wack, sat_wack, trig_thres_wack,
+           trig_dly_wack) begin
    ctl_wreq <= '0';
    calib_wreq <= '0';
    sat_wreq <= '0';
@@ -255,7 +256,9 @@ begin
  end process;
  -- Process for read requests.
-  process (adr_int, rd_req_int, ctl_ssr_reg, fmc_adc_100ms_ch_i.sta_val, calib_gain_reg, calib_offset_reg, sat_val_reg, trig_thres_val_reg, trig_thres_hyst_reg, trig_dly_reg) begin
+  process (adr_int, rd_req_int, ctl_ssr_reg, fmc_adc_100ms_ch_i.sta_val,
+           calib_gain_reg, calib_offset_reg, sat_val_reg, trig_thres_val_reg,
+           trig_thres_hyst_reg, trig_dly_reg) begin
    -- By default ack read requests
    rd_dat_d0 <= (others => 'X');
    case adr_int(4 downto 2) is

--- a/hdl/cheby/fmc_adc_100Ms_csr.vhd
+++ b/hdl/cheby/fmc_adc_100Ms_csr.vhd
@@ -2,9 +2,10 @@
 --
 -- SPDX-License-Identifier: CC-BY-SA-4.0 OR CERN-OHL-W-2.0+ OR GPL-2.0-or-later
-- Do not edit; this file was generated by Cheby using these options:
+-- Do not edit.  Generated by cheby 1.5.dev0 using these options:
 --  -i fmc_adc_100Ms_csr.cheby --gen-hdl=fmc_adc_100Ms_csr.vhd
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -71,6 +72,7 @@ package fmc_adc_100ms_csr_pkg is
    samples_cnt      : std_logic_vector(31 downto 0);
  end record t_fmc_adc_100ms_csr_slave_out;
  subtype t_fmc_adc_100ms_csr_master_in is t_fmc_adc_100ms_csr_slave_out;
 end fmc_adc_100ms_csr_pkg;
 library ieee;
@@ -525,7 +527,10 @@ begin
  fmc_adc_ch4_o.dat <= wr_dat_d0;
  -- Process for write requests.
-  process (rd_adr_d0, wr_req_d0, ctl_wack, trig_en_wack, trig_pol_wack, ext_trig_dly_wack, shots_wack, downsample_wack, pre_samples_wack, post_samples_wack, fmc_adc_ch1_wack, fmc_adc_ch2_wack, fmc_adc_ch3_wack, fmc_adc_ch4_wack) begin
+  process (rd_adr_d0, wr_req_d0, ctl_wack, trig_en_wack, trig_pol_wack,
+           ext_trig_dly_wack, shots_wack, downsample_wack, pre_samples_wack,
+           post_samples_wack, fmc_adc_ch1_wack, fmc_adc_ch2_wack,
+           fmc_adc_ch3_wack, fmc_adc_ch4_wack) begin
    ctl_wreq <= '0';
    trig_en_wreq <= '0';
    trig_pol_wreq <= '0';
@@ -626,7 +631,34 @@ begin
  end process;
  -- Process for read requests.
-  process (rd_adr_d0, rd_req_d0, fmc_adc_100ms_csr_i.ctl_fsm_cmd, ctl_fmc_clk_oe_reg, ctl_offset_dac_clr_n_reg, ctl_serdes_calib_reg, ctl_trig_led_reg, ctl_acq_led_reg, fmc_adc_100ms_csr_i.ctl_clear_trig_stat, fmc_adc_100ms_csr_i.ctl_calib_apply, fmc_adc_100ms_csr_i.sta_fsm, fmc_adc_100ms_csr_i.sta_serdes_pll, fmc_adc_100ms_csr_i.sta_serdes_synced, fmc_adc_100ms_csr_i.sta_acq_cfg, fmc_adc_100ms_csr_i.sta_fmc_nr, fmc_adc_100ms_csr_i.sta_calib_busy, fmc_adc_100ms_csr_i.trig_stat_ext, fmc_adc_100ms_csr_i.trig_stat_sw, fmc_adc_100ms_csr_i.trig_stat_time, fmc_adc_100ms_csr_i.trig_stat_ch1, fmc_adc_100ms_csr_i.trig_stat_ch2, fmc_adc_100ms_csr_i.trig_stat_ch3, fmc_adc_100ms_csr_i.trig_stat_ch4, trig_en_ext_reg, fmc_adc_100ms_csr_i.trig_en_sw, trig_en_time_reg, fmc_adc_100ms_csr_i.trig_en_aux_time, trig_en_ch1_reg, trig_en_ch2_reg, trig_en_ch3_reg, trig_en_ch4_reg, trig_pol_ext_reg, trig_pol_ch1_reg, trig_pol_ch2_reg, trig_pol_ch3_reg, trig_pol_ch4_reg, ext_trig_dly_reg, shots_nbr_reg, fmc_adc_100ms_csr_i.shots_remain, fmc_adc_100ms_csr_i.multi_depth, fmc_adc_100ms_csr_i.trig_pos, fmc_adc_100ms_csr_i.fs_freq, downsample_reg, pre_samples_reg, post_samples_reg, fmc_adc_100ms_csr_i.samples_cnt, fmc_adc_ch1_i.dat, fmc_adc_ch1_rack, fmc_adc_ch2_i.dat, fmc_adc_ch2_rack, fmc_adc_ch3_i.dat, fmc_adc_ch3_rack, fmc_adc_ch4_i.dat, fmc_adc_ch4_rack) begin
+  process (rd_adr_d0, rd_req_d0, fmc_adc_100ms_csr_i.ctl_fsm_cmd,
+           ctl_fmc_clk_oe_reg, ctl_offset_dac_clr_n_reg, ctl_serdes_calib_reg,
+           ctl_trig_led_reg, ctl_acq_led_reg,
+           fmc_adc_100ms_csr_i.ctl_clear_trig_stat,
+           fmc_adc_100ms_csr_i.ctl_calib_apply, fmc_adc_100ms_csr_i.sta_fsm,
+           fmc_adc_100ms_csr_i.sta_serdes_pll,
+           fmc_adc_100ms_csr_i.sta_serdes_synced,
+           fmc_adc_100ms_csr_i.sta_acq_cfg, fmc_adc_100ms_csr_i.sta_fmc_nr,
+           fmc_adc_100ms_csr_i.sta_calib_busy,
+           fmc_adc_100ms_csr_i.trig_stat_ext,
+           fmc_adc_100ms_csr_i.trig_stat_sw,
+           fmc_adc_100ms_csr_i.trig_stat_time,
+           fmc_adc_100ms_csr_i.trig_stat_ch1,
+           fmc_adc_100ms_csr_i.trig_stat_ch2,
+           fmc_adc_100ms_csr_i.trig_stat_ch3,
+           fmc_adc_100ms_csr_i.trig_stat_ch4, trig_en_ext_reg,
+           fmc_adc_100ms_csr_i.trig_en_sw, trig_en_time_reg,
+           fmc_adc_100ms_csr_i.trig_en_aux_time, trig_en_ch1_reg,
+           trig_en_ch2_reg, trig_en_ch3_reg, trig_en_ch4_reg, trig_pol_ext_reg,
+           trig_pol_ch1_reg, trig_pol_ch2_reg, trig_pol_ch3_reg,
+           trig_pol_ch4_reg, ext_trig_dly_reg, shots_nbr_reg,
+           fmc_adc_100ms_csr_i.shots_remain, fmc_adc_100ms_csr_i.multi_depth,
+           fmc_adc_100ms_csr_i.trig_pos, fmc_adc_100ms_csr_i.fs_freq,
+           downsample_reg, pre_samples_reg, post_samples_reg,
+           fmc_adc_100ms_csr_i.samples_cnt, fmc_adc_ch1_i.dat,
+           fmc_adc_ch1_rack, fmc_adc_ch2_i.dat, fmc_adc_ch2_rack,
+           fmc_adc_ch3_i.dat, fmc_adc_ch3_rack, fmc_adc_ch4_i.dat,
+           fmc_adc_ch4_rack) begin
    -- By default ack read requests
    rd_dat_d0 <= (others => 'X');
    fmc_adc_ch1_re <= '0';

--- a/hdl/cheby/fmc_adc_aux_trigin.vhd
+++ b/hdl/cheby/fmc_adc_aux_trigin.vhd
@@ -2,9 +2,10 @@
 --
 -- SPDX-License-Identifier: CC-BY-SA-4.0 OR CERN-OHL-W-2.0+ OR GPL-2.0-or-later
-- Do not edit; this file was generated by Cheby using these options:
+-- Do not edit.  Generated by cheby 1.5.dev0 using these options:
 --  -i fmc_adc_aux_trigin.cheby --gen-hdl=fmc_adc_aux_trigin.vhd
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -53,7 +54,6 @@ architecture syn of aux_trigin is
  signal wr_req_d0                      : std_logic;
  signal wr_adr_d0                      : std_logic_vector(4 downto 2);
  signal wr_dat_d0                      : std_logic_vector(31 downto 0);
-  signal wr_sel_d0                      : std_logic_vector(3 downto 0);
 begin
  -- WB decode signals
@@ -100,7 +100,6 @@ begin
        wr_req_d0 <= wr_req_int;
        wr_adr_d0 <= adr_int;
        wr_dat_d0 <= wb_i.dat;
-        wr_sel_d0 <= wb_i.sel;
      end if;
    end if;
  end process;

--- a/hdl/cheby/fmc_adc_aux_trigout.vhd
+++ b/hdl/cheby/fmc_adc_aux_trigout.vhd
-- Do not edit.  Generated on Wed Dec 02 17:51:00 2020 by tgingold
+-- SPDX-FileCopyrightText: 2020 CERN (home.cern)
-- With Cheby 1.4.dev0 and these options:
+--
+-- SPDX-License-Identifier: CC-BY-SA-4.0 OR CERN-OHL-W-2.0+ OR GPL-2.0-or-later
+-- Do not edit.  Generated by cheby 1.5.dev0 using these options:
 --  -i fmc_adc_aux_trigout.cheby --gen-hdl=fmc_adc_aux_trigout.vhd
@@ -60,8 +63,6 @@ architecture syn of aux_trigout is
  signal rd_dat_d0                      : std_logic_vector(31 downto 0);
  signal wr_req_d0                      : std_logic;
  signal wr_adr_d0                      : std_logic_vector(4 downto 2);
-  signal wr_dat_d0                      : std_logic_vector(31 downto 0);
-  signal wr_sel_d0                      : std_logic_vector(3 downto 0);
 begin
  -- WB decode signals
@@ -107,8 +108,6 @@ begin
        wb_o.dat <= rd_dat_d0;
        wr_req_d0 <= wr_req_int;
        wr_adr_d0 <= adr_int;
-        wr_dat_d0 <= wb_i.dat;
-        wr_sel_d0 <= wb_i.sel;
      end if;
    end if;
  end process;
@@ -155,7 +154,9 @@ begin
  end process;
  -- Process for read requests.
-  process (adr_int, rd_req_int, wr_enable_i, wr_link_i, wr_valid_i, ts_present_i, ts_sec_i, ch1_mask_i, ch2_mask_i, ch3_mask_i, ch4_mask_i, ext_mask_i, cycles_i) begin
+  process (adr_int, rd_req_int, wr_enable_i, wr_link_i, wr_valid_i, ts_present_i,
+           ts_sec_i, ch1_mask_i, ch2_mask_i, ch3_mask_i, ch4_mask_i, ext_mask_i,
+           cycles_i) begin
    -- By default ack read requests
    rd_dat_d0 <= (others => 'X');
    ts_cycles_rd_o <= '0';

--- a/hdl/cheby/fmc_adc_eic_regs.vhd
+++ b/hdl/cheby/fmc_adc_eic_regs.vhd
@@ -2,9 +2,10 @@
 --
 -- SPDX-License-Identifier: CC-BY-SA-4.0 OR CERN-OHL-W-2.0+ OR GPL-2.0-or-later
-- Do not edit; this file was generated by Cheby using these options:
+-- Do not edit.  Generated by cheby 1.5.dev0 using these options:
 --  -i fmc_adc_eic_regs.cheby --gen-hdl=fmc_adc_eic_regs.vhd
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -26,6 +27,7 @@ package fmc_adc_eic_regs_pkg is
    isr              : std_logic_vector(31 downto 0);
  end record t_fmc_adc_eic_regs_slave_out;
  subtype t_fmc_adc_eic_regs_master_in is t_fmc_adc_eic_regs_slave_out;
 end fmc_adc_eic_regs_pkg;
 library ieee;
@@ -64,7 +66,6 @@ architecture syn of fmc_adc_eic_regs is
  signal wr_req_d0                      : std_logic;
  signal wr_adr_d0                      : std_logic_vector(3 downto 2);
  signal wr_dat_d0                      : std_logic_vector(31 downto 0);
-  signal wr_sel_d0                      : std_logic_vector(3 downto 0);
 begin
  -- WB decode signals
@@ -111,7 +112,6 @@ begin
        wr_req_d0 <= wr_req_int;
        wr_adr_d0 <= adr_int;
        wr_dat_d0 <= wb_i.dat;
-        wr_sel_d0 <= wb_i.sel;
      end if;
    end if;
  end process;

--- a/hdl/cheby/fmc_adc_mezzanine_mmap.vhd
+++ b/hdl/cheby/fmc_adc_mezzanine_mmap.vhd
@@ -2,9 +2,10 @@
 --
 -- SPDX-License-Identifier: CC-BY-SA-4.0 OR CERN-OHL-W-2.0+ OR GPL-2.0-or-later
-- Do not edit; this file was generated by Cheby using these options:
+-- Do not edit.  Generated by cheby 1.5.dev0 using these options:
 --  -i fmc_adc_mezzanine_mmap.cheby --gen-hdl=fmc_adc_mezzanine_mmap.vhd
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -291,7 +292,9 @@ begin
  timetag_core_o.dat <= wr_dat_d0;
  -- Process for write requests.
-  process (rd_adr_d0, wr_req_d0, fmc_adc_100m_csr_wack, fmc_adc_eic_wack, si570_i2c_master_wack, ds18b20_onewire_master_wack, fmc_spi_master_wack, timetag_core_wack) begin
+  process (rd_adr_d0, wr_req_d0, fmc_adc_100m_csr_wack, fmc_adc_eic_wack,
+           si570_i2c_master_wack, ds18b20_onewire_master_wack,
+           fmc_spi_master_wack, timetag_core_wack) begin
    fmc_adc_100m_csr_we <= '0';
    fmc_adc_eic_we <= '0';
    si570_i2c_master_we <= '0';
@@ -339,7 +342,11 @@ begin
  end process;
  -- Process for read requests.
-  process (rd_adr_d0, rd_req_d0, fmc_adc_100m_csr_i.dat, fmc_adc_100m_csr_rack, fmc_adc_eic_i.dat, fmc_adc_eic_rack, si570_i2c_master_i.dat, si570_i2c_master_rack, ds18b20_onewire_master_i.dat, ds18b20_onewire_master_rack, fmc_spi_master_i.dat, fmc_spi_master_rack, timetag_core_i.dat, timetag_core_rack) begin
+  process (rd_adr_d0, rd_req_d0, fmc_adc_100m_csr_i.dat, fmc_adc_100m_csr_rack,
+           fmc_adc_eic_i.dat, fmc_adc_eic_rack, si570_i2c_master_i.dat,
+           si570_i2c_master_rack, ds18b20_onewire_master_i.dat,
+           ds18b20_onewire_master_rack, fmc_spi_master_i.dat,
+           fmc_spi_master_rack, timetag_core_i.dat, timetag_core_rack) begin
    -- By default ack read requests
    rd_dat_d0 <= (others => 'X');
    fmc_adc_100m_csr_re <= '0';

--- a/hdl/cheby/spec_ref_fmc_adc_100Ms_mmap.vhd
+++ b/hdl/cheby/spec_ref_fmc_adc_100Ms_mmap.vhd
@@ -2,9 +2,10 @@
 --
 -- SPDX-License-Identifier: CC-BY-SA-4.0 OR CERN-OHL-W-2.0+ OR GPL-2.0-or-later
-- Do not edit; this file was generated by Cheby using these options:
+-- Do not edit.  Generated by cheby 1.5.dev0 using these options:
 --  -i spec_ref_fmc_adc_100Ms_mmap.cheby --gen-hdl=spec_ref_fmc_adc_100Ms_mmap.vhd
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -171,7 +172,8 @@ begin
  end process;
  -- Process for read requests.
-  process (adr_int, rd_req_int, metadata_i.dat, metadata_rack, fmc_adc_mezzanine_i.dat, fmc_adc_mezzanine_rack) begin
+  process (adr_int, rd_req_int, metadata_i.dat, metadata_rack,
+           fmc_adc_mezzanine_i.dat, fmc_adc_mezzanine_rack) begin
    -- By default ack read requests
    rd_dat_d0 <= (others => 'X');
    metadata_re <= '0';

--- a/hdl/cheby/svec_ref_fmc_adc_100Ms_mmap.cheby
+++ b/hdl/cheby/svec_ref_fmc_adc_100Ms_mmap.cheby
@@ -5,7 +5,7 @@
 memory-map:
  name: svec_ref_fmc_adc_100m_mmap
  bus: wb-32-be
-  description: SPEC FMC-ADC-100M memory map
+  description: SVEC FMC-ADC-100M memory map
  size: 0x10000
  x-hdl:
    busgroup: True

--- a/hdl/cheby/svec_ref_fmc_adc_100Ms_mmap.vhd
+++ b/hdl/cheby/svec_ref_fmc_adc_100Ms_mmap.vhd
@@ -2,9 +2,10 @@
 --
 -- SPDX-License-Identifier: CC-BY-SA-4.0 OR CERN-OHL-W-2.0+ OR GPL-2.0-or-later
-- Do not edit; this file was generated by Cheby using these options:
+-- Do not edit.  Generated by cheby 1.5.dev0 using these options:
 --  -i svec_ref_fmc_adc_100Ms_mmap.cheby --gen-hdl=svec_ref_fmc_adc_100Ms_mmap.vhd
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -192,7 +193,8 @@ begin
  fmc2_adc_mezzanine_o.dat <= wr_dat_d0;
  -- Process for write requests.
-  process (rd_adr_d0, wr_req_d0, metadata_wack, fmc1_adc_mezzanine_wack, fmc2_adc_mezzanine_wack) begin
+  process (rd_adr_d0, wr_req_d0, metadata_wack, fmc1_adc_mezzanine_wack,
+           fmc2_adc_mezzanine_wack) begin
    metadata_we <= '0';
    fmc1_adc_mezzanine_we <= '0';
    fmc2_adc_mezzanine_we <= '0';
@@ -215,7 +217,9 @@ begin
  end process;
  -- Process for read requests.
-  process (rd_adr_d0, rd_req_d0, metadata_i.dat, metadata_rack, fmc1_adc_mezzanine_i.dat, fmc1_adc_mezzanine_rack, fmc2_adc_mezzanine_i.dat, fmc2_adc_mezzanine_rack) begin
+  process (rd_adr_d0, rd_req_d0, metadata_i.dat, metadata_rack,
+           fmc1_adc_mezzanine_i.dat, fmc1_adc_mezzanine_rack,
+           fmc2_adc_mezzanine_i.dat, fmc2_adc_mezzanine_rack) begin
    -- By default ack read requests
    rd_dat_d0 <= (others => 'X');
    metadata_re <= '0';

--- a/hdl/cheby/timetag_core_regs.vhd
+++ b/hdl/cheby/timetag_core_regs.vhd
@@ -2,9 +2,10 @@
 --
 -- SPDX-License-Identifier: CC-BY-SA-4.0 OR CERN-OHL-W-2.0+ OR GPL-2.0-or-later
-- Do not edit; this file was generated by Cheby using these options:
+-- Do not edit.  Generated by cheby 1.5.dev0 using these options:
 --  -i timetag_core_regs.cheby --gen-hdl=timetag_core_regs.vhd
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -42,6 +43,7 @@ package timetag_core_regs_pkg is
    acq_end_tag_coarse : std_logic_vector(27 downto 0);
  end record t_timetag_core_slave_out;
  subtype t_timetag_core_master_in is t_timetag_core_slave_out;
 end timetag_core_regs_pkg;
 library ieee;
@@ -89,7 +91,6 @@ architecture syn of timetag_core_regs is
  signal wr_req_d0                      : std_logic;
  signal wr_adr_d0                      : std_logic_vector(6 downto 2);
  signal wr_dat_d0                      : std_logic_vector(31 downto 0);
-  signal wr_sel_d0                      : std_logic_vector(3 downto 0);
 begin
  -- WB decode signals
@@ -136,7 +137,6 @@ begin
        wr_req_d0 <= wr_req_int;
        wr_adr_d0 <= adr_int;
        wr_dat_d0 <= wb_i.dat;
-        wr_sel_d0 <= wb_i.sel;
      end if;
    end if;
  end process;
@@ -226,7 +226,8 @@ begin
  -- Register acq_end_tag_coarse
  -- Process for write requests.
-  process (wr_adr_d0, wr_req_d0, time_trig_seconds_upper_wack, time_trig_seconds_lower_wack, time_trig_coarse_wack) begin
+  process (wr_adr_d0, wr_req_d0, time_trig_seconds_upper_wack,
+           time_trig_seconds_lower_wack, time_trig_coarse_wack) begin
    seconds_upper_wreq <= '0';
    seconds_lower_wreq <= '0';
    coarse_wreq <= '0';
@@ -300,7 +301,21 @@ begin
  end process;
  -- Process for read requests.
-  process (adr_int, rd_req_int, timetag_core_i.seconds_upper, timetag_core_i.seconds_lower, timetag_core_i.coarse, time_trig_seconds_upper_reg, time_trig_seconds_lower_reg, time_trig_coarse_reg, timetag_core_i.trig_tag_seconds_upper, timetag_core_i.trig_tag_seconds_lower, timetag_core_i.trig_tag_coarse, timetag_core_i.acq_start_tag_seconds_upper, timetag_core_i.acq_start_tag_seconds_lower, timetag_core_i.acq_start_tag_coarse, timetag_core_i.acq_stop_tag_seconds_upper, timetag_core_i.acq_stop_tag_seconds_lower, timetag_core_i.acq_stop_tag_coarse, timetag_core_i.acq_end_tag_seconds_upper, timetag_core_i.acq_end_tag_seconds_lower, timetag_core_i.acq_end_tag_coarse) begin
+  process (adr_int, rd_req_int, timetag_core_i.seconds_upper,
+           timetag_core_i.seconds_lower, timetag_core_i.coarse,
+           time_trig_seconds_upper_reg, time_trig_seconds_lower_reg,
+           time_trig_coarse_reg, timetag_core_i.trig_tag_seconds_upper,
+           timetag_core_i.trig_tag_seconds_lower,
+           timetag_core_i.trig_tag_coarse,
+           timetag_core_i.acq_start_tag_seconds_upper,
+           timetag_core_i.acq_start_tag_seconds_lower,
+           timetag_core_i.acq_start_tag_coarse,
+           timetag_core_i.acq_stop_tag_seconds_upper,
+           timetag_core_i.acq_stop_tag_seconds_lower,
+           timetag_core_i.acq_stop_tag_coarse,
+           timetag_core_i.acq_end_tag_seconds_upper,
+           timetag_core_i.acq_end_tag_seconds_lower,
+           timetag_core_i.acq_end_tag_coarse) begin
    -- By default ack read requests
    rd_dat_d0 <= (others => 'X');
    case adr_int(6 downto 2) is

--- a/wr-cores @ 3884a655
+++ b/wr-cores @ 3884a655
-Subproject commit a72a4223e2e1b521ba839f5623ee2857cf4fae10
+Subproject commit 3884a65545907de3a0d41d549a4be9e6cccb4916
--- a/hdl/testbench/include/fmc_adc_100Ms_csr.v
+++ b/hdl/testbench/include/fmc_adc_100Ms_csr.v
@@ -91,10 +91,14 @@
 `define ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES 'h34
 `define ADDR_FMC_ADC_100MS_CSR_SAMPLES_CNT 'h38
 `define ADDR_FMC_ADC_100MS_CSR_FMC_ADC_CH1 'h80
+`define ADDR_MASK_FMC_ADC_100MS_CSR_FMC_ADC_CH1 'h1e0
 `define FMC_ADC_100MS_CSR_FMC_ADC_CH1_SIZE 32
 `define ADDR_FMC_ADC_100MS_CSR_FMC_ADC_CH2 'hc0
+`define ADDR_MASK_FMC_ADC_100MS_CSR_FMC_ADC_CH2 'h1e0
 `define FMC_ADC_100MS_CSR_FMC_ADC_CH2_SIZE 32
 `define ADDR_FMC_ADC_100MS_CSR_FMC_ADC_CH3 'h100
+`define ADDR_MASK_FMC_ADC_100MS_CSR_FMC_ADC_CH3 'h1e0
 `define FMC_ADC_100MS_CSR_FMC_ADC_CH3_SIZE 32
 `define ADDR_FMC_ADC_100MS_CSR_FMC_ADC_CH4 'h140
+`define ADDR_MASK_FMC_ADC_100MS_CSR_FMC_ADC_CH4 'h1e0
 `define FMC_ADC_100MS_CSR_FMC_ADC_CH4_SIZE 32
--- a/hdl/testbench/include/fmc_adc_mezzanine_mmap.v
+++ b/hdl/testbench/include/fmc_adc_mezzanine_mmap.v
@@ -4,14 +4,20 @@
 `define FMC_ADC_MEZZANINE_MMAP_SIZE 8192
 `define ADDR_FMC_ADC_MEZZANINE_MMAP_FMC_ADC_100M_CSR 'h1000
+`define ADDR_MASK_FMC_ADC_MEZZANINE_MMAP_FMC_ADC_100M_CSR 'h1e00
 `define FMC_ADC_MEZZANINE_MMAP_FMC_ADC_100M_CSR_SIZE 512
 `define ADDR_FMC_ADC_MEZZANINE_MMAP_FMC_ADC_EIC 'h1500
+`define ADDR_MASK_FMC_ADC_MEZZANINE_MMAP_FMC_ADC_EIC 'h1ff0
 `define FMC_ADC_MEZZANINE_MMAP_FMC_ADC_EIC_SIZE 16
 `define ADDR_FMC_ADC_MEZZANINE_MMAP_SI570_I2C_MASTER 'h1600
+`define ADDR_MASK_FMC_ADC_MEZZANINE_MMAP_SI570_I2C_MASTER 'h1f00
 `define FMC_ADC_MEZZANINE_MMAP_SI570_I2C_MASTER_SIZE 256
 `define ADDR_FMC_ADC_MEZZANINE_MMAP_DS18B20_ONEWIRE_MASTER 'h1700
+`define ADDR_MASK_FMC_ADC_MEZZANINE_MMAP_DS18B20_ONEWIRE_MASTER 'h1ff0
 `define FMC_ADC_MEZZANINE_MMAP_DS18B20_ONEWIRE_MASTER_SIZE 16
 `define ADDR_FMC_ADC_MEZZANINE_MMAP_FMC_SPI_MASTER 'h1800
+`define ADDR_MASK_FMC_ADC_MEZZANINE_MMAP_FMC_SPI_MASTER 'h1fe0
 `define FMC_ADC_MEZZANINE_MMAP_FMC_SPI_MASTER_SIZE 32
 `define ADDR_FMC_ADC_MEZZANINE_MMAP_TIMETAG_CORE 'h1900
+`define ADDR_MASK_FMC_ADC_MEZZANINE_MMAP_TIMETAG_CORE 'h1f80
 `define FMC_ADC_MEZZANINE_MMAP_TIMETAG_CORE_SIZE 128
--- a/hdl/testbench/include/spec_ref_fmc_adc_100Ms_mmap.v
+++ b/hdl/testbench/include/spec_ref_fmc_adc_100Ms_mmap.v
@@ -4,6 +4,8 @@
 `define SPEC_REF_FMC_ADC_100M_MMAP_SIZE 24576
 `define ADDR_SPEC_REF_FMC_ADC_100M_MMAP_METADATA 'h2000
+`define ADDR_MASK_SPEC_REF_FMC_ADC_100M_MMAP_METADATA 'h7fc0
 `define SPEC_REF_FMC_ADC_100M_MMAP_METADATA_SIZE 64
 `define ADDR_SPEC_REF_FMC_ADC_100M_MMAP_FMC_ADC_MEZZANINE 'h4000
+`define ADDR_MASK_SPEC_REF_FMC_ADC_100M_MMAP_FMC_ADC_MEZZANINE 'h6000
 `define SPEC_REF_FMC_ADC_100M_MMAP_FMC_ADC_MEZZANINE_SIZE 8192
--- a/hdl/testbench/include/svec_ref_fmc_adc_100Ms_mmap.v
+++ b/hdl/testbench/include/svec_ref_fmc_adc_100Ms_mmap.v
@@ -4,8 +4,11 @@
 `define SVEC_REF_FMC_ADC_100M_MMAP_SIZE 65536
 `define ADDR_SVEC_REF_FMC_ADC_100M_MMAP_METADATA 'h4000
+`define ADDR_MASK_SVEC_REF_FMC_ADC_100M_MMAP_METADATA 'hffc0
 `define SVEC_REF_FMC_ADC_100M_MMAP_METADATA_SIZE 64
 `define ADDR_SVEC_REF_FMC_ADC_100M_MMAP_FMC1_ADC_MEZZANINE 'h6000
+`define ADDR_MASK_SVEC_REF_FMC_ADC_100M_MMAP_FMC1_ADC_MEZZANINE 'he000
 `define SVEC_REF_FMC_ADC_100M_MMAP_FMC1_ADC_MEZZANINE_SIZE 8192
 `define ADDR_SVEC_REF_FMC_ADC_100M_MMAP_FMC2_ADC_MEZZANINE 'h8000
+`define ADDR_MASK_SVEC_REF_FMC_ADC_100M_MMAP_FMC2_ADC_MEZZANINE 'he000
 `define SVEC_REF_FMC_ADC_100M_MMAP_FMC2_ADC_MEZZANINE_SIZE 8192
--- a/hdl/top/svec_ref_design/svec_ref_fmc_adc_100Ms.vhd
+++ b/hdl/top/svec_ref_design/svec_ref_fmc_adc_100Ms.vhd
@@ -534,7 +534,7 @@ begin -- architecture arch
    cmp_fmc_adc_mezzanine : entity work.fmc_adc_mezzanine
      generic map (
        g_MULTISHOT_RAM_SIZE => g_MULTISHOT_RAM_SIZE,
-        g_SPARTAN6_USE_PLL   => TRUE,
+        g_SPARTAN6_USE_PLL   => FALSE, -- I = 0, -- PLL on fmc0, no PLL on FMC 1
        g_BYTE_SWAP          => TRUE,
        g_FMC_ADC_NR         => I,
        g_WB_MODE            => PIPELINED,

--- a/software/include/hw/fmc_adc_100Ms_csr.h
+++ b/software/include/hw/fmc_adc_100Ms_csr.h
@@ -10,7 +10,7 @@
 #define FMC_ADC_100MS_CSR_CTL_FSM_CMD_SHIFT 0
 #define FMC_ADC_100MS_CSR_CTL_FMC_CLK_OE 0x4UL
 #define FMC_ADC_100MS_CSR_CTL_OFFSET_DAC_CLR_N 0x8UL
-#define FMC_ADC_100MS_CSR_CTL_MAN_BITSLIP 0x10UL
+#define FMC_ADC_100MS_CSR_CTL_SERDES_CALIB 0x10UL
 #define FMC_ADC_100MS_CSR_CTL_TRIG_LED 0x40UL
 #define FMC_ADC_100MS_CSR_CTL_ACQ_LED 0x80UL
 #define FMC_ADC_100MS_CSR_CTL_CLEAR_TRIG_STAT 0x100UL
@@ -92,18 +92,22 @@
 /* Channel 1 registers */
 #define FMC_ADC_100MS_CSR_FMC_ADC_CH1 0x80UL
+#define ADDR_MASK_FMC_ADC_100MS_CSR_FMC_ADC_CH1 0x1e0UL
 #define FMC_ADC_100MS_CSR_FMC_ADC_CH1_SIZE 32 /* 0x20 */
 /* Channel 2 registers */
 #define FMC_ADC_100MS_CSR_FMC_ADC_CH2 0xc0UL
+#define ADDR_MASK_FMC_ADC_100MS_CSR_FMC_ADC_CH2 0x1e0UL
 #define FMC_ADC_100MS_CSR_FMC_ADC_CH2_SIZE 32 /* 0x20 */
 /* Channel 3 registers */
 #define FMC_ADC_100MS_CSR_FMC_ADC_CH3 0x100UL
+#define ADDR_MASK_FMC_ADC_100MS_CSR_FMC_ADC_CH3 0x1e0UL
 #define FMC_ADC_100MS_CSR_FMC_ADC_CH3_SIZE 32 /* 0x20 */
 /* Channel 4 registers */
 #define FMC_ADC_100MS_CSR_FMC_ADC_CH4 0x140UL
+#define ADDR_MASK_FMC_ADC_100MS_CSR_FMC_ADC_CH4 0x1e0UL
 #define FMC_ADC_100MS_CSR_FMC_ADC_CH4_SIZE 32 /* 0x20 */
 struct fmc_adc_100ms_csr {

--- a/software/include/hw/fmc_adc_mezzanine_mmap.h
+++ b/software/include/hw/fmc_adc_mezzanine_mmap.h
 #ifndef __CHEBY__FMC_ADC_MEZZANINE_MMAP__H__
 #define __CHEBY__FMC_ADC_MEZZANINE_MMAP__H__
-#include "fmc_adc_eic_regs.h"
 #include "fmc_adc_100ms_csr.h"
-#include "timetag_core_regs.h"
+#include "fmc_adc_eic_regs.h"
 #include "wb_ds182x_regs.h"
+#include "timetag_core_regs.h"
 #define FMC_ADC_MEZZANINE_MMAP_SIZE 8192 /* 0x2000 = 8KB */
 /* FMC ADC 100M CSR */
 #define FMC_ADC_MEZZANINE_MMAP_FMC_ADC_100M_CSR 0x1000UL
+#define ADDR_MASK_FMC_ADC_MEZZANINE_MMAP_FMC_ADC_100M_CSR 0x1e00UL
 #define FMC_ADC_MEZZANINE_MMAP_FMC_ADC_100M_CSR_SIZE 512 /* 0x200 */
 /* FMC ADC Embedded Interrupt Controller */
 #define FMC_ADC_MEZZANINE_MMAP_FMC_ADC_EIC 0x1500UL
+#define ADDR_MASK_FMC_ADC_MEZZANINE_MMAP_FMC_ADC_EIC 0x1ff0UL
 #define FMC_ADC_MEZZANINE_MMAP_FMC_ADC_EIC_SIZE 16 /* 0x10 */
 /* Si570 control I2C master */
 #define FMC_ADC_MEZZANINE_MMAP_SI570_I2C_MASTER 0x1600UL
+#define ADDR_MASK_FMC_ADC_MEZZANINE_MMAP_SI570_I2C_MASTER 0x1f00UL
 #define FMC_ADC_MEZZANINE_MMAP_SI570_I2C_MASTER_SIZE 256 /* 0x100 */
 /* DS18B20 OneWire master */
 #define FMC_ADC_MEZZANINE_MMAP_DS18B20_ONEWIRE_MASTER 0x1700UL
+#define ADDR_MASK_FMC_ADC_MEZZANINE_MMAP_DS18B20_ONEWIRE_MASTER 0x1ff0UL
 #define FMC_ADC_MEZZANINE_MMAP_DS18B20_ONEWIRE_MASTER_SIZE 16 /* 0x10 */
 /* Mezzanine SPI master (ADC control + DAC offsets) */
 #define FMC_ADC_MEZZANINE_MMAP_FMC_SPI_MASTER 0x1800UL
+#define ADDR_MASK_FMC_ADC_MEZZANINE_MMAP_FMC_SPI_MASTER 0x1fe0UL
 #define FMC_ADC_MEZZANINE_MMAP_FMC_SPI_MASTER_SIZE 32 /* 0x20 */
 /* Timetag Core */
 #define FMC_ADC_MEZZANINE_MMAP_TIMETAG_CORE 0x1900UL
+#define ADDR_MASK_FMC_ADC_MEZZANINE_MMAP_TIMETAG_CORE 0x1f80UL
 #define FMC_ADC_MEZZANINE_MMAP_TIMETAG_CORE_SIZE 128 /* 0x80 */
 struct fmc_adc_mezzanine_mmap {

--- a/software/include/hw/spec_ref_fmc_adc_100Ms_mmap.h
+++ b/software/include/hw/spec_ref_fmc_adc_100Ms_mmap.h
@@ -6,10 +6,12 @@
 /* a ROM containing the application metadata */
 #define SPEC_REF_FMC_ADC_100M_MMAP_METADATA 0x2000UL
+#define ADDR_MASK_SPEC_REF_FMC_ADC_100M_MMAP_METADATA 0x7fc0UL
 #define SPEC_REF_FMC_ADC_100M_MMAP_METADATA_SIZE 64 /* 0x40 */
 /* FMC ADC Mezzanine */
 #define SPEC_REF_FMC_ADC_100M_MMAP_FMC_ADC_MEZZANINE 0x4000UL
+#define ADDR_MASK_SPEC_REF_FMC_ADC_100M_MMAP_FMC_ADC_MEZZANINE 0x6000UL
 #define SPEC_REF_FMC_ADC_100M_MMAP_FMC_ADC_MEZZANINE_SIZE 8192 /* 0x2000 = 8KB */
 struct spec_ref_fmc_adc_100m_mmap {

--- a/software/include/hw/svec_ref_fmc_adc_100Ms_mmap.h
+++ b/software/include/hw/svec_ref_fmc_adc_100Ms_mmap.h
@@ -6,14 +6,17 @@
 /* a ROM containing the application metadata */
 #define SVEC_REF_FMC_ADC_100M_MMAP_METADATA 0x4000UL
+#define ADDR_MASK_SVEC_REF_FMC_ADC_100M_MMAP_METADATA 0xffc0UL
 #define SVEC_REF_FMC_ADC_100M_MMAP_METADATA_SIZE 64 /* 0x40 */
 /* FMC ADC Mezzanine slot 1 */
 #define SVEC_REF_FMC_ADC_100M_MMAP_FMC1_ADC_MEZZANINE 0x6000UL
+#define ADDR_MASK_SVEC_REF_FMC_ADC_100M_MMAP_FMC1_ADC_MEZZANINE 0xe000UL
 #define SVEC_REF_FMC_ADC_100M_MMAP_FMC1_ADC_MEZZANINE_SIZE 8192 /* 0x2000 = 8KB */
 /* FMC ADC Mezzanine slot 2 */
 #define SVEC_REF_FMC_ADC_100M_MMAP_FMC2_ADC_MEZZANINE 0x8000UL
+#define ADDR_MASK_SVEC_REF_FMC_ADC_100M_MMAP_FMC2_ADC_MEZZANINE 0xe000UL
 #define SVEC_REF_FMC_ADC_100M_MMAP_FMC2_ADC_MEZZANINE_SIZE 8192 /* 0x2000 = 8KB */
 struct svec_ref_fmc_adc_100m_mmap {