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F
FMC ADC 100M 14b 4cha
Commit b0544ee0 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: fail CI if FPGA designs do not meet timing

parent 85d82074
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hdl/syn/.gitlab-ci.yml
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......@@ -14,6 +14,12 @@
- cd hdl/syn/"$SYN_NAME"/
- hdlmake
- make
- |
if [[ $(cat *.par | grep -c "All constraints were met") = 0 ]]
then
echo -e "\e[31mTiming errors detected in PAR report. Aborting...\e[0m"
exit 1
fi
artifacts:
name: "$SYN_NAME-synthesis-$CI_JOB_NAME-$CI_COMMIT_REF_NAME"
paths:
......
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