spec: add missing synchroniser

a4e869b1 · Dimitris Lampridis · 9d1504c9 · a4e869b1
Commit a4e869b1 authored May 20, 2019 by Dimitris Lampridis
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spec_ref_fmc_adc_100Ms.vhd hdl/top/spec_ref_design/spec_ref_fmc_adc_100Ms.vhd +9 -1

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--- a/hdl/top/spec_ref_design/spec_ref_fmc_adc_100Ms.vhd
+++ b/hdl/top/spec_ref_design/spec_ref_fmc_adc_100Ms.vhd
@@ -432,6 +432,7 @@ architecture rtl of spec_ref_fmc_adc_100Ms is
  signal tm_tai             : std_logic_vector(39 downto 0);
  signal tm_cycles          : std_logic_vector(27 downto 0);
  signal tm_time_valid      : std_logic;
+
  -- re-synced to ref clock
  signal tm_time_valid_sync : std_logic;

@@ -749,6 +750,13 @@ begin
      data_i   => ddr_wr_fifo_empty,
      synced_o => ddr_wr_fifo_empty_sync);

+  cmp_tm_time_valid_sync : gc_sync_ffs
+    port map (
+      clk_i    => clk_ref_125m,
+      rst_n_i  => '1',
+      data_i   => tm_time_valid,
+      synced_o => tm_time_valid_sync);
+
  cmp_fmc_adc_mezzanine : fmc_adc_mezzanine
    generic map (
      g_MULTISHOT_RAM_SIZE => g_MULTISHOT_RAM_SIZE,
@@ -812,7 +820,7 @@ begin
      sys_sda_b => fmc_sda_b,

      wr_tm_link_up_i    => tm_link_up,
-      wr_tm_time_valid_i => tm_time_valid,
+      wr_tm_time_valid_i => tm_time_valid_sync,
      wr_tm_tai_i        => tm_tai,
      wr_tm_cycles_i     => tm_cycles,
      wr_enable_i        => wrabbit_en