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FMC ADC 100M 14b 4cha
Commit a3a2724b authored by Federico Vaga's avatar Federico Vaga
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Merge branch 'release/v5.0.0' into master

parents 7cc993f1 c0a9675b
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CHANGELOG.rst
View file @ a3a2724b
......@@ -6,7 +6,7 @@
Changelog
=========
5.0.0 - 2020-01-01
5.0.0 - 2021-02-11
==================
Changes
-------
......@@ -26,9 +26,9 @@ Added
- add tool to get/set run-time calibration data
- periodically update gain calibration for DAC and ADC
- trigger time
- MBLT support for SVEC
Removed
-------
- library is not supported anymore, use adc-lib (https://www.ohwr.org/projects/adc-lib)
- fald-acq tool is not supported anymore, use adc-acq from adc-lib (https://www.ohwr.org/projects/adc-lib)
doc/conf.py
View file @ a3a2724b
......@@ -22,7 +22,7 @@
# -- Project information -----------------------------------------------------
project = 'FMC-ADC-100M-14B-4CHA'
copyright = u'2013-2020, CERN, documentation released under CC-BY-SA-4.0'
copyright = u'2013-2021, CERN, documentation released under CC-BY-SA-4.0'
author = 'Matthieu Cattin, Dimitris Lampridis <dimitrios.lampridis@cern.ch>, Federico Vaga <federico.vaga@cern.ch>'
# The suffix(es) of source filenames.
......
doc/fig/Makefile
View file @ a3a2724b
......@@ -9,7 +9,7 @@ PDF=$(SVG:.svg=.pdf)
all: $(PDF)
%.pdf : %.svg
inkscape --without-gui $< -A $@
inkscape $< -o $@ || inkscape --without-gui $< -A $@
clean:
rm -f $(PDF)
......
doc/gateware/index.rst
View file @ a3a2724b
......@@ -103,12 +103,21 @@ There are two different Wishbone bus interconnects in the design.
Mapped WB bus (blue)
This bus connects all the peripherals to the GN4142 core.
Data: 32-bit, address: 32-bit (word aligned), clock: system clock (125MHz).
Data: 32-bit, address: 32-bit (word aligned),
Clock: system clock (125MHz) and system clock / 2 (62.5MHz), see note below.
ADC core to memory controller (orange)
This bus is used to write samples from the ADC core to the DDR memory.
Data: 64-bit, address: 32-bit (word aligned), clock: system clock (125MHz).
.. note::
The SPEC-base core works internally at 62.5MHz, especially for the WR PTP
core. On the other hand, the ADC core needs to work at 125MHz in order to
be able to retrieve and process the incoming ADC samples at 100MHz (from
the ``fs_clk`` domain). Therefore, a Wishbone clock crossing component is
inserted between the SPEC-base core and the ADC core. With this topology,
only the SPEC-base core runs at a lower frequency.
Note that some of the cores from the `General Cores`_ library are
based on cores from `OpenCores`_. Therefore, the documentation for
those cores is hosted on the OpenCores website.
......@@ -116,28 +125,31 @@ those cores is hosted on the OpenCores website.
Clock Domains
~~~~~~~~~~~~~
The SPEC version of the fmc-adc design has five different clock domains.
The SPEC version of the fmc-adc design has six different clock domains.
They are listed in the following table.
+-----------------+-----------------+-----------------+-----------------+
| Name | Description | Frequency | Source |
+=================+=================+=================+=================+
| ``sys_clk_125`` | Main system | 125.00 MHz | 20MHz TCXO |
| | clock | | (carrier) |
+-----------------+-----------------+-----------------+-----------------+
| ``ddr_clk`` | DDR interface | 333.33 MHz | 20MHz TCXO |
| | clock | | (carrier) |
+-----------------+-----------------+-----------------+-----------------+
| ``fs_clk`` | Sampling clock | 100.00 MHz | 400MHz LTC2174 |
| | | | (mezzanine) |
+-----------------+-----------------+-----------------+-----------------+
| ``serdes_clk`` | ADC data | 800.00 MHz | 400MHz LTC2174 |
| | de-serialiser | | (mezzanine) |
| | clock | | |
+-----------------+-----------------+-----------------+-----------------+
| ``p2l_clk`` | Local bus clock | 200.00 MHz | 200MHz GN4124 |
| | | | (carrier) |
+-----------------+-----------------+-----------------+-----------------+
+------------------+-----------------+-----------------+-----------------+
| Name | Description | Frequency | Source |
+==================+=================+=================+=================+
| ``clk_ref_125m`` | Main system | 125.00 MHz | 125MHz VCXO |
| | clock | | (carrier) |
+------------------+-----------------+-----------------+-----------------+
| ``clk_sys_62m5`` | System clock | 62.50 MHz | 125MHz VCXO |
| | for spec-base | | (carrier) |
+------------------+-----------------+-----------------+-----------------+
| ``clk_333m_ddr`` | DDR interface | 333.33 MHz | 125MHz VCXO |
| | clock | | (carrier) |
+------------------+-----------------+-----------------+-----------------+
| ``fs_clk`` | Sampling clock | 100.00 MHz | 400MHz LTC2174 |
| | | | (mezzanine) |
+------------------+-----------------+-----------------+-----------------+
| ``adc_dco`` | ADC data | 800.00 MHz | 400MHz LTC2174 |
| | de-serialiser | | (mezzanine) |
| | clock | | |
+------------------+-----------------+-----------------+-----------------+
| ``p2l_clk`` | PCI to Local | 200.00 MHz | 200MHz GN4124 |
| | bus clock | | (carrier) |
+------------------+-----------------+-----------------+-----------------+
SVEC (VME64x carrier)
---------------------
......@@ -167,39 +179,49 @@ ADC cores to memory controllers (2x, orange)
Data: 64-bit, address: 32-bit (word aligned), clock: system clock (125MHz).
.. note::
The VME64x core cannot work with a clock frequency as high as
125MHz, therefore it is clocked with half the system clock
frequency. As the fmc-adc core needs 125MHz to work properly, a
Wishbone clock crossing component is inserted between the VME64x core
and the first Wishbone crossbar component. With this topology, only
the VME64x core runs at a lower frequency.
The SVEC-base core works internally at 62.5MHz, especially for the WR PTP
core. On the other hand, the ADC core needs to work at 125MHz in order to
be able to retrieve and process the incoming ADC samples at 100MHz (from
the ``fs_clk`` domain). Therefore, a Wishbone clock crossing component is
inserted between the SVEC-base core and the ADC core. With this topology,
only the SVEC-base core runs at a lower frequency.
Note that some of the cores from the `General Cores`_ library are
based on cores from `OpenCores`_. Therefore, the documentation for
those cores is hosted on the OpenCores website.
Clock Domains
~~~~~~~~~~~~~
The SVEC version of the fmc-adc design has five different clock domains.
The SVEC version of the fmc-adc design has seven different clock domains.
They are listed in the following table.
+-----------------+-----------------+-----------------+-----------------+
| Name | Description | Frequency | Source |
+=================+=================+=================+=================+
| sys_clk_125 | Main system | 125.00 MHz | 20MHz TCXO |
| | clock | | (carrier) |
+-----------------+-----------------+-----------------+-----------------+
| sys_clk_62_5 | System clock / | 62.50 MHz | 20MHz TCXO |
| | 2 | | (carrier) |
+-----------------+-----------------+-----------------+-----------------+
| ddr_clk | DDR interface | 333.33 MHz | 20MHz TCXO |
| | clock | | (carrier) |
+-----------------+-----------------+-----------------+-----------------+
| fs_clk | Sampling clock | 100.00 MHz | 400MHz LTC2174 |
| | | | (mezzanine) |
+-----------------+-----------------+-----------------+-----------------+
| serdes_clk | ADC data | 800.00 MHz | 400MHz LTC2174 |
| | de-serialiser | | (mezzanine) |
| | clock | | |
+-----------------+-----------------+-----------------+-----------------+
+------------------+-----------------+-----------------+-----------------+
| Name | Description | Frequency | Source |
+==================+=================+=================+=================+
| ``clk_ref_125m`` | Main system | 125.00 MHz | 125MHz VCXO |
| | clock | | (carrier) |
+------------------+-----------------+-----------------+-----------------+
| ``clk_sys_62m5`` | System clock | 62.50 MHz | 125MHz VCXO |
| | for spec-base | | (carrier) |
+------------------+-----------------+-----------------+-----------------+
| ``clk_ddr_333m`` | DDR interface | 333.33 MHz | 125MHz VCXO |
| | clock | | (carrier) |
+------------------+-----------------+-----------------+-----------------+
| ``fs_clk1`` | Sampling clock | 100.00 MHz | 400MHz LTC2174 |
| | | | (mezzanine #1) |
+------------------+-----------------+-----------------+-----------------+
| ``adc_dco1`` | ADC data | 800.00 MHz | 400MHz LTC2174 |
| | de-serialiser | | (mezzanine #1) |
| | clock | | |
+------------------+-----------------+-----------------+-----------------+
| ``fs_clk2`` | Sampling clock | 100.00 MHz | 400MHz LTC2174 |
| | | | (mezzanine #2) |
+------------------+-----------------+-----------------+-----------------+
| ``adc_dco2`` | ADC data | 800.00 MHz | 400MHz LTC2174 |
| | de-serialiser | | (mezzanine #2) |
| | clock | | |
+------------------+-----------------+-----------------+-----------------+
Common Cores
------------
......
hdl/cheby/Makefile
View file @ a3a2724b
......@@ -3,7 +3,6 @@
# SPDX-License-Identifier: CC0-1.0
SIM =../testbench/include
SW =../../software/include/hw
SOURCES = $(wildcard *.cheby)
TARGETS = $(SOURCES:.cheby=.vhd)
......@@ -13,8 +12,7 @@ all: $(TARGETS)
.PHONY: $(TARGETS)
$(TARGETS): %.vhd : %.cheby
@echo "\n\033[34m\033[1m-> Processing file $<\033[0m"
@cheby -i $< --gen-hdl=$@
@cheby -i $< \
--gen-consts=$(SIM)/$(@:.vhd=.v) \
--gen-c=$(SW)/$(@:.vhd=.h)
@echo -e "\n\033[34m\033[1m-> Processing file $<\033[0m"
cheby -i $< --gen-hdl=$@
cheby -i $< --gen-consts=$(SIM)/$(@:.vhd=.v)
cheby -i $< --gen-c=../../software/include/hw/$(<:.cheby=.h)
hdl/cheby/fmc_adc_100Ms_channel_regs.vhd
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hdl/cheby/fmc_adc_100Ms_csr.cheby
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......@@ -12,6 +12,7 @@ memory-map:
x-hdl:
busgroup: True
iogroup: fmc_adc_100ms_csr
pipeline: wr,rd
children:
- reg:
name: ctl
......
hdl/cheby/fmc_adc_100Ms_csr.vhd
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hdl/cheby/fmc_adc_aux_trigin.vhd
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hdl/cheby/fmc_adc_aux_trigout.cheby
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......@@ -8,7 +8,7 @@ memory-map:
description: FMC ADC aux trigger out registers
x-hdl:
busgroup: True
reg_prefix: False
reg-prefix: False
children:
- reg:
name: status
......
hdl/cheby/fmc_adc_aux_trigout.vhd
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hdl/cheby/fmc_adc_eic_regs.vhd
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......@@ -40,7 +40,6 @@ entity fmc_adc_eic_regs is
clk_i : in std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
-- Wires and registers
fmc_adc_eic_regs_i : in t_fmc_adc_eic_regs_master_in;
fmc_adc_eic_regs_o : out t_fmc_adc_eic_regs_master_out
......@@ -48,19 +47,28 @@ entity fmc_adc_eic_regs is
end fmc_adc_eic_regs;
architecture syn of fmc_adc_eic_regs is
signal rd_int : std_logic;
signal wr_int : std_logic;
signal adr_int : std_logic_vector(3 downto 2);
signal rd_req_int : std_logic;
signal wr_req_int : std_logic;
signal rd_ack_int : std_logic;
signal wr_ack_int : std_logic;
signal wb_en : std_logic;
signal ack_int : std_logic;
signal wb_rip : std_logic;
signal wb_wip : std_logic;
signal reg_rdat_int : std_logic_vector(31 downto 0);
signal rd_ack1_int : std_logic;
signal idr_wreq : std_logic;
signal ier_wreq : std_logic;
signal isr_wreq : std_logic;
signal rd_ack_d0 : std_logic;
signal rd_dat_d0 : std_logic_vector(31 downto 0);
signal wr_req_d0 : std_logic;
signal wr_adr_d0 : std_logic_vector(3 downto 2);
signal wr_dat_d0 : std_logic_vector(31 downto 0);
signal wr_sel_d0 : std_logic_vector(3 downto 0);
begin
-- WB decode signals
adr_int <= wb_i.adr(3 downto 2);
wb_en <= wb_i.cyc and wb_i.stb;
process (clk_i) begin
......@@ -72,7 +80,7 @@ begin
end if;
end if;
end process;
rd_int <= (wb_en and not wb_i.we) and not wb_rip;
rd_req_int <= (wb_en and not wb_i.we) and not wb_rip;
process (clk_i) begin
if rising_edge(clk_i) then
......@@ -83,7 +91,7 @@ begin
end if;
end if;
end process;
wr_int <= (wb_en and wb_i.we) and not wb_wip;
wr_req_int <= (wb_en and wb_i.we) and not wb_wip;
ack_int <= rd_ack_int or wr_ack_int;
wb_o.ack <= ack_int;
......@@ -91,105 +99,84 @@ begin
wb_o.rty <= '0';
wb_o.err <= '0';
-- Assign outputs
-- Process for write requests.
-- pipelining for wr-in+rd-out
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wr_ack_int <= '0';
fmc_adc_eic_regs_o.idr_wr <= '0';
fmc_adc_eic_regs_o.ier_wr <= '0';
fmc_adc_eic_regs_o.isr_wr <= '0';
rd_ack_int <= '0';
wr_req_d0 <= '0';
else
wr_ack_int <= '0';
fmc_adc_eic_regs_o.idr_wr <= '0';
fmc_adc_eic_regs_o.ier_wr <= '0';
fmc_adc_eic_regs_o.isr_wr <= '0';
case wb_i.adr(3 downto 2) is
when "00" =>
-- Register idr
fmc_adc_eic_regs_o.idr_wr <= wr_int;
if wr_int = '1' then
fmc_adc_eic_regs_o.idr <= wb_i.dat;
end if;
wr_ack_int <= wr_int;
when "01" =>
-- Register ier
fmc_adc_eic_regs_o.ier_wr <= wr_int;
if wr_int = '1' then
fmc_adc_eic_regs_o.ier <= wb_i.dat;
end if;
wr_ack_int <= wr_int;
when "10" =>
-- Register imr
when "11" =>
-- Register isr
fmc_adc_eic_regs_o.isr_wr <= wr_int;
if wr_int = '1' then
fmc_adc_eic_regs_o.isr <= wb_i.dat;
end if;
wr_ack_int <= wr_int;
when others =>
wr_ack_int <= wr_int;
end case;
rd_ack_int <= rd_ack_d0;
wb_o.dat <= rd_dat_d0;
wr_req_d0 <= wr_req_int;
wr_adr_d0 <= adr_int;
wr_dat_d0 <= wb_i.dat;
wr_sel_d0 <= wb_i.sel;
end if;
end if;
end process;
-- Process for registers read.
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack1_int <= '0';
else
reg_rdat_int <= (others => 'X');
case wb_i.adr(3 downto 2) is
when "00" =>
-- idr
rd_ack1_int <= rd_int;
when "01" =>
-- ier
rd_ack1_int <= rd_int;
when "10" =>
-- imr
reg_rdat_int <= fmc_adc_eic_regs_i.imr;
rd_ack1_int <= rd_int;
when "11" =>
-- isr
reg_rdat_int <= fmc_adc_eic_regs_i.isr;
rd_ack1_int <= rd_int;
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
end if;
end if;
-- Register idr
fmc_adc_eic_regs_o.idr <= wr_dat_d0;
fmc_adc_eic_regs_o.idr_wr <= idr_wreq;
-- Register ier
fmc_adc_eic_regs_o.ier <= wr_dat_d0;
fmc_adc_eic_regs_o.ier_wr <= ier_wreq;
-- Register imr
-- Register isr
fmc_adc_eic_regs_o.isr <= wr_dat_d0;
fmc_adc_eic_regs_o.isr_wr <= isr_wreq;
-- Process for write requests.
process (wr_adr_d0, wr_req_d0) begin
idr_wreq <= '0';
ier_wreq <= '0';
isr_wreq <= '0';
case wr_adr_d0(3 downto 2) is
when "00" =>
-- Reg idr
idr_wreq <= wr_req_d0;
wr_ack_int <= wr_req_d0;
when "01" =>
-- Reg ier
ier_wreq <= wr_req_d0;
wr_ack_int <= wr_req_d0;
when "10" =>
-- Reg imr
wr_ack_int <= wr_req_d0;
when "11" =>
-- Reg isr
isr_wreq <= wr_req_d0;
wr_ack_int <= wr_req_d0;
when others =>
wr_ack_int <= wr_req_d0;
end case;
end process;
-- Process for read requests.
process (wb_i.adr, reg_rdat_int, rd_ack1_int, rd_int) begin
process (adr_int, rd_req_int, fmc_adc_eic_regs_i.imr, fmc_adc_eic_regs_i.isr) begin
-- By default ack read requests
wb_o.dat <= (others => '0');
case wb_i.adr(3 downto 2) is
when "00" =>
-- idr
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "01" =>
-- ier
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "10" =>
-- imr
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "11" =>
-- isr
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
rd_dat_d0 <= (others => 'X');
case adr_int(3 downto 2) is
when "00" =>
-- Reg idr
rd_ack_d0 <= rd_req_int;
when "01" =>
-- Reg ier
rd_ack_d0 <= rd_req_int;
when "10" =>
-- Reg imr
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= fmc_adc_eic_regs_i.imr;
when "11" =>
-- Reg isr
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= fmc_adc_eic_regs_i.isr;
when others =>
rd_ack_int <= rd_int;
rd_ack_d0 <= rd_req_int;
end case;
end process;
end syn;
hdl/cheby/fmc_adc_mezzanine_mmap.cheby
View file @ a3a2724b
......@@ -9,6 +9,7 @@ memory-map:
size: 0x2000
x-hdl:
busgroup: True
pipeline: wr,rd
children:
- submap:
name: fmc_adc_100m_csr
......
hdl/cheby/fmc_adc_mezzanine_mmap.vhd
View file @ a3a2724b
This diff is collapsed.
hdl/cheby/spec_ref_fmc_adc_100Ms_mmap.vhd
View file @ a3a2724b
......@@ -28,8 +28,9 @@ entity spec_ref_fmc_adc_100m_mmap is
end spec_ref_fmc_adc_100m_mmap;
architecture syn of spec_ref_fmc_adc_100m_mmap is
signal rd_int : std_logic;
signal wr_int : std_logic;
signal adr_int : std_logic_vector(14 downto 2);
signal rd_req_int : std_logic;
signal wr_req_int : std_logic;
signal rd_ack_int : std_logic;
signal wr_ack_int : std_logic;
signal wb_en : std_logic;
......@@ -37,22 +38,29 @@ architecture syn of spec_ref_fmc_adc_100m_mmap is
signal wb_rip : std_logic;
signal wb_wip : std_logic;
signal metadata_re : std_logic;
signal metadata_we : std_logic;
signal metadata_wt : std_logic;
signal metadata_rt : std_logic;
signal metadata_tr : std_logic;
signal metadata_wack : std_logic;
signal metadata_rack : std_logic;
signal fmc_adc_mezzanine_re : std_logic;
signal fmc_adc_mezzanine_we : std_logic;
signal fmc_adc_mezzanine_wt : std_logic;
signal fmc_adc_mezzanine_rt : std_logic;
signal fmc_adc_mezzanine_tr : std_logic;
signal fmc_adc_mezzanine_wack : std_logic;
signal fmc_adc_mezzanine_rack : std_logic;
signal reg_rdat_int : std_logic_vector(31 downto 0);
signal rd_ack1_int : std_logic;
signal rd_ack_d0 : std_logic;
signal rd_dat_d0 : std_logic_vector(31 downto 0);
signal wr_req_d0 : std_logic;
signal wr_adr_d0 : std_logic_vector(14 downto 2);
signal wr_dat_d0 : std_logic_vector(31 downto 0);
signal wr_sel_d0 : std_logic_vector(3 downto 0);
begin
-- WB decode signals
adr_int <= wb_i.adr(14 downto 2);
wb_en <= wb_i.cyc and wb_i.stb;
process (clk_i) begin
......@@ -64,7 +72,7 @@ begin
end if;
end if;
end process;
rd_int <= (wb_en and not wb_i.we) and not wb_rip;
rd_req_int <= (wb_en and not wb_i.we) and not wb_rip;
process (clk_i) begin
if rising_edge(clk_i) then
......@@ -75,7 +83,7 @@ begin
end if;
end if;
end process;
wr_int <= (wb_en and wb_i.we) and not wb_wip;
wr_req_int <= (wb_en and wb_i.we) and not wb_wip;
ack_int <= rd_ack_int or wr_ack_int;
wb_o.ack <= ack_int;
......@@ -83,16 +91,33 @@ begin
wb_o.rty <= '0';
wb_o.err <= '0';
-- Assign outputs
-- pipelining for wr-in+rd-out
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack_int <= '0';
wr_req_d0 <= '0';
else
rd_ack_int <= rd_ack_d0;
wb_o.dat <= rd_dat_d0;
wr_req_d0 <= wr_req_int;
wr_adr_d0 <= adr_int;
wr_dat_d0 <= wb_i.dat;
wr_sel_d0 <= wb_i.sel;
end if;
end if;
end process;
-- Assignments for submap metadata
-- Interface metadata
metadata_tr <= metadata_wt or metadata_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
metadata_rt <= '0';
metadata_wt <= '0';
else
metadata_rt <= (metadata_rt or metadata_re) and not metadata_rack;
metadata_wt <= (metadata_wt or metadata_we) and not metadata_wack;
end if;
end if;
end process;
......@@ -100,19 +125,21 @@ begin
metadata_o.stb <= metadata_tr;
metadata_wack <= metadata_i.ack and metadata_wt;
metadata_rack <= metadata_i.ack and metadata_rt;
metadata_o.adr <= ((25 downto 0 => '0') & wb_i.adr(5 downto 2)) & (1 downto 0 => '0');
metadata_o.sel <= (others => '1');
metadata_o.adr <= ((25 downto 0 => '0') & adr_int(5 downto 2)) & (1 downto 0 => '0');
metadata_o.sel <= wr_sel_d0;
metadata_o.we <= metadata_wt;
metadata_o.dat <= wb_i.dat;
metadata_o.dat <= wr_dat_d0;
-- Assignments for submap fmc_adc_mezzanine
-- Interface fmc_adc_mezzanine
fmc_adc_mezzanine_tr <= fmc_adc_mezzanine_wt or fmc_adc_mezzanine_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
fmc_adc_mezzanine_rt <= '0';
fmc_adc_mezzanine_wt <= '0';
else
fmc_adc_mezzanine_rt <= (fmc_adc_mezzanine_rt or fmc_adc_mezzanine_re) and not fmc_adc_mezzanine_rack;
fmc_adc_mezzanine_wt <= (fmc_adc_mezzanine_wt or fmc_adc_mezzanine_we) and not fmc_adc_mezzanine_wack;
end if;
end if;
end process;
......@@ -120,75 +147,48 @@ begin
fmc_adc_mezzanine_o.stb <= fmc_adc_mezzanine_tr;
fmc_adc_mezzanine_wack <= fmc_adc_mezzanine_i.ack and fmc_adc_mezzanine_wt;
fmc_adc_mezzanine_rack <= fmc_adc_mezzanine_i.ack and fmc_adc_mezzanine_rt;
fmc_adc_mezzanine_o.adr <= ((18 downto 0 => '0') & wb_i.adr(12 downto 2)) & (1 downto 0 => '0');
fmc_adc_mezzanine_o.sel <= (others => '1');
fmc_adc_mezzanine_o.adr <= ((18 downto 0 => '0') & adr_int(12 downto 2)) & (1 downto 0 => '0');
fmc_adc_mezzanine_o.sel <= wr_sel_d0;
fmc_adc_mezzanine_o.we <= fmc_adc_mezzanine_wt;
fmc_adc_mezzanine_o.dat <= wb_i.dat;
fmc_adc_mezzanine_o.dat <= wr_dat_d0;
-- Process for write requests.
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wr_ack_int <= '0';
metadata_wt <= '0';
fmc_adc_mezzanine_wt <= '0';
else
wr_ack_int <= '0';
metadata_wt <= '0';
fmc_adc_mezzanine_wt <= '0';
case wb_i.adr(14 downto 13) is
when "01" =>
-- Submap metadata
metadata_wt <= (metadata_wt or wr_int) and not metadata_wack;
wr_ack_int <= metadata_wack;
when "10" =>
-- Submap fmc_adc_mezzanine
fmc_adc_mezzanine_wt <= (fmc_adc_mezzanine_wt or wr_int) and not fmc_adc_mezzanine_wack;
wr_ack_int <= fmc_adc_mezzanine_wack;
when others =>
wr_ack_int <= wr_int;
end case;
end if;
end if;
end process;
-- Process for registers read.
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack1_int <= '0';
else
reg_rdat_int <= (others => 'X');
case wb_i.adr(14 downto 13) is
when "01" =>
when "10" =>
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
end if;
end if;
process (wr_adr_d0, wr_req_d0, metadata_wack, fmc_adc_mezzanine_wack) begin
metadata_we <= '0';
fmc_adc_mezzanine_we <= '0';
case wr_adr_d0(14 downto 13) is
when "01" =>
-- Submap metadata
metadata_we <= wr_req_d0;
wr_ack_int <= metadata_wack;
when "10" =>
-- Submap fmc_adc_mezzanine
fmc_adc_mezzanine_we <= wr_req_d0;
wr_ack_int <= fmc_adc_mezzanine_wack;
when others =>
wr_ack_int <= wr_req_d0;
end case;
end process;
-- Process for read requests.
process (wb_i.adr, reg_rdat_int, rd_ack1_int, rd_int, rd_int, metadata_i.dat, metadata_rack, metadata_rt, rd_int, fmc_adc_mezzanine_i.dat, fmc_adc_mezzanine_rack, fmc_adc_mezzanine_rt) begin
process (adr_int, rd_req_int, metadata_i.dat, metadata_rack, fmc_adc_mezzanine_i.dat, fmc_adc_mezzanine_rack) begin
-- By default ack read requests
wb_o.dat <= (others => '0');
rd_dat_d0 <= (others => 'X');
metadata_re <= '0';
fmc_adc_mezzanine_re <= '0';
case wb_i.adr(14 downto 13) is
when "01" =>
case adr_int(14 downto 13) is
when "01" =>
-- Submap metadata
metadata_re <= rd_int;
wb_o.dat <= metadata_i.dat;
rd_ack_int <= metadata_rack;
when "10" =>
metadata_re <= rd_req_int;
rd_dat_d0 <= metadata_i.dat;
rd_ack_d0 <= metadata_rack;
when "10" =>
-- Submap fmc_adc_mezzanine
fmc_adc_mezzanine_re <= rd_int;
wb_o.dat <= fmc_adc_mezzanine_i.dat;
rd_ack_int <= fmc_adc_mezzanine_rack;
fmc_adc_mezzanine_re <= rd_req_int;
rd_dat_d0 <= fmc_adc_mezzanine_i.dat;
rd_ack_d0 <= fmc_adc_mezzanine_rack;
when others =>
rd_ack_int <= rd_int;
rd_ack_d0 <= rd_req_int;
end case;
end process;
end syn;
hdl/cheby/svec_ref_fmc_adc_100Ms_mmap.cheby
View file @ a3a2724b
......@@ -6,13 +6,14 @@ memory-map:
name: svec_ref_fmc_adc_100m_mmap
bus: wb-32-be
description: SPEC FMC-ADC-100M memory map
size: 0x8000
size: 0x10000
x-hdl:
busgroup: True
pipeline: wr,rd
children:
- submap:
name: metadata
address: 0x2000
address: 0x4000
size: 0x40
interface: wb-32-be
x-hdl:
......@@ -20,11 +21,11 @@ memory-map:
description: a ROM containing the application metadata
- submap:
name: fmc1_adc_mezzanine
address: 0x4000
address: 0x6000
description: FMC ADC Mezzanine slot 1
filename: fmc_adc_mezzanine_mmap.cheby
- submap:
name: fmc2_adc_mezzanine
address: 0x6000
address: 0x8000
description: FMC ADC Mezzanine slot 2
filename: fmc_adc_mezzanine_mmap.cheby
hdl/cheby/svec_ref_fmc_adc_100Ms_mmap.vhd
View file @ a3a2724b
This diff is collapsed.
hdl/cheby/timetag_core_regs.vhd
View file @ a3a2724b
This diff is collapsed.
ddr3-sp6-core @ b84d0335
Subproject commit 70f9de318f155764fdd4b7e1ae7f9c5b77131930
Subproject commit b84d0335dcda7b55352a3aabd38f65cf2169cac2
general-cores @ 67100ef6
Subproject commit 258eb8e00f99f795fe9b98840b01ac4a8b92ec94
Subproject commit 67100ef69d1d65cbb33f80475f860de996bdf619
gn4124-core @ 461b30fe
Subproject commit 06414d93d446a4e851f8aecd7512eec1b6d1fc4c
Subproject commit 461b30fe1f5e4e0c99f2265cdbf5843d31e31a4b
spec @ fd485c8b
Subproject commit 26b16bd3b1217d447034437eb83c1c56b75c8bd3
Subproject commit fd485c8b31b50a681f1a72504f6969384cfb1d4f
svec @ 577b31c8
Subproject commit 7d85d3b7bcb88186cd49a8646053f67d3aceab41
Subproject commit 577b31c8b1dc530aa145a8a49ab10dff7e9483b1
vme64x-core @ b25fbe11
Subproject commit f85c29dbca768bedd709b3f43448706c7d27b76d
Subproject commit b25fbe11de7efc6c9a22b5646de852f0d27f2d15
hdl/rtl/fmc_adc_100Ms_core.vhd
View file @ a3a2724b
......@@ -140,12 +140,7 @@ architecture rtl of fmc_adc_100Ms_core is
signal serdes_arst : std_logic;
-- Clocks and PLL
signal clk_fb : std_logic;
signal clk_fb_buf : std_logic;
signal locked_in : std_logic;
signal serdes_clk : std_logic;
signal fs_clk : std_logic;
signal fs_clk_buf : std_logic;
signal fs_freq : std_logic_vector(31 downto 0);
signal fs_freq_t : std_logic_vector(31 downto 0);
signal fs_freq_valid : std_logic;
......@@ -279,6 +274,8 @@ architecture rtl of fmc_adc_100Ms_core is
signal dpram_addrb_cnt : unsigned(c_DPRAM_DEPTH-1 downto 0);
signal dpram_dout : std_logic_vector(63 downto 0);
signal dpram_valid : std_logic;
signal dpram_valid_d1 : std_logic;
signal dpram_valid_d2 : std_logic;
signal dpram_valid_t : std_logic;
signal dpram0_dina : std_logic_vector(63 downto 0);
......@@ -302,10 +299,15 @@ architecture rtl of fmc_adc_100Ms_core is
signal wb_ddr_fifo_rd : std_logic;
signal wb_ddr_fifo_wr_en : std_logic;
signal wb_ddr_skidpad_stb_in : std_logic;
signal wb_ddr_skidpad_stb_out : std_logic;
signal wb_ddr_skidpad_stall : std_logic;
signal wb_ddr_skidpad_adr_in : std_logic_vector(28 downto 0);
signal wb_ddr_skidpad_adr_out : std_logic_vector(28 downto 0);
-- RAM address counter
signal ram_addr_cnt : unsigned(28 downto 0);
signal trig_addr : std_logic_vector(31 downto 0);
signal mem_ovr : std_logic;
-- LEDs
signal trig_led : std_logic;
......@@ -546,10 +548,10 @@ begin
if rising_edge(sys_clk_i) then
gpio_si570_oe_o <= csr_regout.ctl_fmc_clk_oe;
gpio_dac_clr_n_o <= csr_regout.ctl_offset_dac_clr_n;
gpio_ssr_ch1_o <= channel_regout(1).ctl_ssr;
gpio_ssr_ch2_o <= channel_regout(2).ctl_ssr;
gpio_ssr_ch3_o <= channel_regout(3).ctl_ssr;
gpio_ssr_ch4_o <= channel_regout(4).ctl_ssr;
gpio_ssr_ch1_o <= channel_regout(1).ctl_ssr;
gpio_ssr_ch2_o <= channel_regout(2).ctl_ssr;
gpio_ssr_ch3_o <= channel_regout(3).ctl_ssr;
gpio_ssr_ch4_o <= channel_regout(4).ctl_ssr;
end if;
end process p_delay_gpio_ssr;
......@@ -794,12 +796,14 @@ begin
ext_trig_delay_bsy <= '0';
else
if ext_trig = '1' and ext_trig_delay_bsy = '0' then
-- Start counter
ext_trig_delay_cnt <= unsigned(ext_trig_delay);
ext_trig_delay_bsy <= '1';
elsif ext_trig_delay_cnt /= 0 then
-- Count
ext_trig_delay_cnt <= ext_trig_delay_cnt - 1;
else
-- when counter reaches zero
-- When counter reaches zero
ext_trig_delay_bsy <= '0';
end if;
end if;
......@@ -989,7 +993,7 @@ begin
downsample_cnt <= to_unsigned(1, downsample_cnt'length);
downsample_en <= '0';
else
if downsample_cnt = to_unsigned(0, downsample_cnt'length) then
if downsample_cnt = 0 then
if downsample_factor /= X"00000000" then
downsample_cnt <= unsigned(downsample_factor) - 1;
end if;
......@@ -1401,23 +1405,37 @@ begin
dpram_addra_trig <= dpram_addra_cnt;
end if;
if post_trig_done = '1' then
dpram_addra_post_done <= dpram_addra_cnt;
-- reads 2 extra addresses -> trigger time-tag
dpram_addra_post_done <= dpram_addra_cnt + 2;
end if;
end if;
end if;
end process p_dpram_addra_cnt;
-- DPRAM inputs
dpram0_addra <= std_logic_vector(dpram_addra_cnt);
dpram1_addra <= std_logic_vector(dpram_addra_cnt);
dpram0_dina <= sync_fifo_dout(63 downto 0)
when acq_in_trig_tag = '0' else trig_tag_data;
dpram1_dina <= sync_fifo_dout(63 downto 0)
when acq_in_trig_tag = '0' else trig_tag_data;
dpram0_wea <= not single_shot and ((samples_wr_en and sync_fifo_valid) or acq_in_trig_tag)
when multishot_buffer_sel = '0' else '0';
dpram1_wea <= not single_shot and ((samples_wr_en and sync_fifo_valid) or acq_in_trig_tag)
when multishot_buffer_sel = '1' else '0';
p_dpram_inputs: process (sys_clk_i)
begin
if rising_edge(sys_clk_i) then
if sys_rst_n_i = '0' then
dpram0_wea <= '0';
dpram1_wea <= '1';
else
dpram0_addra <= std_logic_vector(dpram_addra_cnt);
dpram1_addra <= std_logic_vector(dpram_addra_cnt);
if acq_in_trig_tag = '0' then
dpram0_dina <= sync_fifo_dout(63 downto 0);
dpram1_dina <= sync_fifo_dout(63 downto 0);
else
dpram0_dina <= trig_tag_data;
dpram1_dina <= trig_tag_data;
end if;
dpram0_wea <= not single_shot and ((samples_wr_en and sync_fifo_valid) or acq_in_trig_tag)
and not multishot_buffer_sel;
dpram1_wea <= not single_shot and ((samples_wr_en and sync_fifo_valid) or acq_in_trig_tag)
and multishot_buffer_sel;
end if;
end if;
end process;
-- DPRAMs
cmp_multishot_dpram0 : generic_dpram
......@@ -1480,25 +1498,44 @@ begin
if rising_edge(sys_clk_i) then
if sys_rst_n_i = '0' or single_shot = '1' then
dpram_valid_t <= '0';
dpram_valid <= '0';
else
if trig_tag_done = '1' then
dpram_addrb_cnt <= dpram_addra_trig - unsigned(pre_trig_value(c_DPRAM_DEPTH-1 downto 0));
dpram_valid_t <= '1';
elsif (dpram_addrb_cnt = dpram_addra_post_done + 2) then -- reads 2 extra addresses -> trigger time-tag
elsif dpram_addrb_cnt = dpram_addra_post_done then
dpram_valid_t <= '0';
else
dpram_addrb_cnt <= dpram_addrb_cnt + 1;
end if;
dpram_valid <= dpram_valid_t;
end if;
end if;
end process p_dpram_addrb_cnt;
-- DPRAM output mux
dpram_dout <= dpram0_doutb when multishot_buffer_sel = '1' else dpram1_doutb;
dpram0_addrb <= std_logic_vector(dpram_addrb_cnt);
dpram1_addrb <= std_logic_vector(dpram_addrb_cnt);
p_dpram_valid : process (sys_clk_i)
begin
if rising_edge(sys_clk_i) then
if sys_rst_n_i = '0' or single_shot = '1' then
dpram_valid <= '0';
dpram_valid_d1 <= '0';
dpram_valid_d2 <= '0';
else
dpram0_addrb <= std_logic_vector(dpram_addrb_cnt);
dpram1_addrb <= std_logic_vector(dpram_addrb_cnt);
-- dpram_valid is delayed by 2 cycles from dpram_valid_t.
-- 1 for the dpram access, the second for the pipeline here.
dpram_valid_d1 <= dpram_valid_t;
dpram_valid_d2 <= dpram_valid_d1;
dpram_valid <= dpram_valid_d2;
if multishot_buffer_sel = '1' then
dpram_dout <= dpram0_doutb;
else
dpram_dout <= dpram1_doutb;
end if;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- Flow control FIFO for data to DDR
......@@ -1568,7 +1605,7 @@ begin
wb_ddr_fifo_wr <= wb_ddr_fifo_wr_en and not(wb_ddr_fifo_full);
wb_ddr_fifo_rd <= not(wb_ddr_fifo_empty or wb_ddr_master_i.stall);
wb_ddr_fifo_rd <= not(wb_ddr_fifo_empty or wb_ddr_skidpad_stall);
------------------------------------------------------------------------------
-- Wishbone master (to DDR)
......@@ -1583,24 +1620,45 @@ begin
else
if acq_start = '1' then
ram_addr_cnt <= (others => '0');
elsif wb_ddr_fifo_empty = '0' and wb_ddr_master_i.stall = '0' then
elsif wb_ddr_fifo_empty = '0' and wb_ddr_skidpad_stall = '0' then
ram_addr_cnt <= ram_addr_cnt + 1;
end if;
end if;
end if;
end process p_ram_addr_cnt;
with acq_fsm_state select
wb_ddr_master_o.cyc <=
dpram_valid or not wb_ddr_fifo_empty when "001",
'1' when others;
wb_ddr_master_o.stb <= not wb_ddr_fifo_empty;
wb_ddr_skidpad_stb_in <= not wb_ddr_fifo_empty;
-- Convert to 32-bit word addressing for Wishbone
wb_ddr_master_o.adr <= "00" & std_logic_vector(ram_addr_cnt) & "0";
wb_ddr_skidpad_adr_in <= std_logic_vector(ram_addr_cnt);
inst_skidpad: entity work.wb_skidpad2
generic map (
g_adrbits => ram_addr_cnt'length,
g_datbits => 64
)
port map (
clk_i => wb_ddr_clk_i,
rst_n_i => wb_ddr_rst_n_i,
stb_i => wb_ddr_skidpad_stb_in,
adr_i => wb_ddr_skidpad_adr_in,
dat_i => wb_ddr_fifo_dout(63 downto 0),
sel_i => (others => '1'),
we_i => '1',
stall_o => wb_ddr_skidpad_stall,
stb_o => wb_ddr_skidpad_stb_out,
adr_o => wb_ddr_skidpad_adr_out,
dat_o => wb_ddr_master_o.dat,
sel_o => open,
we_o => open,
stall_i => wb_ddr_master_i.stall
);
wb_ddr_master_o.we <= '1';
wb_ddr_master_o.sel <= X"FF";
wb_ddr_master_o.dat <= wb_ddr_fifo_dout(63 downto 0);
wb_ddr_master_o.cyc <= dpram_valid or wb_ddr_skidpad_stb_out when acq_fsm_state = "001" else '1';
wb_ddr_master_o.stb <= wb_ddr_skidpad_stb_out;
wb_ddr_master_o.adr <= "00" & wb_ddr_skidpad_adr_out & "0";
-- Store trigger DDR address (byte address)
p_trig_addr : process (wb_ddr_clk_i)
......@@ -1708,12 +1766,12 @@ begin
trigout_trig <= f_reduce_or (trigout_triggers);
-- Acquisition trigger delayed pulse
p_acq_end : process (sys_clk_i)
p_acq_trig : process (sys_clk_i)
begin
if rising_edge(sys_clk_i) then
acq_trig_d <= acq_trig;
end if;
end process p_acq_end;
end process p_acq_trig;
trigout_fifo_wr <= trigout_trig and not trigout_fifo_full and acq_trig_d;
......
hdl/rtl/fmc_adc_mezzanine.vhd
View file @ a3a2724b
......@@ -139,14 +139,11 @@ architecture rtl of fmc_adc_mezzanine is
-- Signals declaration
------------------------------------------------------------------------------
-- Wishbone buse(s) from master(s) to crossbar slave port(s)
signal cnx_master_out : t_wishbone_master_out;
signal cnx_master_in : t_wishbone_master_in;
-- Wishbone buse(s) from crossbar master port(s) to slave(s)
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
-- Wishbone buse(s) from master(s) to crossbar slave port(s)
signal wb_csr_out : t_wishbone_slave_in;
signal wb_csr_in : t_wishbone_slave_out;
......@@ -205,24 +202,12 @@ begin
master_i => wb_csr_in,
master_o => wb_csr_out);
-- Additional register to help timing
cmp_xwb_register : xwb_register
generic map (
g_WB_MODE => PIPELINED)
port map (
rst_n_i => sys_rst_n_i,
clk_i => sys_clk_i,
slave_i => wb_csr_out,
slave_o => wb_csr_in,
master_i => cnx_master_in,
master_o => cnx_master_out);
cmp_crossbar : entity work.fmc_adc_mezzanine_mmap
port map (
rst_n_i => sys_rst_n_i,
clk_i => sys_clk_i,
wb_i => cnx_master_out,
wb_o => cnx_master_in,
wb_i => wb_csr_out,
wb_o => wb_csr_in,
fmc_adc_100m_csr_i => cnx_slave_out(c_WB_SLAVE_FMC_ADC),
fmc_adc_100m_csr_o => cnx_slave_in(c_WB_SLAVE_FMC_ADC),
fmc_adc_eic_i => cnx_slave_out(c_WB_SLAVE_FMC_EIC),
......@@ -317,7 +302,7 @@ begin
-- ADC core control and status
------------------------------------------------------------------------------
cmp_fmc_adc_100Ms_core : fmc_adc_100Ms_core
cmp_fmc_adc_100Ms_core : entity work.fmc_adc_100Ms_core
generic map (
g_MULTISHOT_RAM_SIZE => g_MULTISHOT_RAM_SIZE,
g_SPARTAN6_USE_PLL => g_SPARTAN6_USE_PLL,
......
hdl/syn/svec_ref_design_wr/svec_ref_fmc_adc_100Ms_wr.ucf
View file @ a3a2724b
......@@ -203,14 +203,14 @@ NET "gen_fmc_mezzanine[1].*/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs1_clk;
TIMEGRP "adc0_sync_ffs" = "sync_ffs" EXCEPT "fs0_clk";
TIMEGRP "adc1_sync_ffs" = "sync_ffs" EXCEPT "fs1_clk";
TIMESPEC TS_adc0_sync_ffs = FROM fs0_clk TO "adc0_sync_ffs" TIG;
TIMESPEC TS_adc1_sync_ffs = FROM fs1_clk TO "adc1_sync_ffs" TIG;
#TIMESPEC TS_adc0_sync_ffs = FROM fs0_clk TO "adc0_sync_ffs" TIG;
#TIMESPEC TS_adc1_sync_ffs = FROM fs1_clk TO "adc1_sync_ffs" TIG;
TIMEGRP "adc0_sync_reg" = "sync_reg" EXCEPT "fs0_clk";
TIMEGRP "adc1_sync_reg" = "sync_reg" EXCEPT "fs1_clk";
TIMESPEC TS_adc0_sync_reg = FROM fs0_clk TO "adc0_sync_reg" 10ns DATAPATHONLY;
TIMESPEC TS_adc1_sync_reg = FROM fs1_clk TO "adc1_sync_reg" 10ns DATAPATHONLY;
TIMESPEC TS_adc0_sync_reg = FROM fs0_clk TO "adc0_sync_reg" 8ns DATAPATHONLY;
TIMESPEC TS_adc1_sync_reg = FROM fs1_clk TO "adc1_sync_reg" 8ns DATAPATHONLY;
# No sync words used in FMC-ADC
#TIMESPEC TS_adc0_sync_word = FROM sync_word TO fs0_clk 30ns DATAPATHONLY;
......
hdl/testbench/fmc_adc_mezzanine/main.sv
View file @ a3a2724b
......@@ -5,14 +5,15 @@
`timescale 1ns/1ps
`include "vhd_wishbone_master.svh"
`include "fmc_adc_mezzanine_mmap.v"
`include "fmc_adc_100Ms_csr.v"
`include "timetag_core_regs.v"
`include "fmc_adc_aux_trigin.v"
`include "fmc_adc_aux_trigout.v"
`define SDB_ADDR 'h0000
`define CSR_BASE 'h1000
`define TAG_BASE 'h1900
`define CSR_BASE `ADDR_FMC_ADC_MEZZANINE_MMAP_FMC_ADC_100M_CSR
`define TAG_BASE `ADDR_FMC_ADC_MEZZANINE_MMAP_TIMETAG_CORE
module main;
......
hdl/testbench/include/svec_ref_fmc_adc_100Ms_mmap.v
View file @ a3a2724b
......@@ -2,10 +2,10 @@
//
// SPDX-License-Identifier: CC0-1.0
`define SVEC_REF_FMC_ADC_100M_MMAP_SIZE 32768
`define ADDR_SVEC_REF_FMC_ADC_100M_MMAP_METADATA 'h2000
`define SVEC_REF_FMC_ADC_100M_MMAP_SIZE 65536
`define ADDR_SVEC_REF_FMC_ADC_100M_MMAP_METADATA 'h4000
`define SVEC_REF_FMC_ADC_100M_MMAP_METADATA_SIZE 64
`define ADDR_SVEC_REF_FMC_ADC_100M_MMAP_FMC1_ADC_MEZZANINE 'h4000
`define ADDR_SVEC_REF_FMC_ADC_100M_MMAP_FMC1_ADC_MEZZANINE 'h6000
`define SVEC_REF_FMC_ADC_100M_MMAP_FMC1_ADC_MEZZANINE_SIZE 8192
`define ADDR_SVEC_REF_FMC_ADC_100M_MMAP_FMC2_ADC_MEZZANINE 'h6000
`define ADDR_SVEC_REF_FMC_ADC_100M_MMAP_FMC2_ADC_MEZZANINE 'h8000
`define SVEC_REF_FMC_ADC_100M_MMAP_FMC2_ADC_MEZZANINE_SIZE 8192
hdl/testbench/svec_ref_design/main.sv
View file @ a3a2724b
......@@ -6,14 +6,24 @@
`include "vme64x_bfm.svh"
`include "svec_vme_buffers.svh"
`include "svec_ref_fmc_adc_100Ms_mmap.v"
`include "fmc_adc_mezzanine_mmap.v"
`include "fmc_adc_100Ms_csr.v"
`include "fmc_adc_100Ms_channel_regs.v"
`include "fmc_adc_eic_regs.v"
`include "timetag_core_regs.v"
`define VME_OFFSET 'h80000000
`define ADC_OFFSET 'h4000
`define ADC1_OFFSET `VME_OFFSET + `ADDR_SVEC_REF_FMC_ADC_100M_MMAP_FMC1_ADC_MEZZANINE
`define ADC2_OFFSET `VME_OFFSET + `ADDR_SVEC_REF_FMC_ADC_100M_MMAP_FMC2_ADC_MEZZANINE
`define CSR_BASE `VME_OFFSET + `ADC_OFFSET + 'h1000
`define OWC_BASE `VME_OFFSET + `ADC_OFFSET + 'h1700
`define TAG_BASE `VME_OFFSET + `ADC_OFFSET + 'h1900
`define CSR_BASE `ADC1_OFFSET + `ADDR_FMC_ADC_MEZZANINE_MMAP_FMC_ADC_100M_CSR
`define CH1_BASE `CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_FMC_ADC_CH1
`define CH2_BASE `CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_FMC_ADC_CH2
`define CH3_BASE `CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_FMC_ADC_CH3
`define CH4_BASE `CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_FMC_ADC_CH4
`define EIC_BASE `ADC1_OFFSET + `ADDR_FMC_ADC_MEZZANINE_MMAP_FMC_ADC_EIC
`define TAG_BASE `ADC1_OFFSET + `ADDR_FMC_ADC_MEZZANINE_MMAP_TIMETAG_CORE
module main;
......@@ -255,14 +265,13 @@ module main;
/* map func0 to 0x80000000, A32 */
acc.write('h7ff63, 'h80, A32|CR_CSR|D08Byte3);
acc.write('h7ff67, 0, CR_CSR|A32|D08Byte3);
acc.write('h7ff6b, 0, CR_CSR|A32|D08Byte3);
acc.write('h7ff6f, 36, CR_CSR|A32|D08Byte3);
acc.write('h7ff33, 1, CR_CSR|A32|D08Byte3);
acc.write('h7ff63, 'h80, CR_CSR|A32|D08Byte3);
acc.write('h7ff67, 0, CR_CSR|A32|D08Byte3);
acc.write('h7ff6b, 0, CR_CSR|A32|D08Byte3);
acc.write('h7ff6f, 36, CR_CSR|A32|D08Byte3);
acc.write('h7ff33, 1, CR_CSR|A32|D08Byte3);
acc.write('h7fffb, 'h10, CR_CSR|A32|D08Byte3); /* enable module (BIT_SET = 0x10) */
acc.set_default_modifiers(A32 | D32 | SINGLE);
endtask // init_vme64x_core
......@@ -309,22 +318,23 @@ module main;
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SHOTS, 'h00000001);
// FMC-ADC core channel configuration
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH1_CALIB, 'h00008000);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH2_CALIB, 'h00008000);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH3_CALIB, 'h00008000);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH4_CALIB, 'h00008000);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH1_SAT, 'h00007fff);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH2_SAT, 'h00007fff);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH3_SAT, 'h00007fff);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH4_SAT, 'h00007fff);
acc.write(`CH1_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_CALIB, 'h00008000);
acc.write(`CH2_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_CALIB, 'h00008000);
acc.write(`CH3_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_CALIB, 'h00008000);
acc.write(`CH4_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_CALIB, 'h00008000);
acc.write(`CH1_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_SAT, 'h00007fff);
acc.write(`CH2_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_SAT, 'h00007fff);
acc.write(`CH3_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_SAT, 'h00007fff);
acc.write(`CH4_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_SAT, 'h00007fff);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CTL, `FMC_ADC_100MS_CSR_CTL_CALIB_APPLY);
// FMC-ADC core trigger configuration
val = (16'h100 << `FMC_ADC_100MS_CSR_CH1_TRIG_THRES_HYST_OFFSET) |
(16'h300 << `FMC_ADC_100MS_CSR_CH1_TRIG_THRES_VAL_OFFSET);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH1_TRIG_THRES, val);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH2_TRIG_THRES, val);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH3_TRIG_THRES, val);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH4_TRIG_THRES, val);
val = (16'h100 << `FMC_ADC_100MS_CHANNEL_REGS_TRIG_THRES_HYST_OFFSET) |
(16'h300 << `FMC_ADC_100MS_CHANNEL_REGS_TRIG_THRES_VAL_OFFSET);
acc.write(`CH1_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_TRIG_THRES, val);
acc.write(`CH2_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_TRIG_THRES, val);
acc.write(`CH3_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_TRIG_THRES, val);
acc.write(`CH4_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_TRIG_THRES, val);
val = (1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_SW_OFFSET);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_EN, val);
......@@ -353,6 +363,33 @@ module main;
wait (acq_fsm_state == 1);
$display("<%t> END ACQ 1/4", $realtime);
#100ns;
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES, 'h00000004);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES, 'h00000008);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SHOTS, 'h00000001);
val = (1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_CH1_OFFSET);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_EN, val);
$display("<%t> START ACQ 1b/4", $realtime);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CTL, 'h00000001); // FSM sta
#1us;
wait (acq_fsm_state == 1);
$display("<%t> END ACQ 1b/4", $realtime);
// TODO: check results (they are only displayed)
acc.read(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_POS, val);
$display("trig pos: %x", val);
acc.write(`VME_OFFSET + 16'h58, val);
for(i = 0; i < 8*2 + 4; i+=1) begin
acc.read(`VME_OFFSET + 16'h2000, val);
$display("%d: %08x", i, val);
end
$stop;
#200ns;
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SHOTS, 'h00000003); // #nshots: 3x multi-shot acq
......
hdl/top/svec_ref_design/svec_ref_fmc_adc_100Ms.vhd
View file @ a3a2724b
......@@ -240,7 +240,7 @@ architecture arch of svec_ref_fmc_adc_100Ms is
constant c_WB_SLAVE_FMC1_ADC : integer := 2; -- FMC slot 2 ADC mezzanine
-- Convention metadata base address
constant c_METADATA_ADDR : t_wishbone_address := x"0000_2000";
constant c_METADATA_ADDR : t_wishbone_address := x"0000_4000";
------------------------------------------------------------------------------
-- Signals declaration
......@@ -309,6 +309,7 @@ begin -- architecture arch
inst_svec_base : entity work.svec_base_wr
generic map (
g_DECODE_AM => FALSE,
g_WITH_VIC => TRUE,
g_WITH_ONEWIRE => FALSE,
g_WITH_SPI => FALSE,
......@@ -475,7 +476,7 @@ begin -- architecture arch
generic map (
g_VENDOR_ID => x"0000_10DC",
g_DEVICE_ID => x"4144_4302", -- "ADC2"
g_VERSION => x"0500_0000",
g_VERSION => x"0500_0002",
g_CAPABILITIES => x"0000_0000",
g_COMMIT_ID => (others => '0'))
port map (
......@@ -503,9 +504,9 @@ begin -- architecture arch
gen_fmc_mezzanine : for I in 0 to g_NB_FMC_SLOTS - 1 generate
cmp_xwb_clock_bridge : xwb_clock_bridge
generic map (
g_SLAVE_PORT_WB_MODE => CLASSIC,
g_MASTER_PORT_WB_MODE => PIPELINED)
generic map (
g_SLAVE_PORT_WB_MODE => CLASSIC,
g_MASTER_PORT_WB_MODE => PIPELINED)
port map (
slave_clk_i => clk_sys_62m5,
slave_rst_n_i => rst_sys_62m5_n,
......@@ -641,7 +642,7 @@ begin -- architecture arch
d_i => fmc_acq_trig(I),
q_o => fmc_acq_trig_sync(I));
p_fmc_acq_led: process (fmc_acq_cfg_ok_sync) is
p_fmc_acq_led: process (fmc_acq_cfg_ok_sync, fmc_acq_trig_sync) is
begin
if fmc_acq_cfg_ok_sync(I) = '0' then
fmc_acq_led(I) <= c_LED_RED;
......
software/include/hw/fmc_adc_100Ms_channel_regs.h 0 → 100644
View file @ a3a2724b
#ifndef __CHEBY__FMC_ADC_100MS_CHANNEL_REGS__H__
#define __CHEBY__FMC_ADC_100MS_CHANNEL_REGS__H__
#define FMC_ADC_100MS_CHANNEL_REGS_SIZE 24 /* 0x18 */
/* Channel control register */
#define FMC_ADC_100MS_CHANNEL_REGS_CTL 0x0UL
#define FMC_ADC_100MS_CHANNEL_REGS_CTL_SSR_MASK 0x7fUL
#define FMC_ADC_100MS_CHANNEL_REGS_CTL_SSR_SHIFT 0
/* Channel status register */
#define FMC_ADC_100MS_CHANNEL_REGS_STA 0x4UL
#define FMC_ADC_100MS_CHANNEL_REGS_STA_VAL_MASK 0xffffUL
#define FMC_ADC_100MS_CHANNEL_REGS_STA_VAL_SHIFT 0
/* Channel calibration register */
#define FMC_ADC_100MS_CHANNEL_REGS_CALIB 0x8UL
#define FMC_ADC_100MS_CHANNEL_REGS_CALIB_GAIN_MASK 0xffffUL
#define FMC_ADC_100MS_CHANNEL_REGS_CALIB_GAIN_SHIFT 0
#define FMC_ADC_100MS_CHANNEL_REGS_CALIB_OFFSET_MASK 0xffff0000UL
#define FMC_ADC_100MS_CHANNEL_REGS_CALIB_OFFSET_SHIFT 16
/* Channel saturation register */
#define FMC_ADC_100MS_CHANNEL_REGS_SAT 0xcUL
#define FMC_ADC_100MS_CHANNEL_REGS_SAT_VAL_MASK 0x7fffUL
#define FMC_ADC_100MS_CHANNEL_REGS_SAT_VAL_SHIFT 0
/* Channel trigger threshold configuration register */
#define FMC_ADC_100MS_CHANNEL_REGS_TRIG_THRES 0x10UL
#define FMC_ADC_100MS_CHANNEL_REGS_TRIG_THRES_VAL_MASK 0xffffUL
#define FMC_ADC_100MS_CHANNEL_REGS_TRIG_THRES_VAL_SHIFT 0
#define FMC_ADC_100MS_CHANNEL_REGS_TRIG_THRES_HYST_MASK 0xffff0000UL
#define FMC_ADC_100MS_CHANNEL_REGS_TRIG_THRES_HYST_SHIFT 16
/* Channel trigger delay */
#define FMC_ADC_100MS_CHANNEL_REGS_TRIG_DLY 0x14UL
struct fmc_adc_100ms_channel_regs {
/* [0x0]: REG (rw) Channel control register */
uint32_t ctl;
/* [0x4]: REG (ro) Channel status register */
uint32_t sta;
/* [0x8]: REG (rw) Channel calibration register */
uint32_t calib;
/* [0xc]: REG (rw) Channel saturation register */
uint32_t sat;
/* [0x10]: REG (rw) Channel trigger threshold configuration register */
uint32_t trig_thres;
/* [0x14]: REG (rw) Channel trigger delay */
uint32_t trig_dly;
};
#endif /* __CHEBY__FMC_ADC_100MS_CHANNEL_REGS__H__ */
software/include/hw/fmc_adc_100Ms_csr.h 0 → 100644
View file @ a3a2724b
#ifndef __CHEBY__FMC_ADC_100MS_CSR__H__
#define __CHEBY__FMC_ADC_100MS_CSR__H__
#include "fmc_adc_100ms_channel_regs.h"
#define FMC_ADC_100MS_CSR_SIZE 512 /* 0x200 */
/* Control register */
#define FMC_ADC_100MS_CSR_CTL 0x0UL
#define FMC_ADC_100MS_CSR_CTL_FSM_CMD_MASK 0x3UL
#define FMC_ADC_100MS_CSR_CTL_FSM_CMD_SHIFT 0
#define FMC_ADC_100MS_CSR_CTL_FMC_CLK_OE 0x4UL
#define FMC_ADC_100MS_CSR_CTL_OFFSET_DAC_CLR_N 0x8UL
#define FMC_ADC_100MS_CSR_CTL_MAN_BITSLIP 0x10UL
#define FMC_ADC_100MS_CSR_CTL_TRIG_LED 0x40UL
#define FMC_ADC_100MS_CSR_CTL_ACQ_LED 0x80UL
#define FMC_ADC_100MS_CSR_CTL_CLEAR_TRIG_STAT 0x100UL
#define FMC_ADC_100MS_CSR_CTL_CALIB_APPLY 0x8000UL
/* Status register */
#define FMC_ADC_100MS_CSR_STA 0x4UL
#define FMC_ADC_100MS_CSR_STA_FSM_MASK 0x7UL
#define FMC_ADC_100MS_CSR_STA_FSM_SHIFT 0
#define FMC_ADC_100MS_CSR_STA_SERDES_PLL 0x8UL
#define FMC_ADC_100MS_CSR_STA_SERDES_SYNCED 0x10UL
#define FMC_ADC_100MS_CSR_STA_ACQ_CFG 0x20UL
#define FMC_ADC_100MS_CSR_STA_FMC_NR_MASK 0xc0UL
#define FMC_ADC_100MS_CSR_STA_FMC_NR_SHIFT 6
#define FMC_ADC_100MS_CSR_STA_CALIB_BUSY 0x8000UL
/* Trigger status */
#define FMC_ADC_100MS_CSR_TRIG_STAT 0x8UL
#define FMC_ADC_100MS_CSR_TRIG_STAT_EXT 0x1UL
#define FMC_ADC_100MS_CSR_TRIG_STAT_SW 0x2UL
#define FMC_ADC_100MS_CSR_TRIG_STAT_TIME 0x10UL
#define FMC_ADC_100MS_CSR_TRIG_STAT_CH1 0x100UL
#define FMC_ADC_100MS_CSR_TRIG_STAT_CH2 0x200UL
#define FMC_ADC_100MS_CSR_TRIG_STAT_CH3 0x400UL
#define FMC_ADC_100MS_CSR_TRIG_STAT_CH4 0x800UL
/* Trigger enable */
#define FMC_ADC_100MS_CSR_TRIG_EN 0xcUL
#define FMC_ADC_100MS_CSR_TRIG_EN_EXT 0x1UL
#define FMC_ADC_100MS_CSR_TRIG_EN_SW 0x2UL
#define FMC_ADC_100MS_CSR_TRIG_EN_TIME 0x10UL
#define FMC_ADC_100MS_CSR_TRIG_EN_AUX_TIME 0x20UL
#define FMC_ADC_100MS_CSR_TRIG_EN_CH1 0x100UL
#define FMC_ADC_100MS_CSR_TRIG_EN_CH2 0x200UL
#define FMC_ADC_100MS_CSR_TRIG_EN_CH3 0x400UL
#define FMC_ADC_100MS_CSR_TRIG_EN_CH4 0x800UL
/* Trigger polarity */
#define FMC_ADC_100MS_CSR_TRIG_POL 0x10UL
#define FMC_ADC_100MS_CSR_TRIG_POL_EXT 0x1UL
#define FMC_ADC_100MS_CSR_TRIG_POL_CH1 0x100UL
#define FMC_ADC_100MS_CSR_TRIG_POL_CH2 0x200UL
#define FMC_ADC_100MS_CSR_TRIG_POL_CH3 0x400UL
#define FMC_ADC_100MS_CSR_TRIG_POL_CH4 0x800UL
/* External trigger delay */
#define FMC_ADC_100MS_CSR_EXT_TRIG_DLY 0x14UL
/* Software trigger */
#define FMC_ADC_100MS_CSR_SW_TRIG 0x18UL
/* Number of shots */
#define FMC_ADC_100MS_CSR_SHOTS 0x1cUL
#define FMC_ADC_100MS_CSR_SHOTS_NBR_MASK 0xffffUL
#define FMC_ADC_100MS_CSR_SHOTS_NBR_SHIFT 0
#define FMC_ADC_100MS_CSR_SHOTS_REMAIN_MASK 0xffff0000UL
#define FMC_ADC_100MS_CSR_SHOTS_REMAIN_SHIFT 16
/* Multi-shot sample depth register */
#define FMC_ADC_100MS_CSR_MULTI_DEPTH 0x20UL
/* Trigger address register */
#define FMC_ADC_100MS_CSR_TRIG_POS 0x24UL
/* Sampling clock frequency */
#define FMC_ADC_100MS_CSR_FS_FREQ 0x28UL
/* Downsampling ratio */
#define FMC_ADC_100MS_CSR_DOWNSAMPLE 0x2cUL
/* Pre-trigger samples */
#define FMC_ADC_100MS_CSR_PRE_SAMPLES 0x30UL
/* Post-trigger samples */
#define FMC_ADC_100MS_CSR_POST_SAMPLES 0x34UL
/* Samples counter */
#define FMC_ADC_100MS_CSR_SAMPLES_CNT 0x38UL
/* Channel 1 registers */
#define FMC_ADC_100MS_CSR_FMC_ADC_CH1 0x80UL
#define FMC_ADC_100MS_CSR_FMC_ADC_CH1_SIZE 32 /* 0x20 */
/* Channel 2 registers */
#define FMC_ADC_100MS_CSR_FMC_ADC_CH2 0xc0UL
#define FMC_ADC_100MS_CSR_FMC_ADC_CH2_SIZE 32 /* 0x20 */
/* Channel 3 registers */
#define FMC_ADC_100MS_CSR_FMC_ADC_CH3 0x100UL
#define FMC_ADC_100MS_CSR_FMC_ADC_CH3_SIZE 32 /* 0x20 */
/* Channel 4 registers */
#define FMC_ADC_100MS_CSR_FMC_ADC_CH4 0x140UL
#define FMC_ADC_100MS_CSR_FMC_ADC_CH4_SIZE 32 /* 0x20 */
struct fmc_adc_100ms_csr {
/* [0x0]: REG (rw) Control register */
uint32_t ctl;
/* [0x4]: REG (ro) Status register */
uint32_t sta;
/* [0x8]: REG (ro) Trigger status */
uint32_t trig_stat;
/* [0xc]: REG (rw) Trigger enable */
uint32_t trig_en;
/* [0x10]: REG (rw) Trigger polarity */
uint32_t trig_pol;
/* [0x14]: REG (rw) External trigger delay */
uint32_t ext_trig_dly;
/* [0x18]: REG (wo) Software trigger */
uint32_t sw_trig;
/* [0x1c]: REG (rw) Number of shots */
uint32_t shots;
/* [0x20]: REG (ro) Multi-shot sample depth register */
uint32_t multi_depth;
/* [0x24]: REG (ro) Trigger address register */
uint32_t trig_pos;
/* [0x28]: REG (ro) Sampling clock frequency */
uint32_t fs_freq;
/* [0x2c]: REG (rw) Downsampling ratio */
uint32_t downsample;
/* [0x30]: REG (rw) Pre-trigger samples */
uint32_t pre_samples;
/* [0x34]: REG (rw) Post-trigger samples */
uint32_t post_samples;
/* [0x38]: REG (ro) Samples counter */
uint32_t samples_cnt;
/* padding to: 32 words */
uint32_t __padding_0[17];
/* [0x80]: SUBMAP Channel 1 registers */
struct fmc_adc_100ms_channel_regs fmc_adc_ch1;
/* padding to: 48 words */
uint32_t __padding_1[10];
/* [0xc0]: SUBMAP Channel 2 registers */
struct fmc_adc_100ms_channel_regs fmc_adc_ch2;
/* padding to: 64 words */
uint32_t __padding_2[10];
/* [0x100]: SUBMAP Channel 3 registers */
struct fmc_adc_100ms_channel_regs fmc_adc_ch3;
/* padding to: 80 words */
uint32_t __padding_3[10];
/* [0x140]: SUBMAP Channel 4 registers */
struct fmc_adc_100ms_channel_regs fmc_adc_ch4;
/* padding to: 80 words */
uint32_t __padding_4[42];
};
#endif /* __CHEBY__FMC_ADC_100MS_CSR__H__ */
software/include/hw/fmc_adc_aux_trigin.h 0 → 100644
View file @ a3a2724b
#ifndef __CHEBY__AUX_TRIGIN__H__
#define __CHEBY__AUX_TRIGIN__H__
#define AUX_TRIGIN_SIZE 20 /* 0x14 */
/* Core version */
#define AUX_TRIGIN_VERSION 0x0UL
#define AUX_TRIGIN_VERSION_PRESET 0xadc10001UL
/* Control register */
#define AUX_TRIGIN_CTRL 0x4UL
#define AUX_TRIGIN_CTRL_ENABLE 0x1UL
/* Time (seconds) to trigger */
#define AUX_TRIGIN_SECONDS 0x8UL
/* Time (cycles) to trigger */
#define AUX_TRIGIN_CYCLES 0x10UL
struct aux_trigin {
/* [0x0]: REG (ro) Core version */
uint32_t version;
/* [0x4]: REG (rw) Control register */
uint32_t ctrl;
/* [0x8]: REG (rw) Time (seconds) to trigger */
uint64_t seconds;
/* [0x10]: REG (rw) Time (cycles) to trigger */
uint32_t cycles;
};
#endif /* __CHEBY__AUX_TRIGIN__H__ */
software/include/hw/fmc_adc_aux_trigout.h 0 → 100644
View file @ a3a2724b
#ifndef __CHEBY__AUX_TRIGOUT__H__
#define __CHEBY__AUX_TRIGOUT__H__
#define AUX_TRIGOUT_SIZE 20 /* 0x14 */
/* Status register */
#define AUX_TRIGOUT_STATUS 0x0UL
#define AUX_TRIGOUT_WR_ENABLE 0x1UL
#define AUX_TRIGOUT_WR_LINK 0x2UL
#define AUX_TRIGOUT_WR_VALID 0x4UL
#define AUX_TRIGOUT_TS_PRESENT 0x100UL
/* Time (seconds) of the last event */
#define AUX_TRIGOUT_TS_MASK_SEC 0x8UL
#define AUX_TRIGOUT_TS_SEC_MASK 0xffffffffffULL
#define AUX_TRIGOUT_TS_SEC_SHIFT 0
#define AUX_TRIGOUT_CH1_MASK 0x1000000000000ULL
#define AUX_TRIGOUT_CH2_MASK 0x2000000000000ULL
#define AUX_TRIGOUT_CH3_MASK 0x4000000000000ULL
#define AUX_TRIGOUT_CH4_MASK 0x8000000000000ULL
#define AUX_TRIGOUT_EXT_MASK 0x100000000000000ULL
/* Cycles part of timestamp fifo. */
#define AUX_TRIGOUT_TS_CYCLES 0x10UL
#define AUX_TRIGOUT_CYCLES_MASK 0xfffffffUL
#define AUX_TRIGOUT_CYCLES_SHIFT 0
struct aux_trigout {
/* [0x0]: REG (ro) Status register */
uint32_t status;
/* padding to: 2 words */
uint32_t __padding_0[1];
/* [0x8]: REG (ro) Time (seconds) of the last event */
uint64_t ts_mask_sec;
/* [0x10]: REG (ro) Cycles part of timestamp fifo. */
uint32_t ts_cycles;
};
#endif /* __CHEBY__AUX_TRIGOUT__H__ */
software/include/hw/fmc_adc_eic_regs.h 0 → 100644
View file @ a3a2724b
#ifndef __CHEBY__FMC_ADC_EIC_REGS__H__
#define __CHEBY__FMC_ADC_EIC_REGS__H__
#define FMC_ADC_EIC_REGS_SIZE 16 /* 0x10 */
/* Interrupt Disable Register */
#define FMC_ADC_EIC_REGS_IDR 0x0UL
/* Interrupt Enable Register */
#define FMC_ADC_EIC_REGS_IER 0x4UL
/* Interrupt Mask Register */
#define FMC_ADC_EIC_REGS_IMR 0x8UL
/* Interrupt Status Register */
#define FMC_ADC_EIC_REGS_ISR 0xcUL
struct fmc_adc_eic_regs {
/* [0x0]: REG (wo) Interrupt Disable Register */
uint32_t idr;
/* [0x4]: REG (wo) Interrupt Enable Register */
uint32_t ier;
/* [0x8]: REG (ro) Interrupt Mask Register */
uint32_t imr;
/* [0xc]: REG (rw) Interrupt Status Register */
uint32_t isr;
};
#endif /* __CHEBY__FMC_ADC_EIC_REGS__H__ */
software/include/hw/fmc_adc_mezzanine_mmap.h 0 → 100644
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software/include/hw/spec_ref_fmc_adc_100Ms_mmap.h 0 → 100644
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software/include/hw/svec_ref_fmc_adc_100Ms_mmap.h 0 → 100644
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software/include/hw/timetag_core_regs.h 0 → 100644
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software/kernel/fa-core.c
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software/kernel/fa-debug.c
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software/kernel/fa-dma.c
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