Commit 9e0a7d28 authored by Dimitris Lampridis's avatar Dimitris Lampridis

hdl: make use of sdb_desc_gen.tcl from general-cores to generate the SDB meta info records

parent 73dfb60c
...@@ -3,4 +3,4 @@ files = [ ...@@ -3,4 +3,4 @@ files = [
"carrier_csr.vhd", "carrier_csr.vhd",
"carrier_csr_wbgen2_pkg.vhd", "carrier_csr_wbgen2_pkg.vhd",
"dma_eic.vhd", "dma_eic.vhd",
"sdb_meta_pkg.vhd"] ]
-------------------------------------------------------------------------------
-- Title : FMC ADC 100Ms/s SPEC SDB meta-information
-- Project : FMC ADC 100M 14B 4CHA gateware
-- URL : http://www.ohwr.org/projects/fmc-adc-100m14b4cha-gw
-------------------------------------------------------------------------------
-- File : sdb_meta_pkg.vhd
-- Author(s) : Matthieu Cattin <matthieu.cattin@cern.ch>
-- : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2013-03-11
-- Last update: 2016-04-20
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: SDB meta-information for the FMC ADC 100Ms/s design for SPEC.
-------------------------------------------------------------------------------
-- Copyright (c) 2013-2016 CERN (BE-CO-HT)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2016-04-20 4.1 Dimitrios Lampridis
-- 2014-04-25 4.0 Matthieu Cattin
-- 2014-01-16 3.0 Matthieu Cattin
-- 2013-07-29 2.0 Matthieu Cattin
-- 2013-03-28 1.1 Matthieu Cattin
-- 2013-03-11 1.0 Matthieu Cattin
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
package sdb_meta_pkg is
------------------------------------------------------------------------------
-- Meta-information sdb records
------------------------------------------------------------------------------
-- Top module repository url
constant c_repo_url_sdb : t_sdb_repo_url := (
-- url (string, limited to 63 char, full URL does not fit unfortunately)
repo_url => "fmc-projects/fmc-adc-100m14b4cha/fmc-adc-100m14b4cha-gw.git ");
-- Synthesis informations
constant c_synthesis_sdb : t_sdb_synthesis := (
-- Top module name (string, 16 char)
syn_module_name => "spec_top_fmc_adc",
-- Commit ID (hex string, 128-bit = 32 char)
-- git log -1 --format="%H" | cut -c1-32
syn_commit_id => "a37d85ff17a01a013e48e028abfb18c0",
-- Synthesis tool name (string, 8 char)
syn_tool_name => "ISE ",
-- Synthesis tool version (bcd encoded, 32-bit)
syn_tool_version => x"00000147",
-- Synthesis date (bcd encoded, 32-bit, yyyymmdd)
syn_date => x"20160420",
-- Synthesised by (string, 15 char)
syn_username => "dlamprid ");
-- Integration record
constant c_integration_sdb : t_sdb_integration := (
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"47c786a2", -- echo "spec_fmc-adc-100m14b4cha" | md5sum | cut -c1-8
version => x"00040001", -- bcd encoded, [31:16] = major, [15:0] = minor
date => x"20160420", -- yyyymmdd
name => "spec_fmcadc100m14b "));
end sdb_meta_pkg;
package body sdb_meta_pkg is
end sdb_meta_pkg;
...@@ -39,7 +39,7 @@ use work.ddr3_ctrl_pkg.all; ...@@ -39,7 +39,7 @@ use work.ddr3_ctrl_pkg.all;
use work.gencores_pkg.all; use work.gencores_pkg.all;
use work.wishbone_pkg.all; use work.wishbone_pkg.all;
use work.fmc_adc_mezzanine_pkg.all; use work.fmc_adc_mezzanine_pkg.all;
use work.sdb_meta_pkg.all; use work.synthesis_descriptor.all;
use work.timetag_core_pkg.all; use work.timetag_core_pkg.all;
use work.carrier_csr_wbgen2_pkg.all; use work.carrier_csr_wbgen2_pkg.all;
use work.wrcore_pkg.all; use work.wrcore_pkg.all;
...@@ -262,9 +262,9 @@ architecture rtl of spec_top_fmc_adc_100Ms is ...@@ -262,9 +262,9 @@ architecture rtl of spec_top_fmc_adc_100Ms is
constant c_WB_SLAVE_WR_CORE : integer := 5; -- WR PTP core constant c_WB_SLAVE_WR_CORE : integer := 5; -- WR PTP core
-- SDB meta info -- SDB meta info
constant c_SDB_REPO_URL : integer := c_NUM_WB_MASTERS; constant c_SDB_GIT_REPO_URL : integer := c_NUM_WB_MASTERS;
constant c_SDB_SYNTHESIS : integer := c_NUM_WB_MASTERS + 1; constant c_SDB_SYNTHESIS : integer := c_NUM_WB_MASTERS + 1;
constant c_SDB_INTEGRATE : integer := c_NUM_WB_MASTERS + 2; constant c_SDB_INTEGRATE : integer := c_NUM_WB_MASTERS + 2;
-- Devices sdb description -- Devices sdb description
constant c_wb_dma_ctrl_sdb : t_sdb_device := ( constant c_wb_dma_ctrl_sdb : t_sdb_device := (
...@@ -323,6 +323,15 @@ architecture rtl of spec_top_fmc_adc_100Ms is ...@@ -323,6 +323,15 @@ architecture rtl of spec_top_fmc_adc_100Ms is
-- sdb header address -- sdb header address
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000"; constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
-- sdb integration record
constant c_integration_sdb : t_sdb_integration := (
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"47c786a2", -- echo "spec_fmc-adc-100m14b4cha" | md5sum | cut -c1-8
version => x"00050000", -- bcd encoded, [31:16] = major, [15:0] = minor
date => x"20181025", -- yyyymmdd
name => "spec_fmcadc100m14b "));
-- Wishbone crossbar layout -- Wishbone crossbar layout
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_MASTERS + 2 downto 0) := constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_MASTERS + 2 downto 0) :=
( (
...@@ -332,8 +341,8 @@ architecture rtl of spec_top_fmc_adc_100Ms is ...@@ -332,8 +341,8 @@ architecture rtl of spec_top_fmc_adc_100Ms is
c_WB_SLAVE_DMA_EIC => f_sdb_embed_device(c_wb_dma_eic_sdb, x"00001400"), c_WB_SLAVE_DMA_EIC => f_sdb_embed_device(c_wb_dma_eic_sdb, x"00001400"),
c_WB_SLAVE_FMC_ADC => f_sdb_embed_bridge(c_fmc0_bridge_sdb, x"00002000"), c_WB_SLAVE_FMC_ADC => f_sdb_embed_bridge(c_fmc0_bridge_sdb, x"00002000"),
c_WB_SLAVE_WR_CORE => f_sdb_embed_bridge(c_wr_core_bridge_sdb, x"00040000"), c_WB_SLAVE_WR_CORE => f_sdb_embed_bridge(c_wr_core_bridge_sdb, x"00040000"),
c_SDB_REPO_URL => f_sdb_embed_repo_url(c_repo_url_sdb), c_SDB_GIT_REPO_URL => f_sdb_embed_repo_url(c_sdb_repo_url),
c_SDB_SYNTHESIS => f_sdb_embed_synthesis(c_synthesis_sdb), c_SDB_SYNTHESIS => f_sdb_embed_synthesis(c_sdb_synthesis_info),
c_SDB_INTEGRATE => f_sdb_embed_integration(c_integration_sdb) c_SDB_INTEGRATE => f_sdb_embed_integration(c_integration_sdb)
); );
......
board = "spec"
target = "xilinx" target = "xilinx"
action = "synthesis" action = "synthesis"
...@@ -29,3 +30,7 @@ modules = { ...@@ -29,3 +30,7 @@ modules = {
fetchto="../../ip_cores" fetchto="../../ip_cores"
ctrls = ["bank3_64b_32b" ] ctrls = ["bank3_64b_32b" ]
syn_post_project_cmd = "$(TCL_INTERPRETER) " + \
fetchto + "/general-cores/tools/sdb_desc_gen.tcl " + \
syn_tool + " $(PROJECT_FILE)"
...@@ -2,4 +2,4 @@ files = [ ...@@ -2,4 +2,4 @@ files = [
"svec_top_fmc_adc_100Ms.vhd", "svec_top_fmc_adc_100Ms.vhd",
"carrier_csr.vhd", "carrier_csr.vhd",
"carrier_csr_wbgen2_pkg.vhd", "carrier_csr_wbgen2_pkg.vhd",
"sdb_meta_pkg.vhd"] ]
-------------------------------------------------------------------------------
-- Title : FMC ADC 100Ms/s SVEC SDB meta-information
-- Project : FMC ADC 100M 14B 4CHA gateware
-- URL : http://www.ohwr.org/projects/fmc-adc-100m14b4cha-gw
-------------------------------------------------------------------------------
-- File : sdb_meta_pkg.vhd
-- Author(s) : Matthieu Cattin <matthieu.cattin@cern.ch>
-- : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2013-07-05
-- Last update: 2016-04-20
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: SDB meta-information for the FMC ADC 100Ms/s design for SVEC.
-------------------------------------------------------------------------------
-- Copyright (c) 2013-2016 CERN (BE-CO-HT)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2016-04-20 4.1 Dimitrios Lampridis
-- 2014-04-25 4.0 Matthieu Cattin
-- 2014-01-16 3.0 Matthieu Cattin
-- 2013-07-29 1.0 Matthieu Cattin
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
package sdb_meta_pkg is
------------------------------------------------------------------------------
-- Meta-information sdb records
------------------------------------------------------------------------------
-- Top module repository url
constant c_repo_url_sdb : t_sdb_repo_url := (
-- url (string, limited to 63 char, full URL does not fit unfortunately)
repo_url => "fmc-projects/fmc-adc-100m14b4cha/fmc-adc-100m14b4cha-gw.git ");
-- Synthesis informations
constant c_synthesis_sdb : t_sdb_synthesis := (
-- Top module name (string, 16 char)
syn_module_name => "svec_top_fmc_adc",
-- Commit ID (hex string, 128-bit = 32 char)
-- git log -1 --format="%H" | cut -c1-32
syn_commit_id => "a37d85ff17a01a013e48e028abfb18c0",
-- Synthesis tool name (string, 8 char)
syn_tool_name => "ISE ",
-- Synthesis tool version (bcd encoded, 32-bit)
syn_tool_version => x"00000147",
-- Synthesis date (bcd encoded, 32-bit, yyyymmdd)
syn_date => x"20160420",
-- Synthesised by (string, 15 char)
syn_username => "dlamprid ");
-- Integration record
constant c_integration_sdb : t_sdb_integration := (
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"5c01a632", -- echo "svec_fmc-adc-100m14b4cha" | md5sum | cut -c1-8
version => x"00040001", -- bcd encoded, [31:16] = major, [15:0] = minor
date => x"20160420", -- yyyymmdd
name => "svec_fmcadc100m14b "));
end sdb_meta_pkg;
package body sdb_meta_pkg is
end sdb_meta_pkg;
...@@ -39,7 +39,7 @@ use work.ddr3_ctrl_pkg.all; ...@@ -39,7 +39,7 @@ use work.ddr3_ctrl_pkg.all;
use work.gencores_pkg.all; use work.gencores_pkg.all;
use work.wishbone_pkg.all; use work.wishbone_pkg.all;
use work.fmc_adc_mezzanine_pkg.all; use work.fmc_adc_mezzanine_pkg.all;
use work.sdb_meta_pkg.all; use work.synthesis_descriptor.all;
use work.vme64x_pkg.all; use work.vme64x_pkg.all;
use work.timetag_core_pkg.all; use work.timetag_core_pkg.all;
use work.carrier_csr_wbgen2_pkg.all; use work.carrier_csr_wbgen2_pkg.all;
...@@ -369,9 +369,9 @@ architecture rtl of svec_top_fmc_adc_100Ms is ...@@ -369,9 +369,9 @@ architecture rtl of svec_top_fmc_adc_100Ms is
constant c_WB_SLAVE_WR_CORE : integer := 8; -- WR PTP core constant c_WB_SLAVE_WR_CORE : integer := 8; -- WR PTP core
-- SDB meta info -- SDB meta info
constant c_SDB_REPO_URL : integer := c_NUM_WB_MASTERS; constant c_SDB_GIT_REPO_URL : integer := c_NUM_WB_MASTERS;
constant c_SDB_SYNTHESIS : integer := c_NUM_WB_MASTERS + 1; constant c_SDB_SYNTHESIS : integer := c_NUM_WB_MASTERS + 1;
constant c_SDB_INTEGRATE : integer := c_NUM_WB_MASTERS + 2; constant c_SDB_INTEGRATE : integer := c_NUM_WB_MASTERS + 2;
-- Devices sdb description -- Devices sdb description
constant c_wb_svec_csr_sdb : t_sdb_device := ( constant c_wb_svec_csr_sdb : t_sdb_device := (
...@@ -431,6 +431,15 @@ architecture rtl of svec_top_fmc_adc_100Ms is ...@@ -431,6 +431,15 @@ architecture rtl of svec_top_fmc_adc_100Ms is
-- sdb header address -- sdb header address
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000"; constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
-- sdb integration record
constant c_integration_sdb : t_sdb_integration := (
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"5c01a632", -- echo "svec_fmc-adc-100m14b4cha" | md5sum | cut -c1-8
version => x"00050000", -- bcd encoded, [31:16] = major, [15:0] = minor
date => x"20181025", -- yyyymmdd
name => "svec_fmcadc100m14b "));
-- Wishbone crossbar layout -- Wishbone crossbar layout
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_MASTERS + 2 downto 0) := constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_MASTERS + 2 downto 0) :=
( (
...@@ -443,8 +452,8 @@ architecture rtl of svec_top_fmc_adc_100Ms is ...@@ -443,8 +452,8 @@ architecture rtl of svec_top_fmc_adc_100Ms is
c_WB_SLAVE_FMC1_DDR_ADR => f_sdb_embed_device(c_wb_ddr_adr_sdb, x"00008000"), c_WB_SLAVE_FMC1_DDR_ADR => f_sdb_embed_device(c_wb_ddr_adr_sdb, x"00008000"),
c_WB_SLAVE_FMC1_DDR_DAT => f_sdb_embed_device(c_wb_ddr_dat_sdb, x"00009000"), c_WB_SLAVE_FMC1_DDR_DAT => f_sdb_embed_device(c_wb_ddr_dat_sdb, x"00009000"),
c_WB_SLAVE_WR_CORE => f_sdb_embed_bridge(c_wr_core_bridge_sdb, x"00040000"), c_WB_SLAVE_WR_CORE => f_sdb_embed_bridge(c_wr_core_bridge_sdb, x"00040000"),
c_SDB_REPO_URL => f_sdb_embed_repo_url(c_repo_url_sdb), c_SDB_GIT_REPO_URL => f_sdb_embed_repo_url(c_sdb_repo_url),
c_SDB_SYNTHESIS => f_sdb_embed_synthesis(c_synthesis_sdb), c_SDB_SYNTHESIS => f_sdb_embed_synthesis(c_sdb_synthesis_info),
c_SDB_INTEGRATE => f_sdb_embed_integration(c_integration_sdb) c_SDB_INTEGRATE => f_sdb_embed_integration(c_integration_sdb)
); );
......
board = "svec"
target = "xilinx" target = "xilinx"
action = "synthesis" action = "synthesis"
...@@ -29,3 +30,7 @@ modules = { ...@@ -29,3 +30,7 @@ modules = {
fetchto="../../ip_cores" fetchto="../../ip_cores"
ctrls = ["bank4_64b_32b", "bank5_64b_32b"] ctrls = ["bank4_64b_32b", "bank5_64b_32b"]
syn_post_project_cmd = "$(TCL_INTERPRETER) " + \
fetchto + "/general-cores/tools/sdb_desc_gen.tcl " + \
syn_tool + " $(PROJECT_FILE)"
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