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FMC ADC 100M 14b 4cha
Commit 9d054640 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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Introduce adjustment parameter to timetag core and re-align all triggers. 

Re-aligment was performed using the WR-enabled FMC-ADC and the PPS signal coming out from the WR
switch as signal input on channel #1, as well as external trigger input. The PPS signal was
delivered to the FMC-ADC by means of a 40ns coaxial cable.

External, internal and time triggering well all tested and calibrated using the above setup.
parent a4e869b1
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Showing with 64 additions and 22 deletions
hdl/rtl/fmc_adc_100Ms_core.vhd
View file @ 9d054640
......@@ -197,7 +197,7 @@ architecture rtl of fmc_adc_100Ms_core is
signal ext_trig_delay_cnt : unsigned(31 downto 0);
signal ext_trig_delay_bsy : std_logic;
signal ext_trig_en : std_logic;
signal ext_trig_fixed_delay : std_logic_vector(7 downto 0);
signal ext_trig_fixed_delay : std_logic_vector(9 downto 0);
signal ext_trig_p, ext_trig_n : std_logic;
signal ext_trig_pol : std_logic;
signal int_trig : std_logic_vector(1 to 4);
......@@ -212,13 +212,13 @@ architecture rtl of fmc_adc_100Ms_core is
signal int_trig_thres_hyst : t_fmc_adc_vec16_array(1 to 4);
signal sw_trig : std_logic;
signal sw_trig_en : std_logic;
signal sw_trig_fixed_delay : std_logic_vector(4 downto 0);
signal sw_trig_fixed_delay : std_logic_vector(11 downto 0);
signal time_trig : std_logic;
signal time_trig_en : std_logic;
signal time_trig_fixed_delay : std_logic_vector(4 downto 0);
signal time_trig_fixed_delay : std_logic_vector(11 downto 0);
signal alt_time_trig : std_logic;
signal alt_time_trig_en : std_logic;
signal alt_time_trig_fixed_delay : std_logic_vector(4 downto 0);
signal alt_time_trig_fixed_delay : std_logic_vector(11 downto 0);
signal trig : std_logic;
signal trig_align : std_logic_vector(8 downto 0);
signal trig_storage : std_logic_vector(31 downto 0);
......@@ -752,9 +752,9 @@ begin
-- We solve this by introducing individual delays to the other triggers. In doing
-- so, we always add more to account for the 3 clock cycles data delays mentioned
-- before. Thus:
-- * EXT triggers are delayed by 8 (5+3) cycles
-- * TIME triggers are delayed by 5 (2+3) cycles TODO: confirm
-- * SOFT triggers are delayed by 5 (2+3) cycles TODO: confirm
-- * EXT triggers are delayed by 10 (7+3) cycles
-- * TIME triggers are delayed by 12 (9+3) cycles
-- * SOFT triggers are delayed by 12 (9+3) cycles
p_data_shift : process (fs_clk)
begin
......
hdl/rtl/fmc_adc_mezzanine.vhd
View file @ 9d054640
......@@ -498,6 +498,7 @@ begin
-- Mezzanine 1-wire master
-- DS18B20 (thermometer + unique ID)
------------------------------------------------------------------------------
cmp_fmc_onewire : xwb_onewire_master
generic map(
g_interface_mode => CLASSIC,
......@@ -580,6 +581,10 @@ begin
-- Time-tagging core
------------------------------------------------------------------------------
cmp_timetag_core : entity work.timetag_core
generic map (
-- Systematic delay introduced to the time tag by the FMC-ADC-100M core.
-- Measured experimentally.
g_TAG_ADJUST => 24)
port map(
clk_i => sys_clk_i,
rst_n_i => sys_rst_n_i,
......
hdl/rtl/timetag_core/timetag_core.vhd
View file @ 9d054640
......@@ -8,13 +8,12 @@
-- : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-11-18
-- Last update: 2019-05-02
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Implements a UTC seconds counter and a 125MHz system clock
-- ticks counter to time-tag trigger, acquisition start and stop events.
-------------------------------------------------------------------------------
-- Copyright (c) 2011-2016 CERN (BE-CO-HT)
-- Copyright (c) 2011-2019 CERN (BE-CO-HT)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------
......@@ -40,6 +39,11 @@ use work.timetag_core_pkg.all;
use work.timetag_core_wbgen2_pkg.all;
entity timetag_core is
generic (
-- Value to be subtracted from trigger tag coarse counter.
-- This is useful if you know that the system introduces
-- some systematic delay wrt the actual trigger time
g_TAG_ADJUST : natural := 0);
port (
-- Clock, reset
clk_i : in std_logic; -- Must be 125MHz
......@@ -208,7 +212,7 @@ begin
elsif regout.coarse_load_o = '1' then
time_counter.coarse <= regout.coarse_o;
local_pps <= '0';
elsif time_counter.coarse = std_logic_vector(to_unsigned(124999999, 28)) then
elsif time_counter.coarse = std_logic_vector(c_TAG_COARSE_MAX - 1) then
time_counter.coarse <= (others => '0');
local_pps <= '1';
else
......@@ -277,17 +281,49 @@ begin
------------------------------------------------------------------------------
-- Last trigger event time-tag
------------------------------------------------------------------------------
p_trig_tag : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
trig_tag.seconds <= (others => '0');
trig_tag.coarse <= (others => '0');
elsif trigger_p_i = '1' then
trig_tag <= current_time;
gen_trig_tag_no_adjust : if g_TAG_ADJUST = 0 generate
p_trig_tag : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
trig_tag.seconds <= (others => '0');
trig_tag.coarse <= (others => '0');
elsif trigger_p_i = '1' then
trig_tag <= current_time;
end if;
end if;
end if;
end process p_trig_tag;
end process p_trig_tag;
end generate gen_trig_tag_no_adjust;
gen_trig_tag : if g_TAG_ADJUST /= 0 generate
p_trig_tag : process (clk_i)
variable v_seconds_now : unsigned(39 downto 0) := (others => '0');
variable v_coarse_now : unsigned(27 downto 0) := (others => '0');
variable v_seconds_next : unsigned(39 downto 0) := (others => '0');
variable v_coarse_next : unsigned(27 downto 0) := (others => '0');
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
trig_tag.seconds <= (others => '0');
trig_tag.coarse <= (others => '0');
elsif trigger_p_i = '1' then
v_seconds_now := unsigned(current_time.seconds);
v_coarse_now := unsigned(current_time.coarse);
if g_TAG_ADJUST > v_coarse_now then
v_seconds_next := v_seconds_now - 1;
v_coarse_next := c_TAG_COARSE_MAX - (g_TAG_ADJUST - v_coarse_now);
else
v_seconds_next := v_seconds_now;
v_coarse_next := v_coarse_now - g_TAG_ADJUST;
end if;
trig_tag.seconds <= std_logic_vector(v_seconds_next);
trig_tag.coarse <= std_logic_vector(v_coarse_next);
end if;
end if;
end process p_trig_tag;
end generate gen_trig_tag;
trig_tag_o <= trig_tag;
......
hdl/rtl/timetag_core/timetag_core_pkg.vhd
View file @ 9d054640
......@@ -8,12 +8,11 @@
-- : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2013-07-05
-- Last update: 2018-11-06
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Package for timetag core
-------------------------------------------------------------------------------
-- Copyright (c) 2013-2016 CERN (BE-CO-HT)
-- Copyright (c) 2013-2019 CERN (BE-CO-HT)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------
......@@ -46,6 +45,8 @@ package timetag_core_pkg is
coarse : std_logic_vector(27 downto 0);
end record t_timetag;
constant c_TAG_COARSE_MAX : unsigned := to_unsigned(125000000, 28);
end timetag_core_pkg;
package body timetag_core_pkg is
......
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