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FMC ADC 100M 14b 4cha
Commit 96548f64 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: cleanup clocks (closes issue #1240), switch to 125MHz clock source (closes issue #1316)

parent 0fdfbaad
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hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
View file @ 96548f64
......@@ -8,7 +8,7 @@
-- : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-02-24
-- Last update: 2016-04-19
-- Last update: 2016-05-13
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Top entity of FMC ADC 100Ms/s design for Simple PCIe FMC
......@@ -61,8 +61,11 @@ entity spec_top_fmc_adc_100Ms is
g_CALIB_SOFT_IP : string := "TRUE");
port
(
-- Local oscillator
clk20_vcxo_i : in std_logic; -- 20MHz VCXO clock
-- Local oscillators
-- clk20_vcxo_i : in std_logic; -- 20MHz VCXO clock
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_n_i : in std_logic;
-- DAC interface (20MHz and 25MHz VCXO)
pll25dac_sync_n_o : out std_logic; -- 25MHz VCXO
......@@ -70,13 +73,13 @@ entity spec_top_fmc_adc_100Ms is
plldac_din_o : out std_logic;
plldac_sclk_o : out std_logic;
-- Carrier font panel LEDs
-- Carrier front panel LEDs
led_red_o : out std_logic;
led_green_o : out std_logic;
-- Auxiliary pins
aux_leds_o : out std_logic_vector(3 downto 0);
aux_buttons_i : in std_logic_vector(1 downto 0);
aux_leds_o : out std_logic_vector(3 downto 0);
--aux_buttons_i : in std_logic_vector(1 downto 0);
-- PCB version
pcb_ver_i : in std_logic_vector(3 downto 0);
......@@ -85,29 +88,27 @@ entity spec_top_fmc_adc_100Ms is
carrier_one_wire_b : inout std_logic;
-- GN4124 interface
L_CLKp : in std_logic; -- Local bus clock (frequency set in GN4124 config registers)
L_CLKn : in std_logic; -- Local bus clock (frequency set in GN4124 config registers)
L_RST_N : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
P2L_RDY : out std_logic; -- Rx Buffer Full Flag
P2L_CLKn : in std_logic; -- Receiver Source Synchronous Clock-
P2L_CLKp : in std_logic; -- Receiver Source Synchronous Clock+
L_RST_N : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
P2L_RDY : out std_logic; -- Rx Buffer Full Flag
P2L_CLKn : in std_logic; -- Receiver Source Synchronous Clock-
P2L_CLKp : in std_logic; -- Receiver Source Synchronous Clock+
P2L_DATA : in std_logic_vector(15 downto 0); -- Parallel receive data
P2L_DFRAME : in std_logic; -- Receive Frame
P2L_VALID : in std_logic; -- Receive Data Valid
P_WR_REQ : in std_logic_vector(1 downto 0); -- PCIe Write Request
P2L_DFRAME : in std_logic; -- Receive Frame
P2L_VALID : in std_logic; -- Receive Data Valid
--P_WR_REQ : in std_logic_vector(1 downto 0); -- PCIe Write Request
P_WR_RDY : out std_logic_vector(1 downto 0); -- PCIe Write Ready
RX_ERROR : out std_logic; -- Receive Error
RX_ERROR : out std_logic; -- Receive Error
L2P_DATA : out std_logic_vector(15 downto 0); -- Parallel transmit data
L2P_DFRAME : out std_logic; -- Transmit Data Frame
L2P_VALID : out std_logic; -- Transmit Data Valid
L2P_CLKn : out std_logic; -- Transmitter Source Synchronous Clock-
L2P_CLKp : out std_logic; -- Transmitter Source Synchronous Clock+
L2P_EDB : out std_logic; -- Packet termination and discard
L2P_RDY : in std_logic; -- Tx Buffer Full Flag
L2P_DFRAME : out std_logic; -- Transmit Data Frame
L2P_VALID : out std_logic; -- Transmit Data Valid
L2P_CLKn : out std_logic; -- Transmitter Source Synchronous Clock-
L2P_CLKp : out std_logic; -- Transmitter Source Synchronous Clock+
L2P_EDB : out std_logic; -- Packet termination and discard
L2P_RDY : in std_logic; -- Tx Buffer Full Flag
L_WR_RDY : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
P_RD_D_RDY : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
TX_ERROR : in std_logic; -- Transmit Error
VC_RDY : in std_logic_vector(1 downto 0); -- Channel ready
TX_ERROR : in std_logic; -- Transmit Error
--VC_RDY : in std_logic_vector(1 downto 0); -- Channel ready
GPIO : inout std_logic_vector(1 downto 0); -- GPIO[0] -> GN4124 GPIO8
-- GPIO[1] -> GN4124 GPIO9
-- DDR3 interface
......@@ -342,18 +343,14 @@ architecture rtl of spec_top_fmc_adc_100Ms is
-- System clock
signal sys_clk_in : std_logic;
signal sys_clk_125_buf : std_logic;
signal sys_clk_250_buf : std_logic;
signal sys_clk_125 : std_logic;
signal sys_clk_250 : std_logic;
signal sys_clk_fb : std_logic;
signal sys_clk_pll_locked : std_logic;
signal clk_125m_pllref : std_logic;
-- DDR3 clock
signal ddr_clk : std_logic;
signal ddr_clk_buf : std_logic;
-- LCLK from GN4124
signal l_clk : std_logic;
signal ddr_clk : std_logic;
signal ddr_clk_buf : std_logic;
-- Reset
signal powerup_reset_cnt : unsigned(7 downto 0) := "00000000";
......@@ -454,13 +451,6 @@ architecture rtl of spec_top_fmc_adc_100Ms is
begin
------------------------------------------------------------------------------
-- Clocks distribution from 20MHz TCXO
-- 125.000 MHz system clock
-- 250.000 MHz fast system clock
-- 333.333 MHz DDR3 clock
------------------------------------------------------------------------------
-- AD5662BRMZ-1 DAC output powers up to 0V. The output remains valid until a
-- write sequence arrives to the DAC.
-- To avoid spurious writes, the DAC interface outputs are fixed to safe values.
......@@ -469,10 +459,23 @@ begin
plldac_din_o <= '0';
plldac_sclk_o <= '0';
cmp_sys_clk_buf : IBUFG
-- diff clock buffer from 125MHz clock reference
cmp_pll_clk_buf : IBUFGDS
generic map (
DIFF_TERM => TRUE,
IBUF_LOW_PWR => TRUE)
port map (
I => clk20_vcxo_i,
O => sys_clk_in);
O => clk_125m_pllref,
I => clk_125m_pllref_p_i,
IB => clk_125m_pllref_n_i);
-- just an alias to keep it backwards compatible
sys_clk_in <= clk_125m_pllref;
--cmp_sys_clk_buf : IBUFG
-- port map (
-- I => clk20_vcxo_i,
-- O => sys_clk_in);
cmp_sys_clk_pll : PLL_BASE
generic map (
......@@ -480,23 +483,23 @@ begin
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50,
CLKFBOUT_MULT => 8, -- 1GHz
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 8,
CLKOUT0_DIVIDE => 8, -- 125MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 4,
CLKOUT1_DIVIDE => 16, -- 62.5MHz
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 3,
CLKOUT2_DIVIDE => 3, -- 333MHz
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 50.0,
CLKIN_PERIOD => 8.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => sys_clk_fb,
CLKOUT0 => sys_clk_125_buf,
CLKOUT1 => sys_clk_250_buf,
CLKOUT1 => open,
CLKOUT2 => ddr_clk_buf,
CLKOUT3 => open,
CLKOUT4 => open,
......@@ -511,30 +514,11 @@ begin
O => sys_clk_125,
I => sys_clk_125_buf);
cmp_clk_250_buf : BUFG
port map (
O => sys_clk_250,
I => sys_clk_250_buf);
cmp_ddr_clk_buf : BUFG
port map (
O => ddr_clk,
I => ddr_clk_buf);
------------------------------------------------------------------------------
-- Local clock from gennum LCLK
------------------------------------------------------------------------------
cmp_l_clk_buf : IBUFDS
generic map (
DIFF_TERM => FALSE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => l_clk, -- Buffer output
I => L_CLKp, -- Diff_p buffer input (connect directly to top-level port)
IB => L_CLKn -- Diff_n buffer input (connect directly to top-level port)
);
------------------------------------------------------------------------------
-- System reset
------------------------------------------------------------------------------
......@@ -575,7 +559,7 @@ begin
p2l_valid_i => P2L_VALID,
-- P2L Control
p2l_rdy_o => P2L_RDY,
p_wr_req_i => P_WR_REQ,
p_wr_req_i => "00",
p_wr_rdy_o => P_WR_RDY,
rx_error_o => RX_ERROR,
-- L2P Direction Source Sync DDR related signals
......@@ -590,7 +574,7 @@ begin
l_wr_rdy_i => L_WR_RDY,
p_rd_d_rdy_i => P_RD_D_RDY,
tx_error_i => TX_ERROR,
vc_rdy_i => VC_RDY,
vc_rdy_i => "00",
-- Interrupt interface
dma_irq_o => dma_irq,
irq_p_i => irq_to_gn4124,
......
hdl/spec/spec_top_fmc_adc_100Ms.ucf
View file @ 96548f64
......@@ -5,13 +5,13 @@
#----------------------------------------
# Clock inputs
#----------------------------------------
NET "clk20_vcxo_i" LOC = H12; # CLK25_VCXO
NET "clk20_vcxo_i" IOSTANDARD = "LVCMOS25";
#NET "clk20_vcxo_i" LOC = H12; # CLK25_VCXO
#NET "clk20_vcxo_i" IOSTANDARD = "LVCMOS25";
#NET "clk_125m_pllref_n_i" LOC = F10;
#NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
#NET "clk_125m_pllref_p_i" LOC = G9;
#NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_n_i" LOC = F10;
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_p_i" LOC = G9;
NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
#----------------------------------------
# SFP slot
......@@ -79,10 +79,6 @@ NET "L_WR_RDY[0]" LOC = R20;
NET "L_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY[1]" LOC = T22;
NET "L_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "L_CLKN" LOC = N19;
NET "L_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "L_CLKP" LOC = P20;
NET "L_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_CLKN" LOC = M19;
NET "P2L_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_CLKP" LOC = M20;
......@@ -101,18 +97,18 @@ NET "P_WR_RDY[0]" LOC = L15;
NET "P_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY[1]" LOC = K16;
NET "P_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ[0]" LOC = M22;
NET "P_WR_REQ[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ[1]" LOC = M21;
NET "P_WR_REQ[1]" IOSTANDARD = "SSTL18_I";
#NET "P_WR_REQ[0]" LOC = M22;
#NET "P_WR_REQ[0]" IOSTANDARD = "SSTL18_I";
#NET "P_WR_REQ[1]" LOC = M21;
#NET "P_WR_REQ[1]" IOSTANDARD = "SSTL18_I";
NET "RX_ERROR" LOC = J17;
NET "RX_ERROR" IOSTANDARD = "SSTL18_I";
NET "TX_ERROR" LOC = M17;
NET "TX_ERROR" IOSTANDARD = "SSTL18_I";
NET "VC_RDY[0]" LOC = B21;
NET "VC_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "VC_RDY[1]" LOC = B22;
NET "VC_RDY[1]" IOSTANDARD = "SSTL18_I";
#NET "VC_RDY[0]" LOC = B21;
#NET "VC_RDY[0]" IOSTANDARD = "SSTL18_I";
#NET "VC_RDY[1]" LOC = B22;
#NET "VC_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[0]" LOC = P16;
NET "L2P_DATA[0]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[1]" LOC = P21;
......@@ -526,10 +522,10 @@ NET "DDR3_DQ[15]" IOSTANDARD = "SSTL15_II";
#----------------------------------------
# Buttons and LEDs
#----------------------------------------
NET "AUX_BUTTONS_I[0]" LOC = C22;
NET "AUX_BUTTONS_I[0]" IOSTANDARD = "LVCMOS18";
NET "AUX_BUTTONS_I[1]" LOC = D21;
NET "AUX_BUTTONS_I[1]" IOSTANDARD = "LVCMOS18";
#NET "AUX_BUTTONS_I[0]" LOC = C22;
#NET "AUX_BUTTONS_I[0]" IOSTANDARD = "LVCMOS18";
#NET "AUX_BUTTONS_I[1]" LOC = D21;
#NET "AUX_BUTTONS_I[1]" IOSTANDARD = "LVCMOS18";
NET "AUX_LEDS_O[0]" LOC = G19;
NET "AUX_LEDS_O[0]" IOSTANDARD = "LVCMOS18";
NET "AUX_LEDS_O[1]" LOC = F20;
......@@ -567,72 +563,18 @@ NET "DDR3_UDQS_N" IN_TERM = NONE;
# Timing constraints
#===============================================================================
# GN4124
#NET "L_CLKp" TNM_NET = "l_clkp_grp";
#TIMESPEC TS_l_clkp = PERIOD "l_clkp_grp" 5 ns HIGH 50%;
NET "P2L_CLKp" TNM_NET = "p2l_clkp_grp";
TIMESPEC TS_p2l_clkp = PERIOD "p2l_clkp_grp" 5 ns HIGH 50%;
NET "P2L_CLKn" TNM_NET = "p2l_clkn_grp";
TIMESPEC TS_p2l_clkn = PERIOD "p2l_clkn_grp" 5 ns HIGH 50%;
NET "L2P_CLKN" TNM = "gn4124_data_bus_out";
NET "L2P_CLKP" TNM = "gn4124_data_bus_out";
NET "L2P_VALID" TNM = "gn4124_data_bus_out";
NET "L2P_DFRAME" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[0]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[1]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[2]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[3]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[4]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[5]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[6]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[7]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[8]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[9]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[10]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[11]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[12]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[13]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[14]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[15]" TNM = "gn4124_data_bus_out";
#TIMEGRP "gn4124_data_bus_out" OFFSET = OUT AFTER "cmp_gn4124_core/io_clk" REFERENCE_PIN "L2P_CLKP";
NET "P2L_CLKN" TNM = "gn4124_data_bus_in";
NET "P2L_CLKP" TNM = "gn4124_data_bus_in";
NET "P2L_DFRAME" TNM = "gn4124_data_bus_in";
NET "P2L_VALID" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[0]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[1]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[2]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[3]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[4]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[5]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[6]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[7]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[8]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[9]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[10]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[11]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[12]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[13]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[14]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[15]" TNM = "gn4124_data_bus_in";
#TIMEGRP "gn4124_data_bus_in" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE "cmp_gn4124_core/io_clk" RISING;
#TIMEGRP "gn4124_data_bus_in" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE "cmp_gn4124_core/io_clk" FALLING;
# System clock
NET "clk20_vcxo_i" TNM_NET = "clk20_vcxo_i_grp";
TIMESPEC TS_clk20_vcxo_i = PERIOD "clk20_vcxo_i_grp" 50 ns HIGH 50%;
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
# DDR3
# 20MHz clock for DMTD
#NET "clk20_vcxo_i" TNM_NET = "clk20_vcxo_i_grp";
#TIMESPEC TS_clk20_vcxo_i = PERIOD "clk20_vcxo_i_grp" 50 ns HIGH 50%;
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK5";
TIMESPEC "TS_SYS_CLK5" = PERIOD "SYS_CLK5" 3.0 ns HIGH 50 %;
# DDR3
#NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK5";
#TIMESPEC "TS_SYS_CLK5" = PERIOD "SYS_CLK5" 3.0 ns HIGH 50 %;
# ADC
NET "adc0_dco_n_i" TNM_NET = adc_dco_n_i;
......
hdl/svec/rtl/svec_top_fmc_adc_100Ms.vhd
View file @ 96548f64
......@@ -8,7 +8,7 @@
-- : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2013-07-04
-- Last update: 2016-04-19
-- Last update: 2016-05-13
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Top entity of FMC ADC 100Ms/s design for Simple VME FMC
......@@ -60,8 +60,11 @@ entity svec_top_fmc_adc_100Ms is
g_CALIB_SOFT_IP : string := "TRUE");
port
(
-- Local 20MHz VCXO oscillator
clk_20m_vcxo_i : in std_logic;
-- Local oscillators
-- clk20_vcxo_i : in std_logic; -- 20MHz VCXO clock
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_n_i : in std_logic;
-- DAC interface (20MHz and 25MHz VCXO)
pll20dac_din_o : out std_logic;
......@@ -74,7 +77,7 @@ entity svec_top_fmc_adc_100Ms is
-- Reset from system fpga
rst_n_i : in std_logic;
-- Carrier font panel LEDs
-- Carrier front panel LEDs
fp_led_line_oen_o : out std_logic_vector(1 downto 0);
fp_led_line_o : out std_logic_vector(1 downto 0);
fp_led_column_o : out std_logic_vector(3 downto 0);
......@@ -439,6 +442,7 @@ architecture rtl of svec_top_fmc_adc_100Ms is
signal sys_clk_125 : std_logic;
signal sys_clk_fb : std_logic;
signal sys_clk_pll_locked : std_logic;
signal clk_125m_pllref : std_logic;
-- DDR3 clock
signal ddr_clk : std_logic;
......@@ -561,13 +565,6 @@ architecture rtl of svec_top_fmc_adc_100Ms is
begin
------------------------------------------------------------------------------
-- Clocks distribution from 20MHz TCXO
-- 62.500 MHz system clock
-- 125.000 MHz system clock
-- 333.333 MHz DDR3 clock
------------------------------------------------------------------------------
-- AD5662BRMZ-1 DAC output powers up to 0V. The output remains valid until a
-- write sequence arrives to the DAC.
-- To avoid spurious writes, the DAC interface outputs are fixed to safe values.
......@@ -578,10 +575,23 @@ begin
pll25dac_sclk_o <= '0';
pll25dac_sync_n_o <= '1';
cmp_sys_clk_buf : IBUFG
-- diff clock buffer from 125MHz clock reference
cmp_pll_clk_buf : IBUFGDS
generic map (
DIFF_TERM => TRUE,
IBUF_LOW_PWR => TRUE)
port map (
I => clk_20m_vcxo_i,
O => sys_clk_in);
O => clk_125m_pllref,
I => clk_125m_pllref_p_i,
IB => clk_125m_pllref_n_i);
-- just an alias to keep it backwards compatible
sys_clk_in <= clk_125m_pllref;
--cmp_sys_clk_buf : IBUFG
-- port map (
-- I => clk_20m_vcxo_i,
-- O => sys_clk_in);
cmp_sys_clk_pll : PLL_BASE
generic map (
......@@ -589,18 +599,18 @@ begin
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50,
CLKFBOUT_MULT => 8, -- 1GHz
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 8,
CLKOUT0_DIVIDE => 8, -- 125MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 16,
CLKOUT1_DIVIDE => 16,-- 62.5MHz
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 3,
CLKOUT2_DIVIDE => 3, -- 333MHz
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 50.0,
CLKIN_PERIOD => 8.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => sys_clk_fb,
......
hdl/svec/svec_top_fmc_adc_100Ms.ucf
View file @ 96548f64
......@@ -422,12 +422,12 @@ NET "ddr1_a_o[0]" IOSTANDARD = "SSTL15_II";
NET "rst_n_i" LOC = AD28;
NET "rst_n_i" IOSTANDARD = "LVCMOS33";
NET "clk_20m_vcxo_i" LOC = V26;
#NET "clk_125m_pllref_n_i" LOC = AB30;
#NET "clk_125m_pllref_p_i" LOC = AB28;
NET "clk_20m_vcxo_i" IOSTANDARD = "LVCMOS33";
#NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
#NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
#NET "clk_20m_vcxo_i" LOC = V26;
NET "clk_125m_pllref_n_i" LOC = AB30;
NET "clk_125m_pllref_p_i" LOC = AB28;
#NET "clk_20m_vcxo_i" IOSTANDARD = "LVCMOS33";
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
#----------------------------------------
# SFP slot
......@@ -899,19 +899,20 @@ NET "adc1_one_wire_b" IOSTANDARD = "LVCMOS25";
#===============================================================================
# System clock
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
NET "clk_20m_vcxo_i" TNM_NET = clk_20m_vcxo_i;
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
# 20MHz clock for DMTD
#NET "clk_20m_vcxo_i" TNM_NET = clk_20m_vcxo_i;
#TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
# DDR3
#NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK5";
#TIMESPEC "TS_SYS_CLK5" = PERIOD "SYS_CLK5" 3.0 ns HIGH 50 %;
# ADC
NET "adc0_dco_n_i" TNM_NET = adc0_dco_n_i;
TIMESPEC TS_adc0_dco_n_i = PERIOD "adc0_dco_n_i" 2 ns HIGH 50%;
NET "adc1_dco_n_i" TNM_NET = adc1_dco_n_i;
TIMESPEC TS_adc1_dco_n_i = PERIOD "adc1_dco_n_i" 2 ns HIGH 50%;
......
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