migrate complete RTL and SPEC ref memory map and interconnect to Cheby

920b7a16 · Dimitris Lampridis · 8008de69 · 8008de69 · 8008de69 · 8008de69
Commit 920b7a16 authored Dec 10, 2019 by Dimitris Lampridis
43 changed files
--- a/doc/manual/fmc_adc_100Ms_csr.html
+++ b/doc/manual/fmc_adc_100Ms_csr.html
--- a/doc/manual/fmc_adc_alt_trigin.html
+++ b/doc/manual/fmc_adc_alt_trigin.html
--- a/doc/manual/fmc_adc_alt_trigout.html
+++ b/doc/manual/fmc_adc_alt_trigout.html
--- a/doc/manual/fmc_adc_aux_trigin.html
+++ b/doc/manual/fmc_adc_aux_trigin.html
--- a/doc/manual/fmc_adc_aux_trigout.html
+++ b/doc/manual/fmc_adc_aux_trigout.html
--- a/doc/manual/spec_carrier_csr.html
+++ b/doc/manual/spec_carrier_csr.html
--- a/doc/manual/svec_carrier_csr.html
+++ b/doc/manual/svec_carrier_csr.html
--- a/doc/manual/timetag_core_regs.html
+++ b/doc/manual/timetag_core_regs.html
--- a/hdl/rtl/Makefile
+++ b/hdl/rtl/Makefile
 SIM   =../testbench/include
-DOC   =../../doc/manual
 SW    =../../software/include/hw

 SOURCES = $(wildcard *.cheby)
@@ -13,6 +12,5 @@ $(TARGETS): %.vhd : %.cheby
 	@echo "\n\033[34m\033[1m-> Processing file $<\033[0m"
 	@cheby -i $< --gen-hdl=$@
 	@cheby -i $< \
-		--gen-doc=$(DOC)/$(@:.vhd=.html) \
 	        --gen-consts=$(SIM)/$(@:.vhd=.v) \
 		--gen-c=$(SW)/$(@:.vhd=.h)
--- a/hdl/rtl/fmc_adc_100Ms_csr.cheby
+++ b/hdl/rtl/fmc_adc_100Ms_csr.cheby
 memory-map:
  bus: wb-32-be
  name: fmc_adc_100ms_csr
+  size: 0x200
  description: FMC ADC 100MS/s core registers
  comment: |
    Wishbone slave for FMC ADC 100MS/s core

--- a/hdl/rtl/fmc_adc_100Ms_csr.vhd
+++ b/hdl/rtl/fmc_adc_100Ms_csr.vhd
--- a/hdl/rtl/fmc_adc_aux_trigin.cheby
+++ b/hdl/rtl/fmc_adc_aux_trigin.cheby
--- a/hdl/rtl/fmc_adc_aux_trigin.vhd
+++ b/hdl/rtl/fmc_adc_aux_trigin.vhd
--- a/hdl/rtl/fmc_adc_aux_trigout.cheby
+++ b/hdl/rtl/fmc_adc_aux_trigout.cheby
--- a/hdl/rtl/fmc_adc_aux_trigout.vhd
+++ b/hdl/rtl/fmc_adc_aux_trigout.vhd
--- a/hdl/cheby/fmc_adc_mezzanine_mmap.cheby
+++ b/hdl/cheby/fmc_adc_mezzanine_mmap.cheby
+memory-map:
+  name: fmc_adc_mezzanine_mmap
+  bus: wb-32-be
+  description: FMC-ADC-100M mezzanine memory map
+  size: 0x2000
+  x-hdl:
+    busgroup: True
+  children:
+    - submap:
+        name: fmc_adc_100m_csr
+        address: 0x1000
+        description: FMC ADC 100M CSR
+        filename: fmc_adc_100Ms_csr.cheby
+    - submap:
+        name: fmc_i2c_master
+        address: 0x1400
+        size: 0x100
+        interface: wb-32-be
+        x-hdl:
+          busgroup: True
+        description: Mezzanine system management I2C master
+    - submap:
+        name: fmc_adc_eic
+        address: 0x1500
+        size: 0x10
+        interface: wb-32-be
+        x-hdl:
+          busgroup: True
+        description: FMC ADC Embedded Interrupt Controller
+    - submap:
+        name: si570_i2c_master
+        address: 0x1600
+        size: 0x100
+        interface: wb-32-be
+        x-hdl:
+          busgroup: True
+        description: Si570 control I2C master
+    - submap:
+        name: ds18b20_onewire_master
+        address: 0x1700
+        size: 0x100
+        interface: wb-32-be
+        x-hdl:
+          busgroup: True
+        description: DS18B20 OneWire master
+    - submap:
+        name: fmc_spi_master
+        address: 0x1800
+        size: 0x20
+        interface: wb-32-be
+        x-hdl:
+          busgroup: True
+        description: Mezzanine SPI master (ADC control + DAC offsets)
+    - submap:
+        name: timetag_core
+        address: 0x1900
+        description: Timetag Core
+        filename: timetag_core_regs.cheby
--- a/hdl/cheby/fmc_adc_mezzanine_mmap.vhd
+++ b/hdl/cheby/fmc_adc_mezzanine_mmap.vhd
--- a/hdl/cheby/spec_ref_fmc_adc_100Ms_mmap.cheby
+++ b/hdl/cheby/spec_ref_fmc_adc_100Ms_mmap.cheby
+memory-map:
+  name: spec_ref_fmc_adc_100m_mmap
+  bus: wb-32-be
+  description: SPEC FMC-ADC-100M memory map
+  size: 0x6000
+  x-hdl:
+    busgroup: True
+  children:
+    - submap:
+        name: metadata
+        address: 0x2000
+        size: 0x40
+        interface: wb-32-be
+        x-hdl:
+          busgroup: True
+        description: a ROM containing the application metadata
+    - submap:
+        name: fmc_adc_mezzanine
+        address: 0x4000
+        description: FMC ADC Mezzanine
+        filename: fmc_adc_mezzanine_mmap.cheby
--- a/hdl/top/spec_ref_design/spec_carrier_csr.vhd
+++ b/hdl/top/spec_ref_design/spec_carrier_csr.vhd
--- a/hdl/rtl/timetag_core_regs.cheby
+++ b/hdl/rtl/timetag_core_regs.cheby
@@ -2,6 +2,7 @@ memory-map:
  bus: wb-32-be
  name: timetag_core_regs
  description: Time-tagging core registers
+  size: 0x80
  comment: |
    Wishbone slave for registers related to time-tagging core
  x-hdl:

--- a/hdl/rtl/timetag_core_regs.vhd
+++ b/hdl/rtl/timetag_core_regs.vhd
--- a/hdl/rtl/Manifest.py
+++ b/hdl/rtl/Manifest.py
@@ -3,11 +3,12 @@ files = [
    "fmc_adc_mezzanine_pkg.vhd",
    "fmc_adc_100Ms_core.vhd",
    "fmc_adc_100Ms_core_pkg.vhd",
-    "fmc_adc_100Ms_csr.vhd",
-    "fmc_adc_aux_trigin.vhd",
-    "fmc_adc_aux_trigout.vhd",
    "fmc_adc_eic.vhd",
    "offset_gain_s.vhd",
-    "timetag_core_regs.vhd",
    "timetag_core.vhd",
+    "../cheby/fmc_adc_mezzanine_mmap.vhd",
+    "../cheby/fmc_adc_100Ms_csr.vhd",
+    "../cheby/fmc_adc_aux_trigin.vhd",
+    "../cheby/fmc_adc_aux_trigout.vhd",
+    "../cheby/timetag_core_regs.vhd",
 ]
--- a/hdl/rtl/fmc_adc_mezzanine.vhd
+++ b/hdl/rtl/fmc_adc_mezzanine.vhd
--- a/hdl/testbench/include/fmc_adc_100Ms_csr.v
+++ b/hdl/testbench/include/fmc_adc_100Ms_csr.v
-`define FMC_ADC_100MS_CSR_SIZE 344
+`define FMC_ADC_100MS_CSR_SIZE 512
 `define ADDR_FMC_ADC_100MS_CSR_CTL 'h0
 `define FMC_ADC_100MS_CSR_CTL_FSM_CMD_OFFSET 0
 `define FMC_ADC_100MS_CSR_CTL_FSM_CMD 'h3

--- a/hdl/testbench/include/fmc_adc_mezzanine_mmap.v
+++ b/hdl/testbench/include/fmc_adc_mezzanine_mmap.v
+`define FMC_ADC_MEZZANINE_MMAP_SIZE 8192
+`define ADDR_FMC_ADC_MEZZANINE_MMAP_FMC_ADC_100M_CSR 'h1000
+`define FMC_ADC_MEZZANINE_MMAP_FMC_ADC_100M_CSR_SIZE 512
+`define ADDR_FMC_ADC_MEZZANINE_MMAP_FMC_I2C_MASTER 'h1400
+`define FMC_ADC_MEZZANINE_MMAP_FMC_I2C_MASTER_SIZE 256
+`define ADDR_FMC_ADC_MEZZANINE_MMAP_FMC_ADC_EIC 'h1500
+`define FMC_ADC_MEZZANINE_MMAP_FMC_ADC_EIC_SIZE 16
+`define ADDR_FMC_ADC_MEZZANINE_MMAP_SI570_I2C_MASTER 'h1600
+`define FMC_ADC_MEZZANINE_MMAP_SI570_I2C_MASTER_SIZE 256
+`define ADDR_FMC_ADC_MEZZANINE_MMAP_DS18B20_ONEWIRE_MASTER 'h1700
+`define FMC_ADC_MEZZANINE_MMAP_DS18B20_ONEWIRE_MASTER_SIZE 256
+`define ADDR_FMC_ADC_MEZZANINE_MMAP_FMC_SPI_MASTER 'h1800
+`define FMC_ADC_MEZZANINE_MMAP_FMC_SPI_MASTER_SIZE 32
+`define ADDR_FMC_ADC_MEZZANINE_MMAP_TIMETAG_CORE 'h1900
+`define FMC_ADC_MEZZANINE_MMAP_TIMETAG_CORE_SIZE 128
--- a/hdl/testbench/include/spec_ref_fmc_adc_100Ms_mmap.v
+++ b/hdl/testbench/include/spec_ref_fmc_adc_100Ms_mmap.v
+`define SPEC_REF_FMC_ADC_100M_MMAP_SIZE 24576
+`define ADDR_SPEC_REF_FMC_ADC_100M_MMAP_METADATA 'h2000
+`define SPEC_REF_FMC_ADC_100M_MMAP_METADATA_SIZE 64
+`define ADDR_SPEC_REF_FMC_ADC_100M_MMAP_FMC_ADC_MEZZANINE 'h4000
+`define SPEC_REF_FMC_ADC_100M_MMAP_FMC_ADC_MEZZANINE_SIZE 8192
--- a/hdl/testbench/include/timetag_core_regs.v
+++ b/hdl/testbench/include/timetag_core_regs.v
-`define TIMETAG_CORE_REGS_SIZE 72
+`define TIMETAG_CORE_REGS_SIZE 128
 `define ADDR_TIMETAG_CORE_REGS_SECONDS_UPPER 'h0
 `define TIMETAG_CORE_REGS_SECONDS_UPPER_OFFSET 0
 `define TIMETAG_CORE_REGS_SECONDS_UPPER 'hff

--- a/hdl/top/spec_ref_design/Makefile
+++ b/hdl/top/spec_ref_design/Makefile
-SIM   =../../testbench/include
-DOC   =../../../doc/manual
-SW    =../../../software/include/hw
-
-SOURCES = $(wildcard *.cheby)
-TARGETS = $(SOURCES:.cheby=.vhd)
-
-all: $(TARGETS)
-
-.PHONY: $(TARGETS)
-
-$(TARGETS): %.vhd : %.cheby
-	@echo "\n\033[34m\033[1m-> Processing file $<\033[0m"
-	@cheby -i $< --gen-hdl=$@
-	@cheby -i $< \
-		--gen-doc=$(DOC)/$(@:.vhd=.html) \
-	        --gen-consts=$(SIM)/$(@:.vhd=.v) \
-		--gen-c=$(SW)/$(@:.vhd=.h)
--- a/hdl/top/spec_ref_design/Manifest.py
+++ b/hdl/top/spec_ref_design/Manifest.py
 files = [
    "spec_ref_fmc_adc_100Ms.vhd",
-    "spec_carrier_csr.vhd",
-    "dma_eic.vhd",
+    "../../cheby/spec_ref_fmc_adc_100Ms_mmap.vhd",
 ]

 fetchto = "../../ip_cores"

--- a/hdl/top/spec_ref_design/dma_eic.vhd
+++ b/hdl/top/spec_ref_design/dma_eic.vhd
--- a/hdl/top/spec_ref_design/spec_carrier_csr.cheby
+++ b/hdl/top/spec_ref_design/spec_carrier_csr.cheby
--- a/hdl/top/spec_ref_design/spec_ref_fmc_adc_100Ms.vhd
+++ b/hdl/top/spec_ref_design/spec_ref_fmc_adc_100Ms.vhd
--- a/hdl/top/spec_ref_design/wb_gen/Makefile
+++ b/hdl/top/spec_ref_design/wb_gen/Makefile
-WBGEN2=$(shell which wbgen2)
-RTL=../
-TEX=../../../../doc/manual/spec/
-
-all: dma_eic
-
-dma_eic:
-	$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
-	$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
--- a/hdl/top/spec_ref_design/wb_gen/dma_eic.h
+++ b/hdl/top/spec_ref_design/wb_gen/dma_eic.h
--- a/hdl/top/spec_ref_design/wb_gen/dma_eic.htm
+++ b/hdl/top/spec_ref_design/wb_gen/dma_eic.htm
--- a/hdl/top/spec_ref_design/wb_gen/dma_eic.wb
+++ b/hdl/top/spec_ref_design/wb_gen/dma_eic.wb
-peripheral {
-	name = "GN4124 DMA enhanced interrupt controller";
-	description = "Enhanced interrrupt controller for GN4124 DMA.";
-	hdl_entity = "dma_eic";
-        prefix = "dma_eic";
-
-	irq {
-            name = "DMA done interrupt";
-	    description = "DMA done interrupt line (rising edge sensitive).";
-            prefix = "dma_done";
-	    trigger = EDGE_RISING;
-	};
-
-        irq {
-            name = "DMA error interrupt";
-	    description = "DMA error interrupt line (rising edge sensitive).";
-            prefix = "dma_error";
-	    trigger = EDGE_RISING;
-	};
-
-};
--- a/software/include/hw/fmc_adc_100Ms_csr.h
+++ b/software/include/hw/fmc_adc_100Ms_csr.h
--- a/software/include/hw/fmc_adc_aux_trigin.h
+++ b/software/include/hw/fmc_adc_aux_trigin.h
 #ifndef __CHEBY__AUX_TRIGIN__H__
 #define __CHEBY__AUX_TRIGIN__H__
+#define AUX_TRIGIN_SIZE 20

 /* Core version */
 #define AUX_TRIGIN_VERSION 0x0UL
@@ -18,13 +19,13 @@
 struct aux_trigin {
  /* [0x0]: REG (ro) Core version */
  uint32_t version;
-  
+
  /* [0x4]: REG (rw) Control register */
  uint32_t ctrl;
-  
+
  /* [0x8]: REG (rw) Time (seconds) to trigger */
  uint64_t seconds;
-  
+
  /* [0x10]: REG (rw) Time (cycles) to trigger */
  uint32_t cycles;
 };

--- a/software/include/hw/fmc_adc_aux_trigout.h
+++ b/software/include/hw/fmc_adc_aux_trigout.h
--- a/software/include/hw/fmc_adc_mezzanine_mmap.h
+++ b/software/include/hw/fmc_adc_mezzanine_mmap.h
--- a/software/include/hw/spec_carrier_csr.h
+++ b/software/include/hw/spec_carrier_csr.h
--- a/software/include/hw/spec_ref_fmc_adc_100Ms_mmap.h
+++ b/software/include/hw/spec_ref_fmc_adc_100Ms_mmap.h
--- a/software/include/hw/timetag_core_regs.h
+++ b/software/include/hw/timetag_core_regs.h