Commit 8b4a0b5a authored by Matthieu Cattin's avatar Matthieu Cattin

Replace csr wishbone address decoder by crossbar with sdb support.

Update Manifest to take the git versions of the ddr and gn4124 cores.
parent 99c34478
files = ["fmc_adc_100Ms_core.vhd",
"fmc_adc_100Ms_core_pkg.vhd",
"fmc_adc_100Ms_csr.vhd",
"offset_gain_s.vhd"]
......@@ -8,9 +8,8 @@ files = [
modules = {
"local" : "../../adc/rtl",
"svn" : [ "http://svn.ohwr.org/ddr3-sp6-core/trunk/hdl",
"http://svn.ohwr.org/gn4124-core/trunk/hdl/gn4124core/rtl",
"http://svn.ohwr.org/gn4124-core/trunk/hdl/common/rtl"],
"git" : "git://ohwr.org/hdl-core-lib/general-cores.git"}
"git" : ["git://ohwr.org/hdl-core-lib/general-cores.git::no_coregen",
"git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git::spec_bank3_64b_32b",
"git://ohwr.org/hdl-core-lib/gn4124-core.git::master"]}
fetchto="../ip_cores"
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