Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
F
FMC ADC 100M 14b 4cha
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
FMC ADC 100M 14b 4cha
Commits
76513c14
Commit
76513c14
authored
May 31, 2022
by
Tristan Gingold
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
hdl: clean-up (remove current adc value read extra registers)
parent
ad355619
Hide whitespace changes
Inline
Side-by-side
Showing
9 changed files
with
115 additions
and
170 deletions
+115
-170
fmc_adc_100Ms_channel_regs.cheby
hdl/cheby/fmc_adc_100Ms_channel_regs.cheby
+1
-23
fmc_adc_100Ms_channel_regs.vhd
hdl/cheby/fmc_adc_100Ms_channel_regs.vhd
+22
-45
fmc_adc_100Ms_csr.vhd
hdl/cheby/fmc_adc_100Ms_csr.vhd
+58
-48
fmc_adc_100Ms_core.vhd
hdl/rtl/fmc_adc_100Ms_core.vhd
+1
-30
offset_gain_s.vhd
hdl/rtl/offset_gain_s.vhd
+1
-4
fmc_adc_100Ms_channel_regs.v
hdl/testbench/include/fmc_adc_100Ms_channel_regs.v
+1
-7
fmc_adc_100Ms_csr.v
hdl/testbench/include/fmc_adc_100Ms_csr.v
+8
-8
fmc_adc_100Ms_channel_regs.h
software/include/hw/fmc_adc_100Ms_channel_regs.h
+19
-1
fmc_adc_100Ms_csr.h
software/include/hw/fmc_adc_100Ms_csr.h
+4
-4
No files found.
hdl/cheby/fmc_adc_100Ms_channel_regs.cheby
View file @
76513c14
...
...
@@ -131,31 +131,9 @@ memory-map:
address: 0x0000001c
width: 32
access: ro
description: Channel saturation register
description: Channel saturation register
(read from hw)
children:
- field:
name: val
range: 14-0
description: Saturation value for channel
- reg:
name: calib_sta
address: 0x00000020
width: 32
access: ro
description: Channel adjusted value register
children:
- field:
name: val
range: 15-0
description: Channel adjusted current ADC value
- reg:
name: prod_sta
address: 0x00000024
width: 32
access: ro
description: Channel adjusted value register
children:
- field:
name: val
range: 16-0
description: Channel adjusted by gain current ADC value
hdl/cheby/fmc_adc_100Ms_channel_regs.vhd
View file @
76513c14
...
...
@@ -28,8 +28,6 @@ package fmc_adc_100ms_channel_regs_pkg is
calib_val_gain
:
std_logic_vector
(
15
downto
0
);
calib_val_offset
:
std_logic_vector
(
15
downto
0
);
sat_val_val
:
std_logic_vector
(
14
downto
0
);
calib_sta_val
:
std_logic_vector
(
15
downto
0
);
prod_sta_val
:
std_logic_vector
(
16
downto
0
);
end
record
t_fmc_adc_100ms_ch_slave_out
;
subtype
t_fmc_adc_100ms_ch_master_in
is
t_fmc_adc_100ms_ch_slave_out
;
...
...
@@ -54,7 +52,7 @@ entity fmc_adc_100ms_channel_regs is
end
fmc_adc_100ms_channel_regs
;
architecture
syn
of
fmc_adc_100ms_channel_regs
is
signal
adr_int
:
std_logic_vector
(
5
downto
2
);
signal
adr_int
:
std_logic_vector
(
4
downto
2
);
signal
rd_req_int
:
std_logic
;
signal
wr_req_int
:
std_logic
;
signal
rd_ack_int
:
std_logic
;
...
...
@@ -83,12 +81,12 @@ architecture syn of fmc_adc_100ms_channel_regs is
signal
rd_ack_d0
:
std_logic
;
signal
rd_dat_d0
:
std_logic_vector
(
31
downto
0
);
signal
wr_req_d0
:
std_logic
;
signal
wr_adr_d0
:
std_logic_vector
(
5
downto
2
);
signal
wr_adr_d0
:
std_logic_vector
(
4
downto
2
);
signal
wr_dat_d0
:
std_logic_vector
(
31
downto
0
);
begin
-- WB decode signals
adr_int
<=
wb_i
.
adr
(
5
downto
2
);
adr_int
<=
wb_i
.
adr
(
4
downto
2
);
wb_en
<=
wb_i
.
cyc
and
wb_i
.
stb
;
process
(
clk_i
)
begin
...
...
@@ -227,10 +225,6 @@ begin
-- Register sat_val
-- Register calib_sta
-- Register prod_sta
-- Process for write requests.
process
(
wr_adr_d0
,
wr_req_d0
,
ctl_wack
,
calib_wack
,
sat_wack
,
trig_thres_wack
,
trig_dly_wack
)
begin
...
...
@@ -239,42 +233,36 @@ begin
sat_wreq
<=
'0'
;
trig_thres_wreq
<=
'0'
;
trig_dly_wreq
<=
'0'
;
case
wr_adr_d0
(
5
downto
2
)
is
when
"000
0
"
=>
case
wr_adr_d0
(
4
downto
2
)
is
when
"000"
=>
-- Reg ctl
ctl_wreq
<=
wr_req_d0
;
wr_ack_int
<=
ctl_wack
;
when
"00
0
1"
=>
when
"001"
=>
-- Reg sta
wr_ack_int
<=
wr_req_d0
;
when
"0
0
10"
=>
when
"010"
=>
-- Reg calib
calib_wreq
<=
wr_req_d0
;
wr_ack_int
<=
calib_wack
;
when
"0
0
11"
=>
when
"011"
=>
-- Reg sat
sat_wreq
<=
wr_req_d0
;
wr_ack_int
<=
sat_wack
;
when
"
0
100"
=>
when
"100"
=>
-- Reg trig_thres
trig_thres_wreq
<=
wr_req_d0
;
wr_ack_int
<=
trig_thres_wack
;
when
"
0
101"
=>
when
"101"
=>
-- Reg trig_dly
trig_dly_wreq
<=
wr_req_d0
;
wr_ack_int
<=
trig_dly_wack
;
when
"
0
110"
=>
when
"110"
=>
-- Reg calib_val
wr_ack_int
<=
wr_req_d0
;
when
"
0
111"
=>
when
"111"
=>
-- Reg sat_val
wr_ack_int
<=
wr_req_d0
;
when
"1000"
=>
-- Reg calib_sta
wr_ack_int
<=
wr_req_d0
;
when
"1001"
=>
-- Reg prod_sta
wr_ack_int
<=
wr_req_d0
;
when
others
=>
wr_ack_int
<=
wr_req_d0
;
end
case
;
...
...
@@ -286,60 +274,49 @@ begin
trig_thres_hyst_reg
,
trig_dly_reg
,
fmc_adc_100ms_ch_i
.
calib_val_gain
,
fmc_adc_100ms_ch_i
.
calib_val_offset
,
fmc_adc_100ms_ch_i
.
sat_val_val
,
fmc_adc_100ms_ch_i
.
calib_sta_val
,
fmc_adc_100ms_ch_i
.
prod_sta_val
)
begin
fmc_adc_100ms_ch_i
.
sat_val_val
)
begin
-- By default ack read requests
rd_dat_d0
<=
(
others
=>
'X'
);
case
adr_int
(
5
downto
2
)
is
when
"000
0
"
=>
case
adr_int
(
4
downto
2
)
is
when
"000"
=>
-- Reg ctl
rd_ack_d0
<=
rd_req_int
;
rd_dat_d0
(
6
downto
0
)
<=
ctl_ssr_reg
;
rd_dat_d0
(
31
downto
7
)
<=
(
others
=>
'0'
);
when
"00
0
1"
=>
when
"001"
=>
-- Reg sta
rd_ack_d0
<=
rd_req_int
;
rd_dat_d0
(
15
downto
0
)
<=
fmc_adc_100ms_ch_i
.
sta_val
;
rd_dat_d0
(
31
downto
16
)
<=
(
others
=>
'0'
);
when
"0
0
10"
=>
when
"010"
=>
-- Reg calib
rd_ack_d0
<=
rd_req_int
;
rd_dat_d0
(
15
downto
0
)
<=
calib_gain_reg
;
rd_dat_d0
(
31
downto
16
)
<=
calib_offset_reg
;
when
"0
0
11"
=>
when
"011"
=>
-- Reg sat
rd_ack_d0
<=
rd_req_int
;
rd_dat_d0
(
14
downto
0
)
<=
sat_val_reg
;
rd_dat_d0
(
31
downto
15
)
<=
(
others
=>
'0'
);
when
"
0
100"
=>
when
"100"
=>
-- Reg trig_thres
rd_ack_d0
<=
rd_req_int
;
rd_dat_d0
(
15
downto
0
)
<=
trig_thres_val_reg
;
rd_dat_d0
(
31
downto
16
)
<=
trig_thres_hyst_reg
;
when
"
0
101"
=>
when
"101"
=>
-- Reg trig_dly
rd_ack_d0
<=
rd_req_int
;
rd_dat_d0
<=
trig_dly_reg
;
when
"
0
110"
=>
when
"110"
=>
-- Reg calib_val
rd_ack_d0
<=
rd_req_int
;
rd_dat_d0
(
15
downto
0
)
<=
fmc_adc_100ms_ch_i
.
calib_val_gain
;
rd_dat_d0
(
31
downto
16
)
<=
fmc_adc_100ms_ch_i
.
calib_val_offset
;
when
"
0
111"
=>
when
"111"
=>
-- Reg sat_val
rd_ack_d0
<=
rd_req_int
;
rd_dat_d0
(
14
downto
0
)
<=
fmc_adc_100ms_ch_i
.
sat_val_val
;
rd_dat_d0
(
31
downto
15
)
<=
(
others
=>
'0'
);
when
"1000"
=>
-- Reg calib_sta
rd_ack_d0
<=
rd_req_int
;
rd_dat_d0
(
15
downto
0
)
<=
fmc_adc_100ms_ch_i
.
calib_sta_val
;
rd_dat_d0
(
31
downto
16
)
<=
(
others
=>
'0'
);
when
"1001"
=>
-- Reg prod_sta
rd_ack_d0
<=
rd_req_int
;
rd_dat_d0
(
16
downto
0
)
<=
fmc_adc_100ms_ch_i
.
prod_sta_val
;
rd_dat_d0
(
31
downto
17
)
<=
(
others
=>
'0'
);
when
others
=>
rd_ack_d0
<=
rd_req_int
;
end
case
;
...
...
hdl/cheby/fmc_adc_100Ms_csr.vhd
View file @
76513c14
...
...
@@ -455,7 +455,7 @@ begin
fmc_adc_ch1_o
.
stb
<=
fmc_adc_ch1_tr
;
fmc_adc_ch1_wack
<=
fmc_adc_ch1_i
.
ack
and
fmc_adc_ch1_wt
;
fmc_adc_ch1_rack
<=
fmc_adc_ch1_i
.
ack
and
fmc_adc_ch1_rt
;
fmc_adc_ch1_o
.
adr
<=
((
2
5
downto
0
=>
'0'
)
&
rd_adr_d0
(
5
downto
2
))
&
(
1
downto
0
=>
'0'
);
fmc_adc_ch1_o
.
adr
<=
((
2
6
downto
0
=>
'0'
)
&
rd_adr_d0
(
4
downto
2
))
&
(
1
downto
0
=>
'0'
);
fmc_adc_ch1_o
.
sel
<=
wr_sel_d0
;
fmc_adc_ch1_o
.
we
<=
fmc_adc_ch1_wt
;
fmc_adc_ch1_o
.
dat
<=
wr_dat_d0
;
...
...
@@ -477,7 +477,7 @@ begin
fmc_adc_ch2_o
.
stb
<=
fmc_adc_ch2_tr
;
fmc_adc_ch2_wack
<=
fmc_adc_ch2_i
.
ack
and
fmc_adc_ch2_wt
;
fmc_adc_ch2_rack
<=
fmc_adc_ch2_i
.
ack
and
fmc_adc_ch2_rt
;
fmc_adc_ch2_o
.
adr
<=
((
2
5
downto
0
=>
'0'
)
&
rd_adr_d0
(
5
downto
2
))
&
(
1
downto
0
=>
'0'
);
fmc_adc_ch2_o
.
adr
<=
((
2
6
downto
0
=>
'0'
)
&
rd_adr_d0
(
4
downto
2
))
&
(
1
downto
0
=>
'0'
);
fmc_adc_ch2_o
.
sel
<=
wr_sel_d0
;
fmc_adc_ch2_o
.
we
<=
fmc_adc_ch2_wt
;
fmc_adc_ch2_o
.
dat
<=
wr_dat_d0
;
...
...
@@ -499,7 +499,7 @@ begin
fmc_adc_ch3_o
.
stb
<=
fmc_adc_ch3_tr
;
fmc_adc_ch3_wack
<=
fmc_adc_ch3_i
.
ack
and
fmc_adc_ch3_wt
;
fmc_adc_ch3_rack
<=
fmc_adc_ch3_i
.
ack
and
fmc_adc_ch3_rt
;
fmc_adc_ch3_o
.
adr
<=
((
2
5
downto
0
=>
'0'
)
&
rd_adr_d0
(
5
downto
2
))
&
(
1
downto
0
=>
'0'
);
fmc_adc_ch3_o
.
adr
<=
((
2
6
downto
0
=>
'0'
)
&
rd_adr_d0
(
4
downto
2
))
&
(
1
downto
0
=>
'0'
);
fmc_adc_ch3_o
.
sel
<=
wr_sel_d0
;
fmc_adc_ch3_o
.
we
<=
fmc_adc_ch3_wt
;
fmc_adc_ch3_o
.
dat
<=
wr_dat_d0
;
...
...
@@ -521,7 +521,7 @@ begin
fmc_adc_ch4_o
.
stb
<=
fmc_adc_ch4_tr
;
fmc_adc_ch4_wack
<=
fmc_adc_ch4_i
.
ack
and
fmc_adc_ch4_wt
;
fmc_adc_ch4_rack
<=
fmc_adc_ch4_i
.
ack
and
fmc_adc_ch4_rt
;
fmc_adc_ch4_o
.
adr
<=
((
2
5
downto
0
=>
'0'
)
&
rd_adr_d0
(
5
downto
2
))
&
(
1
downto
0
=>
'0'
);
fmc_adc_ch4_o
.
adr
<=
((
2
6
downto
0
=>
'0'
)
&
rd_adr_d0
(
4
downto
2
))
&
(
1
downto
0
=>
'0'
);
fmc_adc_ch4_o
.
sel
<=
wr_sel_d0
;
fmc_adc_ch4_o
.
we
<=
fmc_adc_ch4_wt
;
fmc_adc_ch4_o
.
dat
<=
wr_dat_d0
;
...
...
@@ -544,79 +544,84 @@ begin
fmc_adc_ch2_we
<=
'0'
;
fmc_adc_ch3_we
<=
'0'
;
fmc_adc_ch4_we
<=
'0'
;
case
rd_adr_d0
(
8
downto
6
)
is
when
"000"
=>
case
rd_adr_d0
(
5
downto
2
)
is
when
"000
0
"
=>
case
rd_adr_d0
(
8
downto
5
)
is
when
"000
0
"
=>
case
rd_adr_d0
(
4
downto
2
)
is
when
"000"
=>
-- Reg ctl
ctl_wreq
<=
wr_req_d0
;
wr_ack_d0
<=
ctl_wack
;
when
"00
0
1"
=>
when
"001"
=>
-- Reg sta
wr_ack_d0
<=
wr_req_d0
;
when
"0
0
10"
=>
when
"010"
=>
-- Reg trig_stat
wr_ack_d0
<=
wr_req_d0
;
when
"0
0
11"
=>
when
"011"
=>
-- Reg trig_en
trig_en_wreq
<=
wr_req_d0
;
wr_ack_d0
<=
trig_en_wack
;
when
"
0
100"
=>
when
"100"
=>
-- Reg trig_pol
trig_pol_wreq
<=
wr_req_d0
;
wr_ack_d0
<=
trig_pol_wack
;
when
"
0
101"
=>
when
"101"
=>
-- Reg ext_trig_dly
ext_trig_dly_wreq
<=
wr_req_d0
;
wr_ack_d0
<=
ext_trig_dly_wack
;
when
"
0
110"
=>
when
"110"
=>
-- Reg sw_trig
sw_trig_wreq
<=
wr_req_d0
;
wr_ack_d0
<=
wr_req_d0
;
when
"
0
111"
=>
when
"111"
=>
-- Reg shots
shots_wreq
<=
wr_req_d0
;
wr_ack_d0
<=
shots_wack
;
when
"1000"
=>
when
others
=>
wr_ack_d0
<=
wr_req_d0
;
end
case
;
when
"0001"
=>
case
rd_adr_d0
(
4
downto
2
)
is
when
"000"
=>
-- Reg multi_depth
wr_ack_d0
<=
wr_req_d0
;
when
"
1
001"
=>
when
"001"
=>
-- Reg trig_pos
wr_ack_d0
<=
wr_req_d0
;
when
"
1
010"
=>
when
"010"
=>
-- Reg fs_freq
wr_ack_d0
<=
wr_req_d0
;
when
"
1
011"
=>
when
"011"
=>
-- Reg downsample
downsample_wreq
<=
wr_req_d0
;
wr_ack_d0
<=
downsample_wack
;
when
"1
1
00"
=>
when
"100"
=>
-- Reg pre_samples
pre_samples_wreq
<=
wr_req_d0
;
wr_ack_d0
<=
pre_samples_wack
;
when
"1
1
01"
=>
when
"101"
=>
-- Reg post_samples
post_samples_wreq
<=
wr_req_d0
;
wr_ack_d0
<=
post_samples_wack
;
when
"11
1
0"
=>
when
"110"
=>
-- Reg samples_cnt
wr_ack_d0
<=
wr_req_d0
;
when
others
=>
wr_ack_d0
<=
wr_req_d0
;
end
case
;
when
"010"
=>
when
"010
0
"
=>
-- Submap fmc_adc_ch1
fmc_adc_ch1_we
<=
wr_req_d0
;
wr_ack_d0
<=
fmc_adc_ch1_wack
;
when
"011"
=>
when
"011
0
"
=>
-- Submap fmc_adc_ch2
fmc_adc_ch2_we
<=
wr_req_d0
;
wr_ack_d0
<=
fmc_adc_ch2_wack
;
when
"100"
=>
when
"100
0
"
=>
-- Submap fmc_adc_ch3
fmc_adc_ch3_we
<=
wr_req_d0
;
wr_ack_d0
<=
fmc_adc_ch3_wack
;
when
"101"
=>
when
"101
0
"
=>
-- Submap fmc_adc_ch4
fmc_adc_ch4_we
<=
wr_req_d0
;
wr_ack_d0
<=
fmc_adc_ch4_wack
;
...
...
@@ -660,10 +665,10 @@ begin
fmc_adc_ch2_re
<=
'0'
;
fmc_adc_ch3_re
<=
'0'
;
fmc_adc_ch4_re
<=
'0'
;
case
rd_adr_d0
(
8
downto
6
)
is
when
"000"
=>
case
rd_adr_d0
(
5
downto
2
)
is
when
"000
0
"
=>
case
rd_adr_d0
(
8
downto
5
)
is
when
"000
0
"
=>
case
rd_adr_d0
(
4
downto
2
)
is
when
"000"
=>
-- Reg ctl
rd_ack_d0
<=
rd_req_d0
;
rd_dat_d0
(
1
downto
0
)
<=
fmc_adc_100ms_csr_i
.
ctl_fsm_cmd
;
...
...
@@ -677,7 +682,7 @@ begin
rd_dat_d0
(
14
downto
9
)
<=
(
others
=>
'0'
);
rd_dat_d0
(
15
)
<=
fmc_adc_100ms_csr_i
.
ctl_calib_apply
;
rd_dat_d0
(
31
downto
16
)
<=
(
others
=>
'0'
);
when
"00
0
1"
=>
when
"001"
=>
-- Reg sta
rd_ack_d0
<=
rd_req_d0
;
rd_dat_d0
(
2
downto
0
)
<=
fmc_adc_100ms_csr_i
.
sta_fsm
;
...
...
@@ -688,7 +693,7 @@ begin
rd_dat_d0
(
14
downto
8
)
<=
(
others
=>
'0'
);
rd_dat_d0
(
15
)
<=
fmc_adc_100ms_csr_i
.
sta_calib_busy
;
rd_dat_d0
(
31
downto
16
)
<=
(
others
=>
'0'
);
when
"0
0
10"
=>
when
"010"
=>
-- Reg trig_stat
rd_ack_d0
<=
rd_req_d0
;
rd_dat_d0
(
0
)
<=
fmc_adc_100ms_csr_i
.
trig_stat_ext
;
...
...
@@ -701,7 +706,7 @@ begin
rd_dat_d0
(
10
)
<=
fmc_adc_100ms_csr_i
.
trig_stat_ch3
;
rd_dat_d0
(
11
)
<=
fmc_adc_100ms_csr_i
.
trig_stat_ch4
;
rd_dat_d0
(
31
downto
12
)
<=
(
others
=>
'0'
);
when
"0
0
11"
=>
when
"011"
=>
-- Reg trig_en
rd_ack_d0
<=
rd_req_d0
;
rd_dat_d0
(
0
)
<=
trig_en_ext_reg
;
...
...
@@ -715,7 +720,7 @@ begin
rd_dat_d0
(
10
)
<=
trig_en_ch3_reg
;
rd_dat_d0
(
11
)
<=
trig_en_ch4_reg
;
rd_dat_d0
(
31
downto
12
)
<=
(
others
=>
'0'
);
when
"
0
100"
=>
when
"100"
=>
-- Reg trig_pol
rd_ack_d0
<=
rd_req_d0
;
rd_dat_d0
(
0
)
<=
trig_pol_ext_reg
;
...
...
@@ -725,65 +730,70 @@ begin
rd_dat_d0
(
10
)
<=
trig_pol_ch3_reg
;
rd_dat_d0
(
11
)
<=
trig_pol_ch4_reg
;
rd_dat_d0
(
31
downto
12
)
<=
(
others
=>
'0'
);
when
"
0
101"
=>
when
"101"
=>
-- Reg ext_trig_dly
rd_ack_d0
<=
rd_req_d0
;
rd_dat_d0
<=
ext_trig_dly_reg
;
when
"
0
110"
=>
when
"110"
=>
-- Reg sw_trig
rd_ack_d0
<=
rd_req_d0
;
when
"
0
111"
=>
when
"111"
=>
-- Reg shots
rd_ack_d0
<=
rd_req_d0
;
rd_dat_d0
(
15
downto
0
)
<=
shots_nbr_reg
;
rd_dat_d0
(
31
downto
16
)
<=
fmc_adc_100ms_csr_i
.
shots_remain
;
when
"1000"
=>
when
others
=>
rd_ack_d0
<=
rd_req_d0
;
end
case
;
when
"0001"
=>
case
rd_adr_d0
(
4
downto
2
)
is
when
"000"
=>
-- Reg multi_depth
rd_ack_d0
<=
rd_req_d0
;
rd_dat_d0
<=
fmc_adc_100ms_csr_i
.
multi_depth
;
when
"
1
001"
=>
when
"001"
=>
-- Reg trig_pos
rd_ack_d0
<=
rd_req_d0
;
rd_dat_d0
<=
fmc_adc_100ms_csr_i
.
trig_pos
;
when
"
1
010"
=>
when
"010"
=>
-- Reg fs_freq
rd_ack_d0
<=
rd_req_d0
;
rd_dat_d0
<=
fmc_adc_100ms_csr_i
.
fs_freq
;
when
"
1
011"
=>
when
"011"
=>
-- Reg downsample
rd_ack_d0
<=
rd_req_d0
;
rd_dat_d0
<=
downsample_reg
;
when
"1
1
00"
=>
when
"100"
=>
-- Reg pre_samples
rd_ack_d0
<=
rd_req_d0
;
rd_dat_d0
<=
pre_samples_reg
;
when
"1
1
01"
=>
when
"101"
=>
-- Reg post_samples
rd_ack_d0
<=
rd_req_d0
;
rd_dat_d0
<=
post_samples_reg
;
when
"11
1
0"
=>
when
"110"
=>
-- Reg samples_cnt
rd_ack_d0
<=
rd_req_d0
;
rd_dat_d0
<=
fmc_adc_100ms_csr_i
.
samples_cnt
;
when
others
=>
rd_ack_d0
<=
rd_req_d0
;
end
case
;
when
"010"
=>
when
"010
0
"
=>
-- Submap fmc_adc_ch1
fmc_adc_ch1_re
<=
rd_req_d0
;
rd_dat_d0
<=
fmc_adc_ch1_i
.
dat
;
rd_ack_d0
<=
fmc_adc_ch1_rack
;
when
"011"
=>
when
"011
0
"
=>
-- Submap fmc_adc_ch2
fmc_adc_ch2_re
<=
rd_req_d0
;
rd_dat_d0
<=
fmc_adc_ch2_i
.
dat
;
rd_ack_d0
<=
fmc_adc_ch2_rack
;
when
"100"
=>
when
"100
0
"
=>
-- Submap fmc_adc_ch3
fmc_adc_ch3_re
<=
rd_req_d0
;
rd_dat_d0
<=
fmc_adc_ch3_i
.
dat
;
rd_ack_d0
<=
fmc_adc_ch3_rack
;
when
"101"
=>
when
"101
0
"
=>
-- Submap fmc_adc_ch4
fmc_adc_ch4_re
<=
rd_req_d0
;
rd_dat_d0
<=
fmc_adc_ch4_i
.
dat
;
...
...
hdl/rtl/fmc_adc_100Ms_core.vhd
View file @
76513c14
...
...
@@ -223,13 +223,11 @@ architecture rtl of fmc_adc_100Ms_core is
signal
sync_calib_out
:
std_logic_vector
(
127
downto
0
);
signal
data_calibr_in
:
std_logic_vector
(
63
downto
0
);
signal
data_calibr_out
:
std_logic_vector
(
63
downto
0
);
signal
data_calibr_out_synced
:
std_logic_vector
(
63
downto
0
);
signal
data_calibr_out_d1
:
std_logic_vector
(
63
downto
0
);
signal
data_calibr_out_d2
:
std_logic_vector
(
63
downto
0
);
signal
data_calibr_out_d3
:
std_logic_vector
(
63
downto
0
);
signal
sat_val
:
std_logic_vector
(
59
downto
0
);
signal
sat_val_in
:
std_logic_vector
(
59
downto
0
);
signal
product_out
,
product_out_synced
:
std_logic_vector
(
17
*
4
-
1
downto
0
);
-- Acquisition FSM
signal
acq_fsm_current_state
:
t_acq_fsm_state
;
...
...
@@ -571,8 +569,6 @@ begin
channel_regin
(
I
)
.
calib_val_gain
<=
gain_calibr
(
I
*
16-1
downto
(
I
-1
)
*
16
);
channel_regin
(
I
)
.
calib_val_offset
<=
offset_calibr
(
I
*
16-1
downto
(
I
-1
)
*
16
);
channel_regin
(
I
)
.
sat_val_val
<=
sat_val
(
I
*
15-1
downto
(
I
-1
)
*
15
);
channel_regin
(
I
)
.
calib_sta_val
<=
data_calibr_out_synced
(
I
*
16-1
downto
(
I
-1
)
*
16
);
channel_regin
(
I
)
.
prod_sta_val
<=
product_out_synced
(
I
*
17-1
downto
(
I
-1
)
*
17
);
int_trig_delay_in
(
I
)
<=
channel_regout
(
I
)
.
trig_dly
;
int_trig_thres_in
(
I
)
<=
channel_regout
(
I
)
.
trig_thres_val
;
...
...
@@ -747,35 +743,10 @@ begin
gain_i
=>
gain_calibr
((
I
+
1
)
*
16-1
downto
I
*
16
),
sat_i
=>
sat_val
((
I
+
1
)
*
15-1
downto
I
*
15
),
data_i
=>
data_calibr_in
((
I
+
1
)
*
16-1
downto
I
*
16
),
data_o
=>
data_calibr_out
((
I
+
1
)
*
16-1
downto
I
*
16
),
product_o
=>
product_out
((
I
+
1
)
*
17-1
downto
I
*
17
)
data_o
=>
data_calibr_out
((
I
+
1
)
*
16-1
downto
I
*
16
)
);
end
generate
l_offset_gain_calibr
;
cmp_calib_sta_sync
:
gc_sync_word_wr
generic
map
(
g_AUTO_WR
=>
TRUE
,
g_WIDTH
=>
64
)
port
map
(
clk_in_i
=>
fs_clk
,
rst_in_n_i
=>
fs_rst_n
,
clk_out_i
=>
sys_clk_i
,
rst_out_n_i
=>
'1'
,
data_i
=>
data_calibr_out
,
data_o
=>
data_calibr_out_synced
);
cmp_prod_sta_sync
:
gc_sync_word_wr
generic
map
(
g_AUTO_WR
=>
TRUE
,
g_WIDTH
=>
17
*
4
)
port
map
(
clk_in_i
=>
fs_clk
,
rst_in_n_i
=>
fs_rst_n
,
clk_out_i
=>
sys_clk_i
,
rst_out_n_i
=>
'1'
,
data_i
=>
product_out
,
data_o
=>
product_out_synced
);
data_calibr_in
<=
serdes_out_data
;
------------------------------------------------------------------------------
...
...
hdl/rtl/offset_gain_s.vhd
View file @
76513c14
...
...
@@ -57,8 +57,7 @@ entity offset_gain_s is
gain_i
:
in
std_logic_vector
(
15
downto
0
);
--! Unsigned gain input
sat_i
:
in
std_logic_vector
(
14
downto
0
);
--! Unsigned saturation value input
data_i
:
in
std_logic_vector
(
15
downto
0
);
--! Signed data input (two's complement)
data_o
:
out
std_logic_vector
(
15
downto
0
);
--! Signed data output (two's complement)
product_o
:
out
std_logic_vector
(
16
downto
0
)
--! Signed intermediate output (two's complement)
data_o
:
out
std_logic_vector
(
15
downto
0
)
--! Signed data output (two's complement)
);
end
entity
offset_gain_s
;
...
...
@@ -145,8 +144,6 @@ begin
end
if
;
end
process
p_pipeline
;
product_o
<=
product
;
------------------------------------------------------------------------------
-- Saturate addition and multiplication result
------------------------------------------------------------------------------
...
...
hdl/testbench/include/fmc_adc_100Ms_channel_regs.v
View file @
76513c14
...
...
@@ -2,7 +2,7 @@
//
// SPDX-License-Identifier: CC0-1.0
`define
FMC_ADC_100MS_CHANNEL_REGS_SIZE
40
`define
FMC_ADC_100MS_CHANNEL_REGS_SIZE
32
`define
ADDR_FMC_ADC_100MS_CHANNEL_REGS_CTL
'
h0
`define
FMC_ADC_100MS_CHANNEL_REGS_CTL_SSR_OFFSET 0
`define
FMC_ADC_100MS_CHANNEL_REGS_CTL_SSR
'
h7f
...
...
@@ -31,9 +31,3 @@
`define
ADDR_FMC_ADC_100MS_CHANNEL_REGS_SAT_VAL
'
h1c
`define
FMC_ADC_100MS_CHANNEL_REGS_SAT_VAL_VAL_OFFSET 0
`define
FMC_ADC_100MS_CHANNEL_REGS_SAT_VAL_VAL
'
h7fff
`define
ADDR_FMC_ADC_100MS_CHANNEL_REGS_CALIB_STA
'
h20
`define
FMC_ADC_100MS_CHANNEL_REGS_CALIB_STA_VAL_OFFSET 0
`define
FMC_ADC_100MS_CHANNEL_REGS_CALIB_STA_VAL
'
hffff
`define
ADDR_FMC_ADC_100MS_CHANNEL_REGS_PROD_STA
'
h24
`define
FMC_ADC_100MS_CHANNEL_REGS_PROD_STA_VAL_OFFSET 0
`define
FMC_ADC_100MS_CHANNEL_REGS_PROD_STA_VAL
'
h1ffff
hdl/testbench/include/fmc_adc_100Ms_csr.v
View file @
76513c14
...
...
@@ -91,14 +91,14 @@
`define
ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES
'
h34
`define
ADDR_FMC_ADC_100MS_CSR_SAMPLES_CNT
'
h38
`define
ADDR_FMC_ADC_100MS_CSR_FMC_ADC_CH1
'
h80
`define
ADDR_MASK_FMC_ADC_100MS_CSR_FMC_ADC_CH1
'
h1
c
0
`define
FMC_ADC_100MS_CSR_FMC_ADC_CH1_SIZE
64
`define
ADDR_MASK_FMC_ADC_100MS_CSR_FMC_ADC_CH1
'
h1
e
0
`define
FMC_ADC_100MS_CSR_FMC_ADC_CH1_SIZE
32
`define
ADDR_FMC_ADC_100MS_CSR_FMC_ADC_CH2
'
hc0
`define
ADDR_MASK_FMC_ADC_100MS_CSR_FMC_ADC_CH2
'
h1
c
0
`define
FMC_ADC_100MS_CSR_FMC_ADC_CH2_SIZE
64
`define
ADDR_MASK_FMC_ADC_100MS_CSR_FMC_ADC_CH2
'
h1
e
0
`define
FMC_ADC_100MS_CSR_FMC_ADC_CH2_SIZE
32
`define
ADDR_FMC_ADC_100MS_CSR_FMC_ADC_CH3
'
h100
`define
ADDR_MASK_FMC_ADC_100MS_CSR_FMC_ADC_CH3
'
h1
c
0
`define
FMC_ADC_100MS_CSR_FMC_ADC_CH3_SIZE
64
`define
ADDR_MASK_FMC_ADC_100MS_CSR_FMC_ADC_CH3
'
h1
e
0
`define
FMC_ADC_100MS_CSR_FMC_ADC_CH3_SIZE
32
`define
ADDR_FMC_ADC_100MS_CSR_FMC_ADC_CH4
'
h140
`define
ADDR_MASK_FMC_ADC_100MS_CSR_FMC_ADC_CH4
'
h1
c
0
`define
FMC_ADC_100MS_CSR_FMC_ADC_CH4_SIZE
64
`define
ADDR_MASK_FMC_ADC_100MS_CSR_FMC_ADC_CH4
'
h1
e
0
`define
FMC_ADC_100MS_CSR_FMC_ADC_CH4_SIZE
32
software/include/hw/fmc_adc_100Ms_channel_regs.h
View file @
76513c14
#ifndef __CHEBY__FMC_ADC_100MS_CHANNEL_REGS__H__
#define __CHEBY__FMC_ADC_100MS_CHANNEL_REGS__H__
#define FMC_ADC_100MS_CHANNEL_REGS_SIZE
24
/* 0x18
*/
#define FMC_ADC_100MS_CHANNEL_REGS_SIZE
32
/* 0x20
*/
/* Channel control register */
#define FMC_ADC_100MS_CHANNEL_REGS_CTL 0x0UL
...
...
@@ -34,6 +34,18 @@
/* Channel trigger delay */
#define FMC_ADC_100MS_CHANNEL_REGS_TRIG_DLY 0x14UL
/* Channel calibration value (read from hw) */
#define FMC_ADC_100MS_CHANNEL_REGS_CALIB_VAL 0x18UL
#define FMC_ADC_100MS_CHANNEL_REGS_CALIB_VAL_GAIN_MASK 0xffffUL
#define FMC_ADC_100MS_CHANNEL_REGS_CALIB_VAL_GAIN_SHIFT 0
#define FMC_ADC_100MS_CHANNEL_REGS_CALIB_VAL_OFFSET_MASK 0xffff0000UL
#define FMC_ADC_100MS_CHANNEL_REGS_CALIB_VAL_OFFSET_SHIFT 16
/* Channel saturation register (read from hw) */
#define FMC_ADC_100MS_CHANNEL_REGS_SAT_VAL 0x1cUL
#define FMC_ADC_100MS_CHANNEL_REGS_SAT_VAL_VAL_MASK 0x7fffUL
#define FMC_ADC_100MS_CHANNEL_REGS_SAT_VAL_VAL_SHIFT 0
struct
fmc_adc_100ms_channel_regs
{
/* [0x0]: REG (rw) Channel control register */
uint32_t
ctl
;
...
...
@@ -52,6 +64,12 @@ struct fmc_adc_100ms_channel_regs {
/* [0x14]: REG (rw) Channel trigger delay */
uint32_t
trig_dly
;
/* [0x18]: REG (ro) Channel calibration value (read from hw) */
uint32_t
calib_val
;
/* [0x1c]: REG (ro) Channel saturation register (read from hw) */
uint32_t
sat_val
;
};
#endif
/* __CHEBY__FMC_ADC_100MS_CHANNEL_REGS__H__ */
software/include/hw/fmc_adc_100Ms_csr.h
View file @
76513c14
...
...
@@ -163,25 +163,25 @@ struct fmc_adc_100ms_csr {
struct
fmc_adc_100ms_channel_regs
fmc_adc_ch1
;
/* padding to: 48 words */
uint32_t
__padding_1
[
10
];
uint32_t
__padding_1
[
8
];
/* [0xc0]: SUBMAP Channel 2 registers */
struct
fmc_adc_100ms_channel_regs
fmc_adc_ch2
;
/* padding to: 64 words */
uint32_t
__padding_2
[
10
];
uint32_t
__padding_2
[
8
];
/* [0x100]: SUBMAP Channel 3 registers */
struct
fmc_adc_100ms_channel_regs
fmc_adc_ch3
;
/* padding to: 80 words */
uint32_t
__padding_3
[
10
];
uint32_t
__padding_3
[
8
];
/* [0x140]: SUBMAP Channel 4 registers */
struct
fmc_adc_100ms_channel_regs
fmc_adc_ch4
;
/* padding to: 80 words */
uint32_t
__padding_4
[
4
2
];
uint32_t
__padding_4
[
4
0
];
};
#endif
/* __CHEBY__FMC_ADC_100MS_CSR__H__ */
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment