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FMC ADC 100M 14b 4cha
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FMC ADC 100M 14b 4cha
Commits
66dde10f
Commit
66dde10f
authored
Nov 20, 2020
by
Federico Vaga
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Signed-off-by:
Federico Vaga
<
federico.vaga@cern.ch
>
parent
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327 additions
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7 deletions
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.gitignore
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.gitlab-ci.yml
.gitlab-ci.yml
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.gitmodules
.gitmodules
+4
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dep5
.reuse/dep5
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CHANGELOG.rst
CHANGELOG.rst
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Manifest.py
Manifest.py
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.gitignore
distribution/.gitignore
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Makefile
distribution/Makefile
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dkms.conf
distribution/dkms.conf
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fmc-adc-100m14b4ch.spec
distribution/fmc-adc-100m14b4ch.spec
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.gitignore
doc/.gitignore
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Makefile
doc/Makefile
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conf.py
doc/conf.py
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Makefile
doc/fig/Makefile
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Makefile
doc/gateware/regs/Makefile
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index.rst
doc/index.rst
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Makefile
doc/specs/Makefile
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adc100m14b4cha.tex
doc/specs/adc100m14b4cha.tex
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Makefile
hdl/cheby/Makefile
+4
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Manifest.py
hdl/platform/Manifest.py
+4
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Manifest.py
hdl/platform/xilinx/Manifest.py
+4
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Manifest.py
hdl/platform/xilinx/spartan6/Manifest.py
+4
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Manifest.py
hdl/rtl/Manifest.py
+4
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offset_gain_s.vhd
hdl/rtl/offset_gain_s.vhd
+1
-1
.gitignore
hdl/syn/spec150_ref_design_wr/.gitignore
+4
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Manifest.py
hdl/syn/spec150_ref_design_wr/Manifest.py
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spec_ref_fmc_adc_100Ms_wr.ucf
hdl/syn/spec150_ref_design_wr/spec_ref_fmc_adc_100Ms_wr.ucf
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syn_extra_steps.tcl
hdl/syn/spec150_ref_design_wr/syn_extra_steps.tcl
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hdl/syn/spec_ref_design_wr/.gitignore
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Manifest.py
hdl/syn/spec_ref_design_wr/Manifest.py
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spec_ref_fmc_adc_100Ms_wr.ucf
hdl/syn/spec_ref_design_wr/spec_ref_fmc_adc_100Ms_wr.ucf
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syn_extra_steps.tcl
hdl/syn/spec_ref_design_wr/syn_extra_steps.tcl
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hdl/syn/svec_ref_design_wr/.gitignore
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Manifest.py
hdl/syn/svec_ref_design_wr/Manifest.py
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svec_ref_fmc_adc_100Ms_wr.ucf
hdl/syn/svec_ref_design_wr/svec_ref_fmc_adc_100Ms_wr.ucf
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syn_extra_steps.tcl
hdl/syn/svec_ref_design_wr/syn_extra_steps.tcl
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Manifest.py
hdl/testbench/__deprecated/other/Manifest.py
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Manifest.py
...nch/__deprecated/other/sim_models/2048Mb_ddr3/Manifest.py
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Manifest.py
hdl/testbench/__deprecated/other/testbench/Manifest.py
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Manifest.py
hdl/testbench/__deprecated/spec/Manifest.py
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Manifest.py
hdl/testbench/__deprecated/spec/gn4124_bfm/Manifest.py
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Manifest.py
hdl/testbench/__deprecated/svec/2048Mb_ddr3/Manifest.py
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Manifest.py
hdl/testbench/__deprecated/svec/testbench/Manifest.py
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.gitignore
hdl/testbench/fmc_adc_mezzanine/.gitignore
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Manifest.py
hdl/testbench/fmc_adc_mezzanine/Manifest.py
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main.sv
hdl/testbench/fmc_adc_mezzanine/main.sv
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run.do
hdl/testbench/fmc_adc_mezzanine/run.do
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run_ci.do
hdl/testbench/fmc_adc_mezzanine/run_ci.do
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fmc_adc_100Ms_channel_regs.v
hdl/testbench/include/fmc_adc_100Ms_channel_regs.v
+4
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fmc_adc_100Ms_csr.v
hdl/testbench/include/fmc_adc_100Ms_csr.v
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fmc_adc_aux_trigin.v
hdl/testbench/include/fmc_adc_aux_trigin.v
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fmc_adc_aux_trigout.v
hdl/testbench/include/fmc_adc_aux_trigout.v
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fmc_adc_eic_regs.v
hdl/testbench/include/fmc_adc_eic_regs.v
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fmc_adc_mezzanine_mmap.v
hdl/testbench/include/fmc_adc_mezzanine_mmap.v
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spec_carrier_csr.v
hdl/testbench/include/spec_carrier_csr.v
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spec_ref_fmc_adc_100Ms_mmap.v
hdl/testbench/include/spec_ref_fmc_adc_100Ms_mmap.v
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svec_carrier_csr.v
hdl/testbench/include/svec_carrier_csr.v
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svec_ref_fmc_adc_100Ms_mmap.v
hdl/testbench/include/svec_ref_fmc_adc_100Ms_mmap.v
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timetag_core_regs.v
hdl/testbench/include/timetag_core_regs.v
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.gitignore
hdl/testbench/spec_ref_design/.gitignore
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Manifest.py
hdl/testbench/spec_ref_design/Manifest.py
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main.sv
hdl/testbench/spec_ref_design/main.sv
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run.do
hdl/testbench/spec_ref_design/run.do
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run_ci.do
hdl/testbench/spec_ref_design/run_ci.do
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wave.do
hdl/testbench/spec_ref_design/wave.do
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hdl/testbench/svec_ref_design/.gitignore
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Manifest.py
hdl/testbench/svec_ref_design/Manifest.py
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main.sv
hdl/testbench/svec_ref_design/main.sv
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run.do
hdl/testbench/svec_ref_design/run.do
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run_ci.do
hdl/testbench/svec_ref_design/run_ci.do
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Manifest.py
hdl/top/spec_ref_design/Manifest.py
+4
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Makefile
hdl/top/svec_ref_design/Makefile
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Manifest.py
hdl/top/svec_ref_design/Manifest.py
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.gitignore
software/.gitignore
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software/Makefile
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software/kernel/.gitignore
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Kbuild
software/kernel/Kbuild
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Makefile
software/kernel/Makefile
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fa-calibration.c
software/kernel/fa-calibration.c
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.gitignore
software/tools/.gitignore
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software/tools/Makefile
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fau-config-if
software/tools/fau-config-if
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No files found.
.gitignore
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66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
hdl/ip_cores/.lso
hdl/ip_cores/.lso
hdl/ip_cores/_xmsgs
hdl/ip_cores/_xmsgs
hdl/*/sim/*/transcript
hdl/*/sim/*/transcript
...
...
.gitlab-ci.yml
View file @
66dde10f
# SPDX-License-Identifier: CC0-1.0
#
# SPDX-FileCopyrightText: 2019 CERN
# SPDX-FileCopyrightText: 2019 CERN
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
---
---
variables
:
variables
:
...
...
.gitmodules
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
[submodule "hdl/ip_cores/general-cores"]
[submodule "hdl/ip_cores/general-cores"]
path = hdl/ip_cores/general-cores
path = hdl/ip_cores/general-cores
url = https://ohwr.org/project/general-cores.git
url = https://ohwr.org/project/general-cores.git
...
...
.reuse/dep5
0 → 100644
View file @
66dde10f
Format: https://www.debian.org/doc/packaging-manuals/copyright-format/1.0/
Upstream-Name: fmc-adc-100m14b4ch
Upstream-Contact: Jane Doe <jane@example.com>
Source: https://git.example.com/jane/my-project
Files: doc/img/* doc/fig/*
Copyright: 2020 CERN (home.cern)
License: CC-BY-SA-4.0
Files: doc/requirements.txt
Copyright: 2020 CERN (home.cern)
License: CC0-1.0
CHANGELOG.rst
View file @
66dde10f
..
SPDX-FileCopyrightText: 2020 CERN (home.cern)
SPDX-License-Identifier: CC0-1.0
=========
=========
Changelog
Changelog
=========
=========
...
...
Manifest.py
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
modules
=
{
modules
=
{
"local"
:
[
"local"
:
[
"hdl/rtl"
,
"hdl/rtl"
,
...
...
distribution/.gitignore
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
build/
build/
sources/
sources/
\ No newline at end of file
distribution/Makefile
View file @
66dde10f
# SPDX-License-Identifier: GPL-2.0-or-later
#
# Copyright (C) 2020 CERN
# Copyright (C) 2020 CERN
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
TOP_DIR
?=
$(
shell
pwd
)
/../
TOP_DIR
?=
$(
shell
pwd
)
/../
...
...
distribution/dkms.conf
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
PACKAGE_NAME
=
"@PKGNAME@"
PACKAGE_NAME
=
"@PKGNAME@"
PACKAGE_VERSION
=
"@PKGVER@"
PACKAGE_VERSION
=
"@PKGVER@"
CLEAN
=
"make KVERSION=$kernelver DKMSTREE=$dkms_tree DKMS=1 clean"
CLEAN
=
"make KVERSION=$kernelver DKMSTREE=$dkms_tree DKMS=1 clean"
...
...
distribution/fmc-adc-100m14b4ch.spec
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
# Mainline copied from the template, added requirements
# Mainline copied from the template, added requirements
name: fmc-adc-100m14b4ch
name: fmc-adc-100m14b4ch
...
...
doc/.gitignore
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
build_env
build_env
_build
_build
*.htm
*.htm
doc/Makefile
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
# Minimal makefile for Sphinx documentation
# Minimal makefile for Sphinx documentation
#
#
...
...
doc/conf.py
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
# Configuration file for the Sphinx documentation builder.
# Configuration file for the Sphinx documentation builder.
#
#
# This file only contains a selection of the most common options. For a full
# This file only contains a selection of the most common options. For a full
...
...
doc/fig/Makefile
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
SVG
=
$
(
wildcard
*
.svg
)
SVG
=
$
(
wildcard
*
.svg
)
PDF
=
$
(
SVG:.svg
=
.pdf
)
PDF
=
$
(
SVG:.svg
=
.pdf
)
...
...
doc/gateware/regs/Makefile
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
SOURCES
=
$
(
wildcard
*
.cheby
)
../../../hdl/cheby/fmc_adc_mezzanine_mmap.cheby
SOURCES
=
$
(
wildcard
*
.cheby
)
../../../hdl/cheby/fmc_adc_mezzanine_mmap.cheby
TARGETS
=
$
(
SOURCES:.cheby
=
.htm
)
TARGETS
=
$
(
SOURCES:.cheby
=
.htm
)
...
...
doc/index.rst
View file @
66dde10f
.. Copyright (c) 2013-2020 CERN (home.cern)
SPDX-License-Identifier: CC-BY-SA-4.0
.. FMC-ADC-100M-14B-4CHA documentation master file, created by
.. FMC-ADC-100M-14B-4CHA documentation master file, created by
sphinx-quickstart on Thu Aug 6 14:57:13 2020.
sphinx-quickstart on Thu Aug 6 14:57:13 2020.
You can adapt this file completely to your liking, but it should at least
You can adapt this file completely to your liking, but it should at least
...
...
doc/specs/Makefile
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
# Makefile for Latex work
# Makefile for Latex work
TEXFILE
=
adc100m14b4cha.tex
TEXFILE
=
adc100m14b4cha.tex
...
...
doc/specs/adc100m14b4cha.tex
View file @
66dde10f
% SPDX-FileCopyrightText: 2020 CERN (home.cern)
%
% SPDX-License-Identifier: CC-BY-SA-4.0
% This document specifies how our ADCs should be implemented
% This document specifies how our ADCs should be implemented
% using FMC cards and blocks of HDL in our PCIe carriers.
% using FMC cards and blocks of HDL in our PCIe carriers.
...
...
hdl/cheby/Makefile
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
SIM
=
../testbench/include
SIM
=
../testbench/include
SW
=
../../software/include/hw
SW
=
../../software/include/hw
...
...
hdl/platform/Manifest.py
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
if
target
==
"xilinx"
:
if
target
==
"xilinx"
:
modules
=
{
"local"
:
"xilinx"
}
modules
=
{
"local"
:
"xilinx"
}
hdl/platform/xilinx/Manifest.py
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
modules
=
{
modules
=
{
"local"
:
[
"local"
:
[
"spartan6"
,
"spartan6"
,
...
...
hdl/platform/xilinx/spartan6/Manifest.py
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
files
=
[
files
=
[
"ltc2174_2l16b_receiver.vhd"
,
"ltc2174_2l16b_receiver.vhd"
,
]
]
hdl/rtl/Manifest.py
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
files
=
[
files
=
[
"fmc_adc_mezzanine.vhd"
,
"fmc_adc_mezzanine.vhd"
,
"fmc_adc_mezzanine_pkg.vhd"
,
"fmc_adc_mezzanine_pkg.vhd"
,
...
...
hdl/rtl/offset_gain_s.vhd
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66dde10f
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- SPDX-FileCopyrightText: 2020 CERN (home.cern)
-- SPDX-License-Identifier: CERN-OHL-W-2.0
-- SPDX-License-Identifier: CERN-OHL-W-2.0
-- CERN (BE-CO-HT)
-- Offset and gain correction, signed data input and output (two's complement)
-- Offset and gain correction, signed data input and output (two's complement)
-- http://www.ohwr.org/projects/fmc-adc-100m14b4cha
-- http://www.ohwr.org/projects/fmc-adc-100m14b4cha
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
...
...
hdl/syn/spec150_ref_design_wr/.gitignore
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66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
*
*
!.gitignore
!.gitignore
!Manifest.py
!Manifest.py
...
...
hdl/syn/spec150_ref_design_wr/Manifest.py
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
board
=
"spec"
board
=
"spec"
target
=
"xilinx"
target
=
"xilinx"
action
=
"synthesis"
action
=
"synthesis"
...
...
hdl/syn/spec150_ref_design_wr/spec_ref_fmc_adc_100Ms_wr.ucf
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66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
#===============================================================================
#===============================================================================
# IO Constraints
# IO Constraints
#===============================================================================
#===============================================================================
...
...
hdl/syn/spec150_ref_design_wr/syn_extra_steps.tcl
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern
)
#
# SPDX-License-Identifier: CC0-1.0
# get project file from 1st command-line argument
# get project file from 1st command-line argument
set
project_file
[
lindex
$argv
0
]
set
project_file
[
lindex
$argv
0
]
...
...
hdl/syn/spec_ref_design_wr/.gitignore
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
*
*
!.gitignore
!.gitignore
!Manifest.py
!Manifest.py
...
...
hdl/syn/spec_ref_design_wr/Manifest.py
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
board
=
"spec"
board
=
"spec"
target
=
"xilinx"
target
=
"xilinx"
action
=
"synthesis"
action
=
"synthesis"
...
...
hdl/syn/spec_ref_design_wr/spec_ref_fmc_adc_100Ms_wr.ucf
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
#===============================================================================
#===============================================================================
# IO Constraints
# IO Constraints
#===============================================================================
#===============================================================================
...
...
hdl/syn/spec_ref_design_wr/syn_extra_steps.tcl
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern
)
#
# SPDX-License-Identifier: CC0-1.0
# get project file from 1st command-line argument
# get project file from 1st command-line argument
set
project_file
[
lindex
$argv
0
]
set
project_file
[
lindex
$argv
0
]
...
...
hdl/syn/svec_ref_design_wr/.gitignore
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
*
*
!.gitignore
!.gitignore
!Manifest.py
!Manifest.py
...
...
hdl/syn/svec_ref_design_wr/Manifest.py
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
board
=
"svec"
board
=
"svec"
target
=
"xilinx"
target
=
"xilinx"
action
=
"synthesis"
action
=
"synthesis"
...
...
hdl/syn/svec_ref_design_wr/svec_ref_fmc_adc_100Ms_wr.ucf
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
#===============================================================================
#===============================================================================
# IO Constraints
# IO Constraints
#===============================================================================
#===============================================================================
...
...
hdl/syn/svec_ref_design_wr/syn_extra_steps.tcl
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern
)
#
# SPDX-License-Identifier: CC0-1.0
# get project file from 1st command-line argument
# get project file from 1st command-line argument
set
project_file
[
lindex
$argv
0
]
set
project_file
[
lindex
$argv
0
]
...
...
hdl/testbench/__deprecated/other/Manifest.py
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
sim_tool
=
"modelsim"
sim_tool
=
"modelsim"
top_module
=
"main"
top_module
=
"main"
target
=
"xilinx"
target
=
"xilinx"
...
...
hdl/testbench/__deprecated/other/sim_models/2048Mb_ddr3/Manifest.py
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
files
=
[
"ddr3.v"
]
files
=
[
"ddr3.v"
]
vlog_opt
=
"+incdir+sim_models/2048Mb_ddr3 +define+sg15E +define+x16"
vlog_opt
=
"+incdir+sim_models/2048Mb_ddr3 +define+sg15E +define+x16"
hdl/testbench/__deprecated/other/testbench/Manifest.py
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
files
=
[
"mem_model.vhd"
]
files
=
[
"mem_model.vhd"
]
vcom_opt
=
"-87"
vcom_opt
=
"-87"
hdl/testbench/__deprecated/spec/Manifest.py
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
sim_tool
=
"modelsim"
sim_tool
=
"modelsim"
top_module
=
"main"
top_module
=
"main"
action
=
"simulation"
action
=
"simulation"
...
...
hdl/testbench/__deprecated/spec/gn4124_bfm/Manifest.py
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
files
=
[
"mem_model.vhd"
,
"textutil.vhd"
,
"gn412x_bfm.vhd"
,
"util.vhd"
]
files
=
[
"mem_model.vhd"
,
"textutil.vhd"
,
"gn412x_bfm.vhd"
,
"util.vhd"
]
hdl/testbench/__deprecated/svec/2048Mb_ddr3/Manifest.py
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
files
=
[
"ddr3.v"
]
files
=
[
"ddr3.v"
]
vlog_opt
=
"+define+sg15E +define+x16"
vlog_opt
=
"+define+sg15E +define+x16"
hdl/testbench/__deprecated/svec/testbench/Manifest.py
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
sim_tool
=
"modelsim"
sim_tool
=
"modelsim"
top_module
=
"main"
top_module
=
"main"
action
=
"simulation"
action
=
"simulation"
...
...
hdl/testbench/fmc_adc_mezzanine/.gitignore
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
Makefile
Makefile
work/
work/
transcript
transcript
...
...
hdl/testbench/fmc_adc_mezzanine/Manifest.py
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
board
=
"spec"
board
=
"spec"
sim_tool
=
"modelsim"
sim_tool
=
"modelsim"
top_module
=
"main"
top_module
=
"main"
...
...
hdl/testbench/fmc_adc_mezzanine/main.sv
View file @
66dde10f
// SPDX-FileCopyrightText: 2020 CERN (home.cern)
//
// SPDX-License-Identifier: CC0-1.0
`timescale
1
ns
/
1
ps
`timescale
1
ns
/
1
ps
`include
"vhd_wishbone_master.svh"
`include
"vhd_wishbone_master.svh"
...
...
hdl/testbench/fmc_adc_mezzanine/run.do
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
vsim -quiet -L unisim work.main -voptargs=+acc
vsim -quiet -L unisim work.main -voptargs=+acc
set StdArithNoWarnings 1
set StdArithNoWarnings 1
...
...
hdl/testbench/fmc_adc_mezzanine/run_ci.do
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
vsim -quiet -L unisim work.main
vsim -quiet -L unisim work.main
set StdArithNoWarnings 1
set StdArithNoWarnings 1
...
...
hdl/testbench/include/fmc_adc_100Ms_channel_regs.v
View file @
66dde10f
// SPDX-FileCopyrightText: 2020 CERN (home.cern)
//
// SPDX-License-Identifier: CC0-1.0
`define
FMC_ADC_100MS_CHANNEL_REGS_SIZE 24
`define
FMC_ADC_100MS_CHANNEL_REGS_SIZE 24
`define
ADDR_FMC_ADC_100MS_CHANNEL_REGS_CTL
'
h0
`define
ADDR_FMC_ADC_100MS_CHANNEL_REGS_CTL
'
h0
`define
FMC_ADC_100MS_CHANNEL_REGS_CTL_SSR_OFFSET 0
`define
FMC_ADC_100MS_CHANNEL_REGS_CTL_SSR_OFFSET 0
...
...
hdl/testbench/include/fmc_adc_100Ms_csr.v
View file @
66dde10f
// SPDX-FileCopyrightText: 2020 CERN (home.cern)
//
// SPDX-License-Identifier: CC0-1.0
`define
FMC_ADC_100MS_CSR_SIZE 512
`define
FMC_ADC_100MS_CSR_SIZE 512
`define
ADDR_FMC_ADC_100MS_CSR_CTL
'
h0
`define
ADDR_FMC_ADC_100MS_CSR_CTL
'
h0
`define
FMC_ADC_100MS_CSR_CTL_FSM_CMD_OFFSET 0
`define
FMC_ADC_100MS_CSR_CTL_FSM_CMD_OFFSET 0
...
...
hdl/testbench/include/fmc_adc_aux_trigin.v
View file @
66dde10f
// SPDX-FileCopyrightText: 2020 CERN (home.cern)
//
// SPDX-License-Identifier: CC0-1.0
`define
AUX_TRIGIN_SIZE 20
`define
AUX_TRIGIN_SIZE 20
`define
ADDR_AUX_TRIGIN_VERSION
'
h0
`define
ADDR_AUX_TRIGIN_VERSION
'
h0
`define
AUX_TRIGIN_VERSION_PRESET
'
hadc10001
`define
AUX_TRIGIN_VERSION_PRESET
'
hadc10001
...
...
hdl/testbench/include/fmc_adc_aux_trigout.v
View file @
66dde10f
// SPDX-FileCopyrightText: 2020 CERN (home.cern)
//
// SPDX-License-Identifier: CC0-1.0
`define
AUX_TRIGOUT_SIZE 20
`define
AUX_TRIGOUT_SIZE 20
`define
ADDR_AUX_TRIGOUT_STATUS
'
h0
`define
ADDR_AUX_TRIGOUT_STATUS
'
h0
`define
AUX_TRIGOUT_WR_ENABLE_OFFSET 0
`define
AUX_TRIGOUT_WR_ENABLE_OFFSET 0
...
...
hdl/testbench/include/fmc_adc_eic_regs.v
View file @
66dde10f
// SPDX-FileCopyrightText: 2020 CERN (home.cern)
//
// SPDX-License-Identifier: CC0-1.0
`define
FMC_ADC_EIC_REGS_SIZE 16
`define
FMC_ADC_EIC_REGS_SIZE 16
`define
ADDR_FMC_ADC_EIC_REGS_IDR
'
h0
`define
ADDR_FMC_ADC_EIC_REGS_IDR
'
h0
`define
ADDR_FMC_ADC_EIC_REGS_IER
'
h4
`define
ADDR_FMC_ADC_EIC_REGS_IER
'
h4
...
...
hdl/testbench/include/fmc_adc_mezzanine_mmap.v
View file @
66dde10f
// SPDX-FileCopyrightText: 2020 CERN (home.cern)
//
// SPDX-License-Identifier: CC0-1.0
`define
FMC_ADC_MEZZANINE_MMAP_SIZE 8192
`define
FMC_ADC_MEZZANINE_MMAP_SIZE 8192
`define
ADDR_FMC_ADC_MEZZANINE_MMAP_FMC_ADC_100M_CSR
'
h1000
`define
ADDR_FMC_ADC_MEZZANINE_MMAP_FMC_ADC_100M_CSR
'
h1000
`define
FMC_ADC_MEZZANINE_MMAP_FMC_ADC_100M_CSR_SIZE 512
`define
FMC_ADC_MEZZANINE_MMAP_FMC_ADC_100M_CSR_SIZE 512
...
...
hdl/testbench/include/spec_carrier_csr.v
View file @
66dde10f
// SPDX-FileCopyrightText: 2020 CERN (home.cern)
//
// SPDX-License-Identifier: CC0-1.0
`define
SPEC_CARRIER_CSR_SIZE 16
`define
SPEC_CARRIER_CSR_SIZE 16
`define
ADDR_SPEC_CARRIER_CSR_CARRIER
'
h0
`define
ADDR_SPEC_CARRIER_CSR_CARRIER
'
h0
`define
SPEC_CARRIER_CSR_CARRIER_PCB_REV_OFFSET 0
`define
SPEC_CARRIER_CSR_CARRIER_PCB_REV_OFFSET 0
...
...
hdl/testbench/include/spec_ref_fmc_adc_100Ms_mmap.v
View file @
66dde10f
// SPDX-FileCopyrightText: 2020 CERN (home.cern)
//
// SPDX-License-Identifier: CC0-1.0
`define
SPEC_REF_FMC_ADC_100M_MMAP_SIZE 24576
`define
SPEC_REF_FMC_ADC_100M_MMAP_SIZE 24576
`define
ADDR_SPEC_REF_FMC_ADC_100M_MMAP_METADATA
'
h2000
`define
ADDR_SPEC_REF_FMC_ADC_100M_MMAP_METADATA
'
h2000
`define
SPEC_REF_FMC_ADC_100M_MMAP_METADATA_SIZE 64
`define
SPEC_REF_FMC_ADC_100M_MMAP_METADATA_SIZE 64
...
...
hdl/testbench/include/svec_carrier_csr.v
View file @
66dde10f
// SPDX-FileCopyrightText: 2020 CERN (home.cern)
//
// SPDX-License-Identifier: CC0-1.0
`define
SVEC_CARRIER_CSR_SIZE 16
`define
SVEC_CARRIER_CSR_SIZE 16
`define
ADDR_SVEC_CARRIER_CSR_CARRIER
'
h0
`define
ADDR_SVEC_CARRIER_CSR_CARRIER
'
h0
`define
SVEC_CARRIER_CSR_CARRIER_PCB_REV_OFFSET 0
`define
SVEC_CARRIER_CSR_CARRIER_PCB_REV_OFFSET 0
...
...
hdl/testbench/include/svec_ref_fmc_adc_100Ms_mmap.v
View file @
66dde10f
// SPDX-FileCopyrightText: 2020 CERN (home.cern)
//
// SPDX-License-Identifier: CC0-1.0
`define
SVEC_REF_FMC_ADC_100M_MMAP_SIZE 32768
`define
SVEC_REF_FMC_ADC_100M_MMAP_SIZE 32768
`define
ADDR_SVEC_REF_FMC_ADC_100M_MMAP_METADATA
'
h2000
`define
ADDR_SVEC_REF_FMC_ADC_100M_MMAP_METADATA
'
h2000
`define
SVEC_REF_FMC_ADC_100M_MMAP_METADATA_SIZE 64
`define
SVEC_REF_FMC_ADC_100M_MMAP_METADATA_SIZE 64
...
...
hdl/testbench/include/timetag_core_regs.v
View file @
66dde10f
// SPDX-FileCopyrightText: 2020 CERN (home.cern)
//
// SPDX-License-Identifier: CC0-1.0
`define
TIMETAG_CORE_REGS_SIZE 128
`define
TIMETAG_CORE_REGS_SIZE 128
`define
ADDR_TIMETAG_CORE_REGS_SECONDS_UPPER
'
h0
`define
ADDR_TIMETAG_CORE_REGS_SECONDS_UPPER
'
h0
`define
TIMETAG_CORE_REGS_SECONDS_UPPER_OFFSET 0
`define
TIMETAG_CORE_REGS_SECONDS_UPPER_OFFSET 0
...
...
hdl/testbench/spec_ref_design/.gitignore
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
Makefile
Makefile
work/
work/
transcript
transcript
...
...
hdl/testbench/spec_ref_design/Manifest.py
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
board
=
"spec"
board
=
"spec"
sim_tool
=
"modelsim"
sim_tool
=
"modelsim"
sim_top
=
"main"
sim_top
=
"main"
...
...
hdl/testbench/spec_ref_design/main.sv
View file @
66dde10f
// SPDX-FileCopyrightText: 2020 CERN (home.cern)
//
// SPDX-License-Identifier: CC0-1.0
`timescale
1
ns
/
1
ps
`timescale
1
ns
/
1
ps
`include
"gn4124_bfm.svh"
`include
"gn4124_bfm.svh"
...
...
hdl/testbench/spec_ref_design/run.do
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
vsim -quiet -t 10fs -L unisim work.main -voptargs=+acc -suppress 143,1270,8617,8683,8684,8822
vsim -quiet -t 10fs -L unisim work.main -voptargs=+acc -suppress 143,1270,8617,8683,8684,8822
set StdArithNoWarnings 1
set StdArithNoWarnings 1
...
...
hdl/testbench/spec_ref_design/run_ci.do
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
vsim -quiet -t 10fs -L unisim work.main -suppress 1270,8617,8683,8684,8822
vsim -quiet -t 10fs -L unisim work.main -suppress 1270,8617,8683,8684,8822
set StdArithNoWarnings 1
set StdArithNoWarnings 1
...
...
hdl/testbench/spec_ref_design/wave.do
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
onerror {resume}
onerror {resume}
quietly WaveActivateNextPane {} 0
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/DUT/cmp_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/acq_fsm_current_state
add wave -noupdate /main/DUT/cmp_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/acq_fsm_current_state
...
...
hdl/testbench/svec_ref_design/.gitignore
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
Makefile
Makefile
work/
work/
transcript
transcript
...
...
hdl/testbench/svec_ref_design/Manifest.py
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
board
=
"svec"
board
=
"svec"
sim_tool
=
"modelsim"
sim_tool
=
"modelsim"
sim_top
=
"main"
sim_top
=
"main"
...
...
hdl/testbench/svec_ref_design/main.sv
View file @
66dde10f
// SPDX-FileCopyrightText: 2020 CERN (home.cern)
//
// SPDX-License-Identifier: CC0-1.0
`timescale
1
ns
/
1
ps
`timescale
1
ns
/
1
ps
`include
"vme64x_bfm.svh"
`include
"vme64x_bfm.svh"
...
...
hdl/testbench/svec_ref_design/run.do
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
vsim -quiet -t 10fs -L unisim work.main -voptargs=+acc -suppress 143,1270,8617,8683,8684,8822
vsim -quiet -t 10fs -L unisim work.main -voptargs=+acc -suppress 143,1270,8617,8683,8684,8822
set StdArithNoWarnings 1
set StdArithNoWarnings 1
...
...
hdl/testbench/svec_ref_design/run_ci.do
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
vsim -quiet -t 10fs -L unisim work.main -suppress 1270,8617,8683,8684,8822
vsim -quiet -t 10fs -L unisim work.main -suppress 1270,8617,8683,8684,8822
set StdArithNoWarnings 1
set StdArithNoWarnings 1
...
...
hdl/top/spec_ref_design/Manifest.py
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
files
=
[
files
=
[
"spec_ref_fmc_adc_100Ms.vhd"
,
"spec_ref_fmc_adc_100Ms.vhd"
,
"../../cheby/spec_ref_fmc_adc_100Ms_mmap.vhd"
,
"../../cheby/spec_ref_fmc_adc_100Ms_mmap.vhd"
,
...
...
hdl/top/svec_ref_design/Makefile
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
SIM
=
../../testbench/include
SIM
=
../../testbench/include
DOC
=
../../../doc/manual
DOC
=
../../../doc/manual
SW
=
../../../software/include/hw
SW
=
../../../software/include/hw
...
...
hdl/top/svec_ref_design/Manifest.py
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
files
=
[
files
=
[
"svec_ref_fmc_adc_100Ms.vhd"
,
"svec_ref_fmc_adc_100Ms.vhd"
,
"../../cheby/svec_ref_fmc_adc_100Ms_mmap.vhd"
,
"../../cheby/svec_ref_fmc_adc_100Ms_mmap.vhd"
,
...
...
software/.gitignore
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
compile_commands.json
compile_commands.json
software/Makefile
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
# include parent_common.mk for buildsystem's defines
# include parent_common.mk for buildsystem's defines
# use absolute path for REPO_PARENT
# use absolute path for REPO_PARENT
-include
$(REPO_PARENT)/parent_common.mk
-include
$(REPO_PARENT)/parent_common.mk
...
...
software/kernel/.gitignore
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
fmc-bus-link
fmc-bus-link
software/kernel/Kbuild
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
CONFIG_FMC_ADC_SVEC ?= CONFIG_VME
CONFIG_FMC_ADC_SVEC ?= CONFIG_VME
VMEBUS_EXTRA_SYMBOLS-$(CONFIG_FMC_ADC_SVEC) := $(VMEBUS_ABS)/driver/Module.symvers
VMEBUS_EXTRA_SYMBOLS-$(CONFIG_FMC_ADC_SVEC) := $(VMEBUS_ABS)/driver/Module.symvers
...
...
software/kernel/Makefile
View file @
66dde10f
# SPDX-License-Identifier: GPL-2.0-or-later
#
# Copyright (C) 2019 CERN
# Copyright (C) 2019 CERN
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
-include
Makefile.specific
-include
Makefile.specific
# include parent_common.mk for buildsystem's defines
# include parent_common.mk for buildsystem's defines
...
...
software/kernel/fa-calibration.c
View file @
66dde10f
// SPDX-FileCopyrightText: 2020 CERN (home.cern)
//
// SPDX-License-Identifier: GPL-2.0-or-later
// SPDX-License-Identifier: GPL-2.0-or-later
/*
/*
...
...
software/tools/.gitignore
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
fau-acq-time
fau-acq-time
fau-trg-config
fau-trg-config
fau-calibration
fau-calibration
...
...
software/tools/Makefile
View file @
66dde10f
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
# If it exists includes Makefile.specific. In this Makefile, you should put
# If it exists includes Makefile.specific. In this Makefile, you should put
# specific Makefile code that you want to run before this. For example,
# specific Makefile code that you want to run before this. For example,
# build a particular environment.
# build a particular environment.
...
...
software/tools/fau-config-if
View file @
66dde10f
#!/usr/bin/wish
#!/usr/bin/wish
# SPDX-FileCopyrightText: 2020 CERN (home.cern
)
#
# SPDX-License-Identifier: GPL-3.0-or-later
set
base
"/sys/bus/zio/devices/adc-100m14b-"
set
base
"/sys/bus/zio/devices/adc-100m14b-"
# We trace the "v" (values
)
array to write to sysfs
# We trace the "v" (values
)
array to write to sysfs
...
...
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