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FMC ADC 100M 14b 4cha
Commit 45de4903 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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doc: update information on HDL clock domains. 

Signed-off-by: Dimitris Lampridis's avatarDimitris Lampridis <dimitris.lampridis@cern.ch>
parent 77320acb
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doc/gateware/index.rst
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...@@ -103,12 +103,21 @@ There are two different Wishbone bus interconnects in the design. ...@@ -103,12 +103,21 @@ There are two different Wishbone bus interconnects in the design.
Mapped WB bus (blue) Mapped WB bus (blue)
This bus connects all the peripherals to the GN4142 core. This bus connects all the peripherals to the GN4142 core.
Data: 32-bit, address: 32-bit (word aligned), clock: system clock (125MHz). Data: 32-bit, address: 32-bit (word aligned),
Clock: system clock (125MHz) and system clock / 2 (62.5MHz), see note below.
ADC core to memory controller (orange) ADC core to memory controller (orange)
This bus is used to write samples from the ADC core to the DDR memory. This bus is used to write samples from the ADC core to the DDR memory.
Data: 64-bit, address: 32-bit (word aligned), clock: system clock (125MHz). Data: 64-bit, address: 32-bit (word aligned), clock: system clock (125MHz).
.. note::
The SPEC-base core works internally at 62.5MHz, especially for the WR PTP
core. On the other hand, the ADC core needs to work at 125MHz in order to
be able to retrieve and process the incoming ADC samples at 100MHz (from
the ``fs_clk`` domain). Therefore, a Wishbone clock crossing component is
inserted between the SPEC-base core and the ADC core. With this topology,
only the SPEC-base core runs at a lower frequency.
Note that some of the cores from the `General Cores`_ library are Note that some of the cores from the `General Cores`_ library are
based on cores from `OpenCores`_. Therefore, the documentation for based on cores from `OpenCores`_. Therefore, the documentation for
those cores is hosted on the OpenCores website. those cores is hosted on the OpenCores website.
...@@ -116,28 +125,31 @@ those cores is hosted on the OpenCores website. ...@@ -116,28 +125,31 @@ those cores is hosted on the OpenCores website.
Clock Domains Clock Domains
~~~~~~~~~~~~~ ~~~~~~~~~~~~~
The SPEC version of the fmc-adc design has five different clock domains. The SPEC version of the fmc-adc design has six different clock domains.
They are listed in the following table. They are listed in the following table.
+-----------------+-----------------+-----------------+-----------------+ +------------------+-----------------+-----------------+-----------------+
| Name | Description | Frequency | Source | | Name | Description | Frequency | Source |
+=================+=================+=================+=================+ +==================+=================+=================+=================+
| ``sys_clk_125`` | Main system | 125.00 MHz | 20MHz TCXO | | ``clk_ref_125m`` | Main system | 125.00 MHz | 125MHz VCXO |
| | clock | | (carrier) | | | clock | | (carrier) |
+-----------------+-----------------+-----------------+-----------------+ +------------------+-----------------+-----------------+-----------------+
| ``ddr_clk`` | DDR interface | 333.33 MHz | 20MHz TCXO | | ``clk_sys_62m5`` | System clock | 62.50 MHz | 125MHz VCXO |
| | clock | | (carrier) | | | for spec-base | | (carrier) |
+-----------------+-----------------+-----------------+-----------------+ +------------------+-----------------+-----------------+-----------------+
| ``fs_clk`` | Sampling clock | 100.00 MHz | 400MHz LTC2174 | | ``clk_333m_ddr`` | DDR interface | 333.33 MHz | 125MHz VCXO |
| | | | (mezzanine) | | | clock | | (carrier) |
+-----------------+-----------------+-----------------+-----------------+ +------------------+-----------------+-----------------+-----------------+
| ``serdes_clk`` | ADC data | 800.00 MHz | 400MHz LTC2174 | | ``fs_clk`` | Sampling clock | 100.00 MHz | 400MHz LTC2174 |
| | de-serialiser | | (mezzanine) | | | | | (mezzanine) |
| | clock | | | +------------------+-----------------+-----------------+-----------------+
+-----------------+-----------------+-----------------+-----------------+ | ``adc_dco`` | ADC data | 800.00 MHz | 400MHz LTC2174 |
| ``p2l_clk`` | Local bus clock | 200.00 MHz | 200MHz GN4124 | | | de-serialiser | | (mezzanine) |
| | | | (carrier) | | | clock | | |
+-----------------+-----------------+-----------------+-----------------+ +------------------+-----------------+-----------------+-----------------+
| ``p2l_clk`` | PCI to Local | 200.00 MHz | 200MHz GN4124 |
| | bus clock | | (carrier) |
+------------------+-----------------+-----------------+-----------------+
SVEC (VME64x carrier) SVEC (VME64x carrier)
--------------------- ---------------------
...@@ -167,39 +179,49 @@ ADC cores to memory controllers (2x, orange) ...@@ -167,39 +179,49 @@ ADC cores to memory controllers (2x, orange)
Data: 64-bit, address: 32-bit (word aligned), clock: system clock (125MHz). Data: 64-bit, address: 32-bit (word aligned), clock: system clock (125MHz).
.. note:: .. note::
The VME64x core cannot work with a clock frequency as high as The SVEC-base core works internally at 62.5MHz, especially for the WR PTP
125MHz, therefore it is clocked with half the system clock core. On the other hand, the ADC core needs to work at 125MHz in order to
frequency. As the fmc-adc core needs 125MHz to work properly, a be able to retrieve and process the incoming ADC samples at 100MHz (from
Wishbone clock crossing component is inserted between the VME64x core the ``fs_clk`` domain). Therefore, a Wishbone clock crossing component is
and the first Wishbone crossbar component. With this topology, only inserted between the SVEC-base core and the ADC core. With this topology,
the VME64x core runs at a lower frequency. only the SVEC-base core runs at a lower frequency.
Note that some of the cores from the `General Cores`_ library are
based on cores from `OpenCores`_. Therefore, the documentation for
those cores is hosted on the OpenCores website.
Clock Domains Clock Domains
~~~~~~~~~~~~~ ~~~~~~~~~~~~~
The SVEC version of the fmc-adc design has five different clock domains. The SVEC version of the fmc-adc design has seven different clock domains.
They are listed in the following table. They are listed in the following table.
+-----------------+-----------------+-----------------+-----------------+ +------------------+-----------------+-----------------+-----------------+
| Name | Description | Frequency | Source | | Name | Description | Frequency | Source |
+=================+=================+=================+=================+ +==================+=================+=================+=================+
| sys_clk_125 | Main system | 125.00 MHz | 20MHz TCXO | | ``clk_ref_125m`` | Main system | 125.00 MHz | 125MHz VCXO |
| | clock | | (carrier) | | | clock | | (carrier) |
+-----------------+-----------------+-----------------+-----------------+ +------------------+-----------------+-----------------+-----------------+
| sys_clk_62_5 | System clock / | 62.50 MHz | 20MHz TCXO | | ``clk_sys_62m5`` | System clock | 62.50 MHz | 125MHz VCXO |
| | 2 | | (carrier) | | | for spec-base | | (carrier) |
+-----------------+-----------------+-----------------+-----------------+ +------------------+-----------------+-----------------+-----------------+
| ddr_clk | DDR interface | 333.33 MHz | 20MHz TCXO | | ``clk_ddr_333m`` | DDR interface | 333.33 MHz | 125MHz VCXO |
| | clock | | (carrier) | | | clock | | (carrier) |
+-----------------+-----------------+-----------------+-----------------+ +------------------+-----------------+-----------------+-----------------+
| fs_clk | Sampling clock | 100.00 MHz | 400MHz LTC2174 | | ``fs_clk1`` | Sampling clock | 100.00 MHz | 400MHz LTC2174 |
| | | | (mezzanine) | | | | | (mezzanine #1) |
+-----------------+-----------------+-----------------+-----------------+ +------------------+-----------------+-----------------+-----------------+
| serdes_clk | ADC data | 800.00 MHz | 400MHz LTC2174 | | ``adc_dco1`` | ADC data | 800.00 MHz | 400MHz LTC2174 |
| | de-serialiser | | (mezzanine) | | | de-serialiser | | (mezzanine #1) |
| | clock | | | | | clock | | |
+-----------------+-----------------+-----------------+-----------------+ +------------------+-----------------+-----------------+-----------------+
| ``fs_clk2`` | Sampling clock | 100.00 MHz | 400MHz LTC2174 |
| | | | (mezzanine #2) |
+------------------+-----------------+-----------------+-----------------+
| ``adc_dco2`` | ADC data | 800.00 MHz | 400MHz LTC2174 |
| | de-serialiser | | (mezzanine #2) |
| | clock | | |
+------------------+-----------------+-----------------+-----------------+
Common Cores Common Cores
------------ ------------
......
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