Skip to content

F
FMC ADC 100M 14b 4cha
Commit 440df6d9 authored by Dimitris Lampridis's avatar Dimitris Lampridis
Browse files
Options

migrate SPEC REF CSR to Cheby

parent dabad887
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 900 additions and 2109 deletions
doc/manual/spec_carrier_csr.html 0 → 100644
View file @ 440df6d9
This diff is collapsed.
hdl/testbench/include/spec_carrier_csr.v 0 → 100644
View file @ 440df6d9
`define SPEC_CARRIER_CSR_SIZE 16
`define ADDR_SPEC_CARRIER_CSR_CARRIER 'h0
`define SPEC_CARRIER_CSR_CARRIER_PCB_REV_OFFSET 0
`define SPEC_CARRIER_CSR_CARRIER_PCB_REV 'hf
`define SPEC_CARRIER_CSR_CARRIER_RESERVED_OFFSET 4
`define SPEC_CARRIER_CSR_CARRIER_RESERVED 'hfff0
`define SPEC_CARRIER_CSR_CARRIER_TYPE_OFFSET 16
`define SPEC_CARRIER_CSR_CARRIER_TYPE 'hffff0000
`define ADDR_SPEC_CARRIER_CSR_STAT 'h4
`define SPEC_CARRIER_CSR_STAT_FMC_PRES_OFFSET 0
`define SPEC_CARRIER_CSR_STAT_FMC_PRES 'h1
`define SPEC_CARRIER_CSR_STAT_P2L_PLL_LCK_OFFSET 1
`define SPEC_CARRIER_CSR_STAT_P2L_PLL_LCK 'h2
`define SPEC_CARRIER_CSR_STAT_SYS_PLL_LCK_OFFSET 2
`define SPEC_CARRIER_CSR_STAT_SYS_PLL_LCK 'h4
`define SPEC_CARRIER_CSR_STAT_DDR3_CAL_DONE_OFFSET 3
`define SPEC_CARRIER_CSR_STAT_DDR3_CAL_DONE 'h8
`define ADDR_SPEC_CARRIER_CSR_CTRL 'h8
`define SPEC_CARRIER_CSR_CTRL_LED_GREEN_OFFSET 0
`define SPEC_CARRIER_CSR_CTRL_LED_GREEN 'h1
`define SPEC_CARRIER_CSR_CTRL_LED_RED_OFFSET 1
`define SPEC_CARRIER_CSR_CTRL_LED_RED 'h2
`define ADDR_SPEC_CARRIER_CSR_RST 'hc
`define SPEC_CARRIER_CSR_RST_FMC0_OFFSET 0
`define SPEC_CARRIER_CSR_RST_FMC0 'h1
hdl/top/spec_ref_design/Makefile 0 → 100644
View file @ 440df6d9
SIM =../../testbench/include
DOC =../../../doc/manual
SW =../../../software/include/hw
SOURCES = $(wildcard *.cheby)
TARGETS = $(SOURCES:.cheby=.vhd)
all: $(TARGETS)
.PHONY: $(TARGETS)
$(TARGETS): %.vhd : %.cheby
@echo "\n\033[34m\033[1m-> Processing file $<\033[0m"
@cheby -i $< --gen-hdl=$@
@cheby -i $< \
--gen-doc=$(DOC)/$(@:.vhd=.html) \
--gen-consts=$(SIM)/$(@:.vhd=.v) \
--gen-c=$(SW)/$(@:.vhd=.h)
hdl/top/spec_ref_design/Manifest.py
View file @ 440df6d9
files = [
"spec_ref_fmc_adc_100Ms.vhd",
"carrier_csr.vhd",
"carrier_csr_wbgen2_pkg.vhd",
"spec_carrier_csr.vhd",
"dma_eic.vhd",
]
......
hdl/top/spec_ref_design/carrier_csr.vhd deleted 100644 → 0
View file @ dabad887
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Carrier control and status registers
---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Mon Feb 26 15:24:45 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.carrier_csr_wbgen2_pkg.all;
entity carrier_csr is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
regs_i : in t_carrier_csr_in_registers;
regs_o : out t_carrier_csr_out_registers
);
end carrier_csr;
architecture syn of carrier_csr is
signal carrier_csr_ctrl_led_green_int : std_logic ;
signal carrier_csr_ctrl_led_red_int : std_logic ;
signal carrier_csr_ctrl_dac_clr_n_int : std_logic ;
signal carrier_csr_rst_fmc0_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
begin
-- Some internal signals assignments
wrdata_reg <= wb_dat_i;
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
carrier_csr_ctrl_led_green_int <= '0';
carrier_csr_ctrl_led_red_int <= '0';
carrier_csr_ctrl_dac_clr_n_int <= '0';
carrier_csr_rst_fmc0_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
end if;
rddata_reg(3 downto 0) <= regs_i.carrier_pcb_rev_i;
rddata_reg(15 downto 4) <= regs_i.carrier_reserved_i;
rddata_reg(31 downto 16) <= regs_i.carrier_type_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= regs_i.stat_fmc_pres_i;
rddata_reg(1) <= regs_i.stat_p2l_pll_lck_i;
rddata_reg(2) <= regs_i.stat_sys_pll_lck_i;
rddata_reg(3) <= regs_i.stat_ddr3_cal_done_i;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
carrier_csr_ctrl_led_green_int <= wrdata_reg(0);
carrier_csr_ctrl_led_red_int <= wrdata_reg(1);
carrier_csr_ctrl_dac_clr_n_int <= wrdata_reg(2);
end if;
rddata_reg(0) <= carrier_csr_ctrl_led_green_int;
rddata_reg(1) <= carrier_csr_ctrl_led_red_int;
rddata_reg(2) <= carrier_csr_ctrl_dac_clr_n_int;
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11" =>
if (wb_we_i = '1') then
carrier_csr_rst_fmc0_int <= wrdata_reg(0);
end if;
rddata_reg(0) <= carrier_csr_rst_fmc0_int;
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- PCB revision
-- Reserved register
-- Carrier type
-- FMC presence
-- GN4142 core P2L PLL status
-- System clock PLL status
-- DDR3 calibration status
-- Green LED
regs_o.ctrl_led_green_o <= carrier_csr_ctrl_led_green_int;
-- Red LED
regs_o.ctrl_led_red_o <= carrier_csr_ctrl_led_red_int;
-- DAC clear
regs_o.ctrl_dac_clr_n_o <= carrier_csr_ctrl_dac_clr_n_int;
-- State of the reset line
regs_o.rst_fmc0_o <= carrier_csr_rst_fmc0_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/top/spec_ref_design/carrier_csr_wbgen2_pkg.vhd deleted 100644 → 0
View file @ dabad887
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Carrier control and status registers
---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Mon Feb 26 15:24:45 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package carrier_csr_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_carrier_csr_in_registers is record
carrier_pcb_rev_i : std_logic_vector(3 downto 0);
carrier_reserved_i : std_logic_vector(11 downto 0);
carrier_type_i : std_logic_vector(15 downto 0);
stat_fmc_pres_i : std_logic;
stat_p2l_pll_lck_i : std_logic;
stat_sys_pll_lck_i : std_logic;
stat_ddr3_cal_done_i : std_logic;
end record;
constant c_carrier_csr_in_registers_init_value: t_carrier_csr_in_registers := (
carrier_pcb_rev_i => (others => '0'),
carrier_reserved_i => (others => '0'),
carrier_type_i => (others => '0'),
stat_fmc_pres_i => '0',
stat_p2l_pll_lck_i => '0',
stat_sys_pll_lck_i => '0',
stat_ddr3_cal_done_i => '0'
);
-- Output registers (WB slave -> user design)
type t_carrier_csr_out_registers is record
ctrl_led_green_o : std_logic;
ctrl_led_red_o : std_logic;
ctrl_dac_clr_n_o : std_logic;
rst_fmc0_o : std_logic;
end record;
constant c_carrier_csr_out_registers_init_value: t_carrier_csr_out_registers := (
ctrl_led_green_o => '0',
ctrl_led_red_o => '0',
ctrl_dac_clr_n_o => '0',
rst_fmc0_o => '0'
);
function "or" (left, right: t_carrier_csr_in_registers) return t_carrier_csr_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body carrier_csr_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if x(i) = '1' then
tmp(i):= '1';
else
tmp(i):= '0';
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_carrier_csr_in_registers) return t_carrier_csr_in_registers is
variable tmp: t_carrier_csr_in_registers;
begin
tmp.carrier_pcb_rev_i := f_x_to_zero(left.carrier_pcb_rev_i) or f_x_to_zero(right.carrier_pcb_rev_i);
tmp.carrier_reserved_i := f_x_to_zero(left.carrier_reserved_i) or f_x_to_zero(right.carrier_reserved_i);
tmp.carrier_type_i := f_x_to_zero(left.carrier_type_i) or f_x_to_zero(right.carrier_type_i);
tmp.stat_fmc_pres_i := f_x_to_zero(left.stat_fmc_pres_i) or f_x_to_zero(right.stat_fmc_pres_i);
tmp.stat_p2l_pll_lck_i := f_x_to_zero(left.stat_p2l_pll_lck_i) or f_x_to_zero(right.stat_p2l_pll_lck_i);
tmp.stat_sys_pll_lck_i := f_x_to_zero(left.stat_sys_pll_lck_i) or f_x_to_zero(right.stat_sys_pll_lck_i);
tmp.stat_ddr3_cal_done_i := f_x_to_zero(left.stat_ddr3_cal_done_i) or f_x_to_zero(right.stat_ddr3_cal_done_i);
return tmp;
end function;
end package body;
hdl/top/spec_ref_design/spec_carrier_csr.cheby 0 → 100644
View file @ 440df6d9
memory-map:
bus: wb-32-be
name: spec_carrier_csr
description: Carrier control and status registers
comment: |
Wishbone slave for control and status registers related to the FMC carrier
x-hdl:
busgroup: True
iogroup: carrier_csr
children:
- reg:
name: carrier
address: 0x00000000
width: 32
access: ro
description: Carrier type and PCB version
children:
- field:
name: pcb_rev
range: 3-0
description: PCB revision
comment: |
Binary coded PCB layout revision.
- field:
name: reserved
range: 15-4
description: Reserved register
comment: |
Ignore on read, write with 0's.
- field:
name: type
range: 31-16
description: Carrier type
comment: |
Carrier type identifier
1 = SPEC
2 = SVEC
3 = VFC
4 = SPEXI
- reg:
name: stat
address: 0x00000004
width: 32
access: ro
description: Status
children:
- field:
name: fmc_pres
range: 0
description: FMC presence
comment: |
0: FMC slot is populated
1: FMC slot is not populated.
- field:
name: p2l_pll_lck
range: 1
description: GN4142 core P2L PLL status
comment: |
0: not locked
1: locked.
- field:
name: sys_pll_lck
range: 2
description: System clock PLL status
comment: |
0: not locked
1: locked.
- field:
name: ddr3_cal_done
range: 3
description: DDR3 calibration status
comment: |
0: not done
1: done.
- reg:
name: ctrl
address: 0x00000008
width: 32
access: rw
description: Control
children:
- field:
name: led_green
range: 0
description: Green LED
comment: |
Manual control of the front panel green LED (unused in the fmc-adc application)
- field:
name: led_red
range: 1
description: Red LED
comment: |
Manual control of the front panel red LED (unused in the fmc-adc application)
- reg:
name: rst
address: 0x0000000c
width: 32
access: wo
description: Reset Register
comment: |
Controls software reset of the mezzanine including the ddr interface and the time-tagging core.
children:
- field:
name: fmc0
range: 0
description: State of the reset line
comment: |
write 0: Normal FMC operation
write 1: FMC is held in reset
hdl/top/spec_ref_design/spec_carrier_csr.vhd 0 → 100644
View file @ 440df6d9
-- Do not edit; this file was generated by Cheby using these options:
-- -i spec_carrier_csr.cheby --gen-hdl=spec_carrier_csr.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
package spec_carrier_csr_pkg is
type t_carrier_csr_master_out is record
ctrl_led_green : std_logic;
ctrl_led_red : std_logic;
rst_fmc0 : std_logic;
end record t_carrier_csr_master_out;
subtype t_carrier_csr_slave_in is t_carrier_csr_master_out;
type t_carrier_csr_slave_out is record
carrier_pcb_rev : std_logic_vector(3 downto 0);
carrier_reserved : std_logic_vector(11 downto 0);
carrier_type : std_logic_vector(15 downto 0);
stat_fmc_pres : std_logic;
stat_p2l_pll_lck : std_logic;
stat_sys_pll_lck : std_logic;
stat_ddr3_cal_done : std_logic;
end record t_carrier_csr_slave_out;
subtype t_carrier_csr_master_in is t_carrier_csr_slave_out;
end spec_carrier_csr_pkg;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.spec_carrier_csr_pkg.all;
entity spec_carrier_csr is
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
-- Wires and registers
carrier_csr_i : in t_carrier_csr_master_in;
carrier_csr_o : out t_carrier_csr_master_out
);
end spec_carrier_csr;
architecture syn of spec_carrier_csr is
signal rd_int : std_logic;
signal wr_int : std_logic;
signal rd_ack_int : std_logic;
signal wr_ack_int : std_logic;
signal wb_en : std_logic;
signal ack_int : std_logic;
signal wb_rip : std_logic;
signal wb_wip : std_logic;
signal ctrl_led_green_reg : std_logic;
signal ctrl_led_red_reg : std_logic;
signal rst_fmc0_reg : std_logic;
signal reg_rdat_int : std_logic_vector(31 downto 0);
signal rd_ack1_int : std_logic;
begin
-- WB decode signals
wb_en <= wb_i.cyc and wb_i.stb;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_rip <= '0';
else
wb_rip <= (wb_rip or (wb_en and not wb_i.we)) and not rd_ack_int;
end if;
end if;
end process;
rd_int <= (wb_en and not wb_i.we) and not wb_rip;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_wip <= '0';
else
wb_wip <= (wb_wip or (wb_en and wb_i.we)) and not wr_ack_int;
end if;
end if;
end process;
wr_int <= (wb_en and wb_i.we) and not wb_wip;
ack_int <= rd_ack_int or wr_ack_int;
wb_o.ack <= ack_int;
wb_o.stall <= not ack_int and wb_en;
wb_o.rty <= '0';
wb_o.err <= '0';
-- Assign outputs
carrier_csr_o.ctrl_led_green <= ctrl_led_green_reg;
carrier_csr_o.ctrl_led_red <= ctrl_led_red_reg;
carrier_csr_o.rst_fmc0 <= rst_fmc0_reg;
-- Process for write requests.
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wr_ack_int <= '0';
ctrl_led_green_reg <= '0';
ctrl_led_red_reg <= '0';
rst_fmc0_reg <= '0';
else
wr_ack_int <= '0';
case wb_i.adr(3 downto 2) is
when "00" =>
-- Register carrier
when "01" =>
-- Register stat
when "10" =>
-- Register ctrl
if wr_int = '1' then
ctrl_led_green_reg <= wb_i.dat(0);
ctrl_led_red_reg <= wb_i.dat(1);
end if;
wr_ack_int <= wr_int;
when "11" =>
-- Register rst
if wr_int = '1' then
rst_fmc0_reg <= wb_i.dat(0);
end if;
wr_ack_int <= wr_int;
when others =>
wr_ack_int <= wr_int;
end case;
end if;
end if;
end process;
-- Process for registers read.
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack1_int <= '0';
else
reg_rdat_int <= (others => '0');
case wb_i.adr(3 downto 2) is
when "00" =>
-- carrier
reg_rdat_int(3 downto 0) <= carrier_csr_i.carrier_pcb_rev;
reg_rdat_int(15 downto 4) <= carrier_csr_i.carrier_reserved;
reg_rdat_int(31 downto 16) <= carrier_csr_i.carrier_type;
rd_ack1_int <= rd_int;
when "01" =>
-- stat
reg_rdat_int(0) <= carrier_csr_i.stat_fmc_pres;
reg_rdat_int(1) <= carrier_csr_i.stat_p2l_pll_lck;
reg_rdat_int(2) <= carrier_csr_i.stat_sys_pll_lck;
reg_rdat_int(3) <= carrier_csr_i.stat_ddr3_cal_done;
rd_ack1_int <= rd_int;
when "10" =>
-- ctrl
reg_rdat_int(0) <= ctrl_led_green_reg;
reg_rdat_int(1) <= ctrl_led_red_reg;
rd_ack1_int <= rd_int;
when "11" =>
-- rst
rd_ack1_int <= rd_int;
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
end if;
end if;
end process;
-- Process for read requests.
process (wb_i.adr, reg_rdat_int, rd_ack1_int, rd_int) begin
-- By default ack read requests
wb_o.dat <= (others => '0');
case wb_i.adr(3 downto 2) is
when "00" =>
-- carrier
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "01" =>
-- stat
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "10" =>
-- ctrl
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "11" =>
-- rst
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when others =>
rd_ack_int <= rd_int;
end case;
end process;
end syn;
hdl/top/spec_ref_design/spec_ref_fmc_adc_100Ms.vhd
View file @ 440df6d9
......@@ -41,7 +41,7 @@ use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.fmc_adc_mezzanine_pkg.all;
use work.synthesis_descriptor.all;
use work.carrier_csr_wbgen2_pkg.all;
use work.spec_carrier_csr_pkg.all;
use work.wr_xilinx_pkg.all;
use work.wr_board_pkg.all;
use work.wr_spec_pkg.all;
......@@ -433,8 +433,8 @@ architecture rtl of spec_ref_fmc_adc_100Ms is
signal tm_time_valid : std_logic;
-- IO for CSR registers
signal csr_regin : t_carrier_csr_in_registers;
signal csr_regout : t_carrier_csr_out_registers;
signal csr_regin : t_carrier_csr_master_in;
signal csr_regout : t_carrier_csr_master_out;
begin
......@@ -622,38 +622,26 @@ begin
-- Release tag
-- VCXO DAC control (CLR_N)
------------------------------------------------------------------------------
cmp_carrier_csr : entity work.carrier_csr
cmp_carrier_csr : entity work.spec_carrier_csr
port map (
rst_n_i => rst_sys_62m5_n,
clk_sys_i => clk_sys_62m5,
wb_adr_i => cnx_slave_in(c_WB_SLAVE_SPEC_CSR).adr(3 downto 2), -- cnx_slave_in.adr is byte address
wb_dat_i => cnx_slave_in(c_WB_SLAVE_SPEC_CSR).dat,
wb_dat_o => cnx_slave_out(c_WB_SLAVE_SPEC_CSR).dat,
wb_cyc_i => cnx_slave_in(c_WB_SLAVE_SPEC_CSR).cyc,
wb_sel_i => cnx_slave_in(c_WB_SLAVE_SPEC_CSR).sel,
wb_stb_i => cnx_slave_in(c_WB_SLAVE_SPEC_CSR).stb,
wb_we_i => cnx_slave_in(c_WB_SLAVE_SPEC_CSR).we,
wb_ack_o => cnx_slave_out(c_WB_SLAVE_SPEC_CSR).ack,
wb_stall_o => open,
regs_i => csr_regin,
regs_o => csr_regout);
csr_regin.carrier_pcb_rev_i <= pcbrev_i;
csr_regin.carrier_reserved_i <= (others => '0');
csr_regin.carrier_type_i <= c_CARRIER_TYPE;
csr_regin.stat_fmc_pres_i <= fmc_prsnt_m2c_n_i;
csr_regin.stat_p2l_pll_lck_i <= gn4124_status(0);
csr_regin.stat_sys_pll_lck_i <= sys_clk_pll_locked;
csr_regin.stat_ddr3_cal_done_i <= ddr_calib_done;
led_red <= csr_regout.ctrl_led_red_o;
led_green <= csr_regout.ctrl_led_green_o;
sw_rst_fmc <= csr_regout.rst_fmc0_o;
-- Unused wishbone signals
cnx_slave_out(c_WB_SLAVE_SPEC_CSR).err <= '0';
cnx_slave_out(c_WB_SLAVE_SPEC_CSR).rty <= '0';
cnx_slave_out(c_WB_SLAVE_SPEC_CSR).stall <= '0';
rst_n_i => rst_sys_62m5_n,
clk_i => clk_sys_62m5,
wb_i => cnx_slave_in(c_WB_SLAVE_SPEC_CSR),
wb_o => cnx_slave_out(c_WB_SLAVE_SPEC_CSR),
carrier_csr_i => csr_regin,
carrier_csr_o => csr_regout);
csr_regin.carrier_pcb_rev <= pcbrev_i;
csr_regin.carrier_reserved <= (others => '0');
csr_regin.carrier_type <= c_CARRIER_TYPE;
csr_regin.stat_fmc_pres <= fmc_prsnt_m2c_n_i;
csr_regin.stat_p2l_pll_lck <= gn4124_status(0);
csr_regin.stat_sys_pll_lck <= sys_clk_pll_locked;
csr_regin.stat_ddr3_cal_done <= ddr_calib_done;
led_red <= csr_regout.ctrl_led_red;
led_green <= csr_regout.ctrl_led_green;
sw_rst_fmc <= csr_regout.rst_fmc0;
------------------------------------------------------------------------------
-- Vectored interrupt controller (VIC)
......
hdl/top/spec_ref_design/wb_gen/Makefile
View file @ 440df6d9
......@@ -2,11 +2,7 @@ WBGEN2=$(shell which wbgen2)
RTL=../
TEX=../../../../doc/manual/spec/
all: carrier_csr dma_eic
carrier_csr:
$(WBGEN2) -l vhdl -H record -V $(RTL)$@.vhd -p $(RTL)$@_wbgen2_pkg.vhd -f html -D $@.htm -C $@.h $@.wb
$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
all: dma_eic
dma_eic:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
......
hdl/top/spec_ref_design/wb_gen/carrier_csr.h deleted 100644 → 0
View file @ dabad887
/*
Register definitions for slave core: Carrier control and status registers
* File : carrier_csr.h
* Author : auto-generated by wbgen2 from carrier_csr.wb
* Created : Mon Feb 26 15:24:45 2018
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_CARRIER_CSR_WB
#define __WBGEN2_REGDEFS_CARRIER_CSR_WB
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <inttypes.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Carrier type and PCB version */
/* definitions for field: PCB revision in reg: Carrier type and PCB version */
#define CARRIER_CSR_CARRIER_PCB_REV_MASK WBGEN2_GEN_MASK(0, 4)
#define CARRIER_CSR_CARRIER_PCB_REV_SHIFT 0
#define CARRIER_CSR_CARRIER_PCB_REV_W(value) WBGEN2_GEN_WRITE(value, 0, 4)
#define CARRIER_CSR_CARRIER_PCB_REV_R(reg) WBGEN2_GEN_READ(reg, 0, 4)
/* definitions for field: Reserved register in reg: Carrier type and PCB version */
#define CARRIER_CSR_CARRIER_RESERVED_MASK WBGEN2_GEN_MASK(4, 12)
#define CARRIER_CSR_CARRIER_RESERVED_SHIFT 4
#define CARRIER_CSR_CARRIER_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 4, 12)
#define CARRIER_CSR_CARRIER_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 4, 12)
/* definitions for field: Carrier type in reg: Carrier type and PCB version */
#define CARRIER_CSR_CARRIER_TYPE_MASK WBGEN2_GEN_MASK(16, 16)
#define CARRIER_CSR_CARRIER_TYPE_SHIFT 16
#define CARRIER_CSR_CARRIER_TYPE_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define CARRIER_CSR_CARRIER_TYPE_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Status */
/* definitions for field: FMC presence in reg: Status */
#define CARRIER_CSR_STAT_FMC_PRES WBGEN2_GEN_MASK(0, 1)
/* definitions for field: GN4142 core P2L PLL status in reg: Status */
#define CARRIER_CSR_STAT_P2L_PLL_LCK WBGEN2_GEN_MASK(1, 1)
/* definitions for field: System clock PLL status in reg: Status */
#define CARRIER_CSR_STAT_SYS_PLL_LCK WBGEN2_GEN_MASK(2, 1)
/* definitions for field: DDR3 calibration status in reg: Status */
#define CARRIER_CSR_STAT_DDR3_CAL_DONE WBGEN2_GEN_MASK(3, 1)
/* definitions for register: Control */
/* definitions for field: Green LED in reg: Control */
#define CARRIER_CSR_CTRL_LED_GREEN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Red LED in reg: Control */
#define CARRIER_CSR_CTRL_LED_RED WBGEN2_GEN_MASK(1, 1)
/* definitions for field: DAC clear in reg: Control */
#define CARRIER_CSR_CTRL_DAC_CLR_N WBGEN2_GEN_MASK(2, 1)
/* definitions for register: Reset Register */
/* definitions for field: State of the reset line in reg: Reset Register */
#define CARRIER_CSR_RST_FMC0 WBGEN2_GEN_MASK(0, 1)
PACKED struct CARRIER_CSR_WB {
/* [0x0]: REG Carrier type and PCB version */
uint32_t CARRIER;
/* [0x4]: REG Status */
uint32_t STAT;
/* [0x8]: REG Control */
uint32_t CTRL;
/* [0xc]: REG Reset Register */
uint32_t RST;
};
#endif
hdl/top/spec_ref_design/wb_gen/carrier_csr.htm deleted 100644 → 0
View file @ dabad887
This diff is collapsed.
hdl/top/spec_ref_design/wb_gen/carrier_csr.wb deleted 100644 → 0
View file @ dabad887
peripheral {
name = "Carrier control and status registers";
description = "Wishbone slave for control and status registers related to the FMC carrier";
hdl_entity = "carrier_csr";
prefix = "carrier_csr";
reg {
name = "Carrier type and PCB version";
prefix = "carrier";
field {
name = "PCB revision";
description = "Binary coded PCB layout revision.";
prefix = "pcb_rev";
type = SLV;
size = 4;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Reserved register";
description = "Ignore on read, write with 0's.";
prefix = "reserved";
type = SLV;
size = 12;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Carrier type";
description = "Carrier type identifier\n1 = SPEC\n2 = SVEC\n3 = VFC\n4 = SPEXI";
prefix = "type";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Status";
prefix = "stat";
field {
name = "FMC presence";
description = "0: FMC slot is populated\n1: FMC slot is not populated.";
prefix = "fmc_pres";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "GN4142 core P2L PLL status";
description = "0: not locked\n1: locked.";
prefix = "p2l_pll_lck";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "System clock PLL status";
description = "0: not locked\n1: locked.";
prefix = "sys_pll_lck";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "DDR3 calibration status";
description = "0: not done\n1: done.";
prefix = "ddr3_cal_done";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Control";
prefix = "ctrl";
field {
name = "Green LED";
description = "Manual control of the front panel green LED (unused in the fmc-adc application)";
prefix = "led_green";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Red LED";
description = "Manual control of the front panel red LED (unused in the fmc-adc application)";
prefix = "led_red";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "DAC clear";
description = "Active low clear signal for VCXO DACs";
prefix = "dac_clr_n";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Reset Register";
prefix = "rst";
description = "Controls software reset of the mezzanine including the ddr interface and the time-tagging core.";
field {
name = "State of the reset line";
description = "write 0: Normal FMC operation\
write 1: FMC is held in reset";
type = BIT;
size = 1;
prefix = "fmc0";
access_bus = WRITE;
access_dev = READ;
};
};
};
software/include/hw/spec_carrier_csr.h 0 → 100644
View file @ 440df6d9
#ifndef __CHEBY__SPEC_CARRIER_CSR__H__
#define __CHEBY__SPEC_CARRIER_CSR__H__
#define SPEC_CARRIER_CSR_SIZE 16
/* Carrier type and PCB version */
#define SPEC_CARRIER_CSR_CARRIER 0x0UL
#define SPEC_CARRIER_CSR_CARRIER_PCB_REV_MASK 0xfUL
#define SPEC_CARRIER_CSR_CARRIER_PCB_REV_SHIFT 0
#define SPEC_CARRIER_CSR_CARRIER_RESERVED_MASK 0xfff0UL
#define SPEC_CARRIER_CSR_CARRIER_RESERVED_SHIFT 4
#define SPEC_CARRIER_CSR_CARRIER_TYPE_MASK 0xffff0000UL
#define SPEC_CARRIER_CSR_CARRIER_TYPE_SHIFT 16
/* Status */
#define SPEC_CARRIER_CSR_STAT 0x4UL
#define SPEC_CARRIER_CSR_STAT_FMC_PRES 0x1UL
#define SPEC_CARRIER_CSR_STAT_P2L_PLL_LCK 0x2UL
#define SPEC_CARRIER_CSR_STAT_SYS_PLL_LCK 0x4UL
#define SPEC_CARRIER_CSR_STAT_DDR3_CAL_DONE 0x8UL
/* Control */
#define SPEC_CARRIER_CSR_CTRL 0x8UL
#define SPEC_CARRIER_CSR_CTRL_LED_GREEN 0x1UL
#define SPEC_CARRIER_CSR_CTRL_LED_RED 0x2UL
/* Reset Register */
#define SPEC_CARRIER_CSR_RST 0xcUL
#define SPEC_CARRIER_CSR_RST_FMC0 0x1UL
struct spec_carrier_csr {
/* [0x0]: REG (ro) Carrier type and PCB version */
uint32_t carrier;
/* [0x4]: REG (ro) Status */
uint32_t stat;
/* [0x8]: REG (rw) Control */
uint32_t ctrl;
/* [0xc]: REG (wo) Reset Register */
uint32_t rst;
};
#endif /* __CHEBY__SPEC_CARRIER_CSR__H__ */
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment