Commit 3cc460e5 authored by Tristan Gingold's avatar Tristan Gingold

Adjust driver for new DMA page on svec

parent 30b3a40d
......@@ -656,7 +656,8 @@ static void fa_sg_alloc_table_init(struct fa_dev *fa)
static struct fmc_adc_platform_data fmc_adc_pdata_default = {
.flags = 0,
.vme_ddr_offset = 0,
.vme_reg_offset = 0,
.vme_dma_offset = 0,
.calib_trig_time = 0,
.calib_trig_threshold = 0,
.calib_trig_internal = 0,
......
......@@ -214,8 +214,6 @@ static unsigned int zfad_block_n_pages(struct zio_block *block)
#ifdef CONFIG_FMC_ADC_SVEC
#define ADC_VME_DDR_ADDR 0x00
#define ADC_VME_DDR_DATA 0x04
#define SVEC_FUNC_NR 1 /* HARD coded in SVEC */
static inline struct vme_dev *fa_to_vme_dev(struct fa_dev *fa)
......@@ -233,9 +231,9 @@ static unsigned long fa_ddr_data_vme_addr(struct fa_dev *fa)
"Invalid VME function\n"))
return ~0; /* invalid address, we will see VME errors */
WARN(data->vme_ddr_offset == 0, "Invalid DDR DATA offset");
WARN(data->vme_dma_offset == 0, "Invalid DDR DMA offset");
addr = vdev->map[SVEC_FUNC_NR].vme_addrl;
addr += data->vme_ddr_offset + ADC_VME_DDR_DATA;
addr += data->vme_dma_offset;
return addr;
}
......@@ -251,7 +249,7 @@ static void *fa_ddr_addr_reg_off(struct fa_dev *fa)
return NULL; /* invalid address, we will see VME errors */
addr = vdev->map[SVEC_FUNC_NR].kernel_va;
addr += data->vme_ddr_offset + ADC_VME_DDR_ADDR;
addr += data->vme_reg_offset;
return addr;
}
......@@ -358,10 +356,8 @@ static int zfad_dma_context_init_svec(struct zio_cset *cset,
* write the data address in the ddr_addr register: this
* address has been computed after ACQ_END by looking to the
* trigger position see fa-irq.c::irq_acq_end.
* Be careful: the SVEC HW version expects an address of 32bits word
* therefore mem-offset in byte is translated into 32bit word
*/
fa_iowrite(fa, zfad_block->sconfig.src_addr / 4, addr);
*/
fa_iowrite(fa, zfad_block->sconfig.src_addr, addr);
}
zfad_block->dma_ctx = desc;
......
......@@ -23,15 +23,15 @@
*/
#define SVEC_BASE_REGS_CSR 0x40UL
#define SVEC_FPGA_CSR_DDR4_ADDR (SVEC_BASE_REGS_CSR + 0x18)
#define SVEC_FPGA_CSR_DDR4_DATA (SVEC_BASE_REGS_CSR + 0x1C)
#define SVEC_FPGA_CSR_DDR5_ADDR (SVEC_BASE_REGS_CSR + 0x20)
#define SVEC_FPGA_CSR_DDR5_DATA (SVEC_BASE_REGS_CSR + 0x24)
#define SVEC_FPGA_DDR4_DMA (0x2000)
#define SVEC_FPGA_CSR_DDR5_ADDR (SVEC_BASE_REGS_CSR + 0x1C)
#define SVEC_FPGA_DDR5_DMA (0x3000)
enum fa_svec_dev_offsets {
FA_SVEC_ADC1_MEM_START = 0x000002000,
FA_SVEC_ADC1_MEM_END = 0x00003FFF,
FA_SVEC_ADC1_MEM_START = 0x00002000,
FA_SVEC_ADC1_MEM_END = 0x00003FFF,
FA_SVEC_ADC2_MEM_START = 0x00004000,
FA_SVEC_ADC2_MEM_END = 0x000005FFF,
FA_SVEC_ADC2_MEM_END = 0x00005FFF,
};
static inline struct platform_device *platform_device_register_resndata_mask(
......@@ -59,7 +59,8 @@ static struct fmc_adc_platform_data fa_svec_adc_pdata[] = {
.flags = FMC_ADC_BIG_ENDIAN |
FMC_ADC_SVEC |
FMC_ADC_NOSQUASH_SCATTERLIST,
.vme_ddr_offset = SVEC_FPGA_CSR_DDR4_ADDR,
.vme_reg_offset = SVEC_FPGA_CSR_DDR4_ADDR,
.vme_dma_offset = SVEC_FPGA_DDR4_DMA,
.calib_trig_time = 0,
.calib_trig_threshold = 0,
.calib_trig_internal = 0,
......@@ -67,7 +68,8 @@ static struct fmc_adc_platform_data fa_svec_adc_pdata[] = {
.flags = FMC_ADC_BIG_ENDIAN |
FMC_ADC_SVEC |
FMC_ADC_NOSQUASH_SCATTERLIST,
.vme_ddr_offset = SVEC_FPGA_CSR_DDR5_ADDR,
.vme_reg_offset = SVEC_FPGA_CSR_DDR5_ADDR,
.vme_dma_offset = SVEC_FPGA_DDR5_DMA,
.calib_trig_time = 0,
.calib_trig_threshold = 0,
.calib_trig_internal = 0,
......
......@@ -19,7 +19,8 @@
struct fmc_adc_platform_data {
unsigned long flags;
unsigned long vme_ddr_offset;
unsigned long vme_reg_offset;
unsigned long vme_dma_offset;
uint8_t calib_trig_time;
uint8_t calib_trig_threshold;
uint8_t calib_trig_internal;
......
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