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FMC ADC 100M 14b 4cha
Commit 3b816e09 authored by Federico Vaga's avatar Federico Vaga
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Merge remote-tracking branch 'origin/develop' into develop

parents 9e498a34 0e54f638
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Showing with 96 additions and 15 deletions
hdl/cheby/fmc_adc_100Ms_channel_regs.cheby
View file @ 3b816e09
......@@ -111,3 +111,29 @@ memory-map:
comment: |
Delay to apply on the trigger in sampling clock period.
The default clock frequency is 100MHz (period = 10ns).
- reg:
name: calib_val
address: 0x00000018
width: 32
access: ro
description: Channel calibration value (read from hw)
children:
- field:
name: gain
range: 15-0
description: Gain calibration for channel
- field:
name: offset
range: 31-16
description: Offset calibration for channel
- reg:
name: sat_val
address: 0x0000001c
width: 32
access: ro
description: Channel saturation register (read from hw)
children:
- field:
name: val
range: 14-0
description: Saturation value for channel
hdl/cheby/fmc_adc_100Ms_channel_regs.vhd
View file @ 3b816e09
......@@ -25,6 +25,9 @@ package fmc_adc_100ms_channel_regs_pkg is
type t_fmc_adc_100ms_ch_slave_out is record
sta_val : std_logic_vector(15 downto 0);
calib_val_gain : std_logic_vector(15 downto 0);
calib_val_offset : std_logic_vector(15 downto 0);
sat_val_val : std_logic_vector(14 downto 0);
end record t_fmc_adc_100ms_ch_slave_out;
subtype t_fmc_adc_100ms_ch_master_in is t_fmc_adc_100ms_ch_slave_out;
......@@ -218,6 +221,10 @@ begin
end if;
end process;
-- Register calib_val
-- Register sat_val
-- Process for write requests.
process (wr_adr_d0, wr_req_d0, ctl_wack, calib_wack, sat_wack, trig_thres_wack,
trig_dly_wack) begin
......@@ -250,6 +257,12 @@ begin
-- Reg trig_dly
trig_dly_wreq <= wr_req_d0;
wr_ack_int <= trig_dly_wack;
when "110" =>
-- Reg calib_val
wr_ack_int <= wr_req_d0;
when "111" =>
-- Reg sat_val
wr_ack_int <= wr_req_d0;
when others =>
wr_ack_int <= wr_req_d0;
end case;
......@@ -258,7 +271,10 @@ begin
-- Process for read requests.
process (adr_int, rd_req_int, ctl_ssr_reg, fmc_adc_100ms_ch_i.sta_val,
calib_gain_reg, calib_offset_reg, sat_val_reg, trig_thres_val_reg,
trig_thres_hyst_reg, trig_dly_reg) begin
trig_thres_hyst_reg, trig_dly_reg,
fmc_adc_100ms_ch_i.calib_val_gain,
fmc_adc_100ms_ch_i.calib_val_offset,
fmc_adc_100ms_ch_i.sat_val_val) begin
-- By default ack read requests
rd_dat_d0 <= (others => 'X');
case adr_int(4 downto 2) is
......@@ -291,6 +307,16 @@ begin
-- Reg trig_dly
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= trig_dly_reg;
when "110" =>
-- Reg calib_val
rd_ack_d0 <= rd_req_int;
rd_dat_d0(15 downto 0) <= fmc_adc_100ms_ch_i.calib_val_gain;
rd_dat_d0(31 downto 16) <= fmc_adc_100ms_ch_i.calib_val_offset;
when "111" =>
-- Reg sat_val
rd_ack_d0 <= rd_req_int;
rd_dat_d0(14 downto 0) <= fmc_adc_100ms_ch_i.sat_val_val;
rd_dat_d0(31 downto 15) <= (others => '0');
when others =>
rd_ack_d0 <= rd_req_int;
end case;
......
general-cores @ a0aeffbb
Subproject commit 7d76d2b6503cd3f129fd4bc3797b6abfefb752c5
Subproject commit a0aeffbb14ab570069ef667d07889c7fe004a2bf
hdl/rtl/fmc_adc_100Ms_core.vhd
View file @ 3b816e09
......@@ -566,6 +566,9 @@ begin
fmc_adc_100ms_ch_o => channel_regout(I));
channel_regin(I).sta_val <= serdes_out_data_synced((16*I)-1 downto 16*(I-1));
channel_regin(I).calib_val_gain <= gain_calibr(I*16-1 downto (I-1)*16);
channel_regin(I).calib_val_offset <= offset_calibr(I*16-1 downto (I-1)*16);
channel_regin(I).sat_val_val <= sat_val(I*15-1 downto (I-1)*15);
int_trig_delay_in(I) <= channel_regout(I).trig_dly;
int_trig_thres_in(I) <= channel_regout(I).trig_thres_val;
......@@ -603,7 +606,7 @@ begin
g_WIDTH => 32)
port map (
clk_in_i => sys_clk_i,
rst_in_n_i => '1',
rst_in_n_i => sys_rst_n_i,
clk_out_i => fs_clk,
rst_out_n_i => '1',
data_i => csr_regout.downsample,
......@@ -617,7 +620,7 @@ begin
g_WIDTH => 64)
port map (
clk_in_i => fs_clk,
rst_in_n_i => '1',
rst_in_n_i => fs_rst_n,
clk_out_i => sys_clk_i,
rst_out_n_i => '1',
data_i => serdes_out_data,
......@@ -629,7 +632,7 @@ begin
g_WIDTH => 32)
port map (
clk_in_i => sys_clk_i,
rst_in_n_i => '1',
rst_in_n_i => sys_rst_n_i,
clk_out_i => fs_clk,
rst_out_n_i => '1',
data_i => csr_regout.ext_trig_dly,
......@@ -657,7 +660,7 @@ begin
g_WIDTH => 32)
port map (
clk_in_i => sys_clk_i,
rst_in_n_i => '1',
rst_in_n_i => sys_rst_n_i,
clk_out_i => fs_clk,
rst_out_n_i => '1',
data_i(15 downto 0) => int_trig_thres_in(I),
......@@ -671,7 +674,7 @@ begin
g_WIDTH => 15)
port map (
clk_in_i => sys_clk_i,
rst_in_n_i => '1',
rst_in_n_i => sys_rst_n_i,
clk_out_i => fs_clk,
rst_out_n_i => '1',
data_i => sat_val_in(15*I-1 downto 15*(I-1)),
......@@ -683,7 +686,7 @@ begin
g_WIDTH => 32)
port map (
clk_in_i => sys_clk_i,
rst_in_n_i => '1',
rst_in_n_i => sys_rst_n_i,
clk_out_i => fs_clk,
rst_out_n_i => '1',
data_i => int_trig_delay_in(I),
......@@ -696,7 +699,7 @@ begin
g_WIDTH => 128)
port map (
clk_in_i => sys_clk_i,
rst_in_n_i => '1',
rst_in_n_i => sys_rst_n_i,
clk_out_i => fs_clk,
rst_out_n_i => '1',
data_i => sync_calib_in,
......
hdl/testbench/include/fmc_adc_100Ms_channel_regs.v
View file @ 3b816e09
......@@ -2,7 +2,7 @@
//
// SPDX-License-Identifier: CC0-1.0
`define FMC_ADC_100MS_CHANNEL_REGS_SIZE 24
`define FMC_ADC_100MS_CHANNEL_REGS_SIZE 32
`define ADDR_FMC_ADC_100MS_CHANNEL_REGS_CTL 'h0
`define FMC_ADC_100MS_CHANNEL_REGS_CTL_SSR_OFFSET 0
`define FMC_ADC_100MS_CHANNEL_REGS_CTL_SSR 'h7f
......@@ -23,3 +23,11 @@
`define FMC_ADC_100MS_CHANNEL_REGS_TRIG_THRES_HYST_OFFSET 16
`define FMC_ADC_100MS_CHANNEL_REGS_TRIG_THRES_HYST 'hffff0000
`define ADDR_FMC_ADC_100MS_CHANNEL_REGS_TRIG_DLY 'h14
`define ADDR_FMC_ADC_100MS_CHANNEL_REGS_CALIB_VAL 'h18
`define FMC_ADC_100MS_CHANNEL_REGS_CALIB_VAL_GAIN_OFFSET 0
`define FMC_ADC_100MS_CHANNEL_REGS_CALIB_VAL_GAIN 'hffff
`define FMC_ADC_100MS_CHANNEL_REGS_CALIB_VAL_OFFSET_OFFSET 16
`define FMC_ADC_100MS_CHANNEL_REGS_CALIB_VAL_OFFSET 'hffff0000
`define ADDR_FMC_ADC_100MS_CHANNEL_REGS_SAT_VAL 'h1c
`define FMC_ADC_100MS_CHANNEL_REGS_SAT_VAL_VAL_OFFSET 0
`define FMC_ADC_100MS_CHANNEL_REGS_SAT_VAL_VAL 'h7fff
software/include/hw/fmc_adc_100Ms_channel_regs.h
View file @ 3b816e09
#ifndef __CHEBY__FMC_ADC_100MS_CHANNEL_REGS__H__
#define __CHEBY__FMC_ADC_100MS_CHANNEL_REGS__H__
#define FMC_ADC_100MS_CHANNEL_REGS_SIZE 24 /* 0x18 */
#define FMC_ADC_100MS_CHANNEL_REGS_SIZE 32 /* 0x20 */
/* Channel control register */
#define FMC_ADC_100MS_CHANNEL_REGS_CTL 0x0UL
......@@ -34,6 +34,18 @@
/* Channel trigger delay */
#define FMC_ADC_100MS_CHANNEL_REGS_TRIG_DLY 0x14UL
/* Channel calibration value (read from hw) */
#define FMC_ADC_100MS_CHANNEL_REGS_CALIB_VAL 0x18UL
#define FMC_ADC_100MS_CHANNEL_REGS_CALIB_VAL_GAIN_MASK 0xffffUL
#define FMC_ADC_100MS_CHANNEL_REGS_CALIB_VAL_GAIN_SHIFT 0
#define FMC_ADC_100MS_CHANNEL_REGS_CALIB_VAL_OFFSET_MASK 0xffff0000UL
#define FMC_ADC_100MS_CHANNEL_REGS_CALIB_VAL_OFFSET_SHIFT 16
/* Channel saturation register (read from hw) */
#define FMC_ADC_100MS_CHANNEL_REGS_SAT_VAL 0x1cUL
#define FMC_ADC_100MS_CHANNEL_REGS_SAT_VAL_VAL_MASK 0x7fffUL
#define FMC_ADC_100MS_CHANNEL_REGS_SAT_VAL_VAL_SHIFT 0
struct fmc_adc_100ms_channel_regs {
/* [0x0]: REG (rw) Channel control register */
uint32_t ctl;
......@@ -52,6 +64,12 @@ struct fmc_adc_100ms_channel_regs {
/* [0x14]: REG (rw) Channel trigger delay */
uint32_t trig_dly;
/* [0x18]: REG (ro) Channel calibration value (read from hw) */
uint32_t calib_val;
/* [0x1c]: REG (ro) Channel saturation register (read from hw) */
uint32_t sat_val;
};
#endif /* __CHEBY__FMC_ADC_100MS_CHANNEL_REGS__H__ */
software/include/hw/fmc_adc_100Ms_csr.h
View file @ 3b816e09
......@@ -163,25 +163,25 @@ struct fmc_adc_100ms_csr {
struct fmc_adc_100ms_channel_regs fmc_adc_ch1;
/* padding to: 48 words */
uint32_t __padding_1[10];
uint32_t __padding_1[8];
/* [0xc0]: SUBMAP Channel 2 registers */
struct fmc_adc_100ms_channel_regs fmc_adc_ch2;
/* padding to: 64 words */
uint32_t __padding_2[10];
uint32_t __padding_2[8];
/* [0x100]: SUBMAP Channel 3 registers */
struct fmc_adc_100ms_channel_regs fmc_adc_ch3;
/* padding to: 80 words */
uint32_t __padding_3[10];
uint32_t __padding_3[8];
/* [0x140]: SUBMAP Channel 4 registers */
struct fmc_adc_100ms_channel_regs fmc_adc_ch4;
/* padding to: 80 words */
uint32_t __padding_4[42];
uint32_t __padding_4[40];
};
#endif /* __CHEBY__FMC_ADC_100MS_CSR__H__ */
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