Commit 3957c9fe authored by Matthieu Cattin's avatar Matthieu Cattin

hdl: Remove bitstream_type and bitstream_date from carrier csr registers.

This information is now in sdb header (meta info).
parent c79f136f
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Wed Nov 23 09:30:44 2011
-- Created : Mon Mar 11 17:11:09 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
......@@ -18,7 +18,7 @@ entity carrier_csr is
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(2 downto 0);
wb_addr_i : in std_logic_vector(1 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
......@@ -32,10 +32,6 @@ entity carrier_csr is
carrier_csr_carrier_reserved_i : in std_logic_vector(11 downto 0);
-- Port for std_logic_vector field: 'Carrier type' in reg: 'Carrier type and PCB version'
carrier_csr_carrier_type_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Bitstream type' in reg: 'Bitstream type'
carrier_csr_bitstream_type_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Bitstream date' in reg: 'Bitstream date'
carrier_csr_bitstream_date_i : in std_logic_vector(31 downto 0);
-- Port for BIT field: 'FMC presence' in reg: 'Status'
carrier_csr_stat_fmc_pres_i : in std_logic;
-- Port for BIT field: 'GN4142 core P2L PLL status' in reg: 'Status'
......@@ -67,7 +63,7 @@ signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(2 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
......@@ -107,8 +103,8 @@ begin
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(2 downto 0) is
when "000" =>
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
else
rddata_reg(3 downto 0) <= carrier_csr_carrier_pcb_rev_i;
......@@ -117,22 +113,12 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= carrier_csr_bitstream_type_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= carrier_csr_bitstream_date_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011" =>
when "01" =>
if (wb_we_i = '1') then
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
else
rddata_reg(0) <= carrier_csr_stat_fmc_pres_i;
rddata_reg(1) <= carrier_csr_stat_p2l_pll_lck_i;
......@@ -142,10 +128,13 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100" =>
when "10" =>
if (wb_we_i = '1') then
rddata_reg(0) <= 'X';
carrier_csr_ctrl_led_green_int <= wrdata_reg(0);
rddata_reg(1) <= 'X';
carrier_csr_ctrl_led_red_int <= wrdata_reg(1);
rddata_reg(2) <= 'X';
carrier_csr_ctrl_dac_clr_n_int <= wrdata_reg(2);
carrier_csr_ctrl_reserved_int <= wrdata_reg(31 downto 3);
else
......@@ -172,8 +161,6 @@ begin
-- PCB revision
-- Reserved register
-- Carrier type
-- Bitstream type
-- Bitstream date
-- FMC presence
-- GN4142 core P2L PLL status
-- System clock PLL status
......
......@@ -173,7 +173,7 @@ architecture rtl of spec_top_fmc_adc_100Ms is
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(2 downto 0);
wb_addr_i : in std_logic_vector(1 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
......@@ -184,8 +184,6 @@ architecture rtl of spec_top_fmc_adc_100Ms is
carrier_csr_carrier_pcb_rev_i : in std_logic_vector(3 downto 0);
carrier_csr_carrier_reserved_i : in std_logic_vector(11 downto 0);
carrier_csr_carrier_type_i : in std_logic_vector(15 downto 0);
carrier_csr_bitstream_type_i : in std_logic_vector(31 downto 0);
carrier_csr_bitstream_date_i : in std_logic_vector(31 downto 0);
carrier_csr_stat_fmc_pres_i : in std_logic;
carrier_csr_stat_p2l_pll_lck_i : in std_logic;
carrier_csr_stat_sys_pll_lck_i : in std_logic;
......@@ -422,8 +420,6 @@ architecture rtl of spec_top_fmc_adc_100Ms is
-- SPEC carrier CSR constants
constant c_CARRIER_TYPE : std_logic_vector(15 downto 0) := X"0001";
constant c_BITSTREAM_TYPE : std_logic_vector(31 downto 0) := X"00000001";
constant c_BITSTREAM_DATE : std_logic_vector(31 downto 0) := X"50AA5124"; -- UTC time
------------------------------------------------------------------------------
-- Signals declaration
......@@ -792,7 +788,7 @@ begin
port map(
rst_n_i => sys_rst_n,
wb_clk_i => sys_clk_125,
wb_addr_i => cnx_master_out(c_SLAVE_SPEC_CSR).adr(4 downto 2), -- cnx_master_out.adr is byte address
wb_addr_i => cnx_master_out(c_SLAVE_SPEC_CSR).adr(3 downto 2), -- cnx_master_out.adr is byte address
wb_data_i => cnx_master_out(c_SLAVE_SPEC_CSR).dat,
wb_data_o => cnx_master_in(c_SLAVE_SPEC_CSR).dat,
wb_cyc_i => cnx_master_out(c_SLAVE_SPEC_CSR).cyc,
......@@ -803,8 +799,6 @@ begin
carrier_csr_carrier_pcb_rev_i => pcb_ver_i,
carrier_csr_carrier_reserved_i => X"000",
carrier_csr_carrier_type_i => c_CARRIER_TYPE,
carrier_csr_bitstream_type_i => c_BITSTREAM_TYPE,
carrier_csr_bitstream_date_i => c_BITSTREAM_DATE,
carrier_csr_stat_fmc_pres_i => prsnt_m2c_n_i,
carrier_csr_stat_p2l_pll_lck_i => p2l_pll_locked,
carrier_csr_stat_sys_pll_lck_i => sys_clk_pll_locked,
......
......@@ -3,7 +3,7 @@
* File : carrier_csr.h
* Author : auto-generated by wbgen2 from carrier_csr.wb
* Created : Wed Nov 23 09:30:44 2011
* Created : Mon Mar 11 17:11:09 2013
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
......@@ -51,10 +51,6 @@
#define CARRIER_CSR_CARRIER_TYPE_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define CARRIER_CSR_CARRIER_TYPE_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Bitstream type */
/* definitions for register: Bitstream date */
/* definitions for register: Status */
/* definitions for field: FMC presence in reg: Status */
......@@ -95,13 +91,9 @@
PACKED struct CARRIER_CSR_WB {
/* [0x0]: REG Carrier type and PCB version */
uint32_t CARRIER;
/* [0x4]: REG Bitstream type */
uint32_t BITSTREAM_TYPE;
/* [0x8]: REG Bitstream date */
uint32_t BITSTREAM_DATE;
/* [0xc]: REG Status */
/* [0x4]: REG Status */
uint32_t STAT;
/* [0x10]: REG Control */
/* [0x8]: REG Control */
uint32_t CTRL;
};
......
This diff is collapsed.
......@@ -31,7 +31,7 @@ peripheral {
field {
name = "Carrier type";
description = "Carrier type identifier";
description = "Carrier type identifier\n1 = SPEC\n2 = SVEC\n3 = VFC\n4 = SPEXI";
prefix = "type";
type = SLV;
size = 16;
......@@ -40,34 +40,6 @@ peripheral {
};
};
reg {
name = "Bitstream type";
prefix = "bitstream_type";
field {
name = "Bitstream type";
description = "Bitstream (firmware) type, unsigned 32-bit number.";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Bitstream date";
prefix = "bitstream_date";
field {
name = "Bitstream date";
description = "Bitstream generation date, unsigned 32-bit UTC time.";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Status";
prefix = "stat";
......
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