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FMC ADC 100M 14b 4cha
Commit 339ad9a0 authored by Federico Vaga's avatar Federico Vaga
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Merge branch 'feature/dma-page' into develop

parents 5f61c4fb 952e85c0
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hdl/cheby/Makefile
View file @ 339ad9a0
......@@ -13,6 +13,6 @@ all: $(TARGETS)
$(TARGETS): %.vhd : %.cheby
@echo -e "\n\033[34m\033[1m-> Processing file $<\033[0m"
@cheby -i $< --gen-hdl=$@
@cheby -i $< \
--gen-consts=$(SIM)/$(@:.vhd=.v)
cheby -i $< --gen-hdl=$@
cheby -i $< --gen-consts=$(SIM)/$(@:.vhd=.v)
cheby -i $< --gen-c=../../software/include/hw/$(<:.cheby=.h)
hdl/cheby/svec_ref_fmc_adc_100Ms_mmap.cheby
View file @ 339ad9a0
......@@ -6,14 +6,14 @@ memory-map:
name: svec_ref_fmc_adc_100m_mmap
bus: wb-32-be
description: SPEC FMC-ADC-100M memory map
size: 0x8000
size: 0x10000
x-hdl:
busgroup: True
pipeline: wr,rd
children:
- submap:
name: metadata
address: 0x2000
address: 0x4000
size: 0x40
interface: wb-32-be
x-hdl:
......@@ -21,11 +21,11 @@ memory-map:
description: a ROM containing the application metadata
- submap:
name: fmc1_adc_mezzanine
address: 0x4000
address: 0x6000
description: FMC ADC Mezzanine slot 1
filename: fmc_adc_mezzanine_mmap.cheby
- submap:
name: fmc2_adc_mezzanine
address: 0x6000
address: 0x8000
description: FMC ADC Mezzanine slot 2
filename: fmc_adc_mezzanine_mmap.cheby
hdl/cheby/svec_ref_fmc_adc_100Ms_mmap.vhd
View file @ 339ad9a0
......@@ -32,7 +32,7 @@ entity svec_ref_fmc_adc_100m_mmap is
end svec_ref_fmc_adc_100m_mmap;
architecture syn of svec_ref_fmc_adc_100m_mmap is
signal adr_int : std_logic_vector(14 downto 2);
signal adr_int : std_logic_vector(15 downto 2);
signal rd_req_int : std_logic;
signal wr_req_int : std_logic;
signal rd_ack_int : std_logic;
......@@ -63,7 +63,7 @@ architecture syn of svec_ref_fmc_adc_100m_mmap is
signal fmc2_adc_mezzanine_wack : std_logic;
signal fmc2_adc_mezzanine_rack : std_logic;
signal rd_req_d0 : std_logic;
signal rd_adr_d0 : std_logic_vector(14 downto 2);
signal rd_adr_d0 : std_logic_vector(15 downto 2);
signal rd_ack_d0 : std_logic;
signal rd_dat_d0 : std_logic_vector(31 downto 0);
signal wr_req_d0 : std_logic;
......@@ -73,7 +73,7 @@ architecture syn of svec_ref_fmc_adc_100m_mmap is
begin
-- WB decode signals
adr_int <= wb_i.adr(14 downto 2);
adr_int <= wb_i.adr(15 downto 2);
wb_en <= wb_i.cyc and wb_i.stb;
process (clk_i) begin
......@@ -196,16 +196,16 @@ begin
metadata_we <= '0';
fmc1_adc_mezzanine_we <= '0';
fmc2_adc_mezzanine_we <= '0';
case rd_adr_d0(14 downto 13) is
when "01" =>
case rd_adr_d0(15 downto 13) is
when "010" =>
-- Submap metadata
metadata_we <= wr_req_d0;
wr_ack_d0 <= metadata_wack;
when "10" =>
when "011" =>
-- Submap fmc1_adc_mezzanine
fmc1_adc_mezzanine_we <= wr_req_d0;
wr_ack_d0 <= fmc1_adc_mezzanine_wack;
when "11" =>
when "100" =>
-- Submap fmc2_adc_mezzanine
fmc2_adc_mezzanine_we <= wr_req_d0;
wr_ack_d0 <= fmc2_adc_mezzanine_wack;
......@@ -221,18 +221,18 @@ begin
metadata_re <= '0';
fmc1_adc_mezzanine_re <= '0';
fmc2_adc_mezzanine_re <= '0';
case rd_adr_d0(14 downto 13) is
when "01" =>
case rd_adr_d0(15 downto 13) is
when "010" =>
-- Submap metadata
metadata_re <= rd_req_d0;
rd_dat_d0 <= metadata_i.dat;
rd_ack_d0 <= metadata_rack;
when "10" =>
when "011" =>
-- Submap fmc1_adc_mezzanine
fmc1_adc_mezzanine_re <= rd_req_d0;
rd_dat_d0 <= fmc1_adc_mezzanine_i.dat;
rd_ack_d0 <= fmc1_adc_mezzanine_rack;
when "11" =>
when "100" =>
-- Submap fmc2_adc_mezzanine
fmc2_adc_mezzanine_re <= rd_req_d0;
rd_dat_d0 <= fmc2_adc_mezzanine_i.dat;
......
svec @ 577b31c8
Subproject commit 3171ceaa70f7c598ff953cc413434826e56e85ff
Subproject commit 577b31c8b1dc530aa145a8a49ab10dff7e9483b1
hdl/testbench/include/svec_ref_fmc_adc_100Ms_mmap.v
View file @ 339ad9a0
......@@ -2,10 +2,10 @@
//
// SPDX-License-Identifier: CC0-1.0
`define SVEC_REF_FMC_ADC_100M_MMAP_SIZE 32768
`define ADDR_SVEC_REF_FMC_ADC_100M_MMAP_METADATA 'h2000
`define SVEC_REF_FMC_ADC_100M_MMAP_SIZE 65536
`define ADDR_SVEC_REF_FMC_ADC_100M_MMAP_METADATA 'h4000
`define SVEC_REF_FMC_ADC_100M_MMAP_METADATA_SIZE 64
`define ADDR_SVEC_REF_FMC_ADC_100M_MMAP_FMC1_ADC_MEZZANINE 'h4000
`define ADDR_SVEC_REF_FMC_ADC_100M_MMAP_FMC1_ADC_MEZZANINE 'h6000
`define SVEC_REF_FMC_ADC_100M_MMAP_FMC1_ADC_MEZZANINE_SIZE 8192
`define ADDR_SVEC_REF_FMC_ADC_100M_MMAP_FMC2_ADC_MEZZANINE 'h6000
`define ADDR_SVEC_REF_FMC_ADC_100M_MMAP_FMC2_ADC_MEZZANINE 'h8000
`define SVEC_REF_FMC_ADC_100M_MMAP_FMC2_ADC_MEZZANINE_SIZE 8192
hdl/testbench/svec_ref_design/main.sv
View file @ 339ad9a0
......@@ -363,6 +363,33 @@ module main;
wait (acq_fsm_state == 1);
$display("<%t> END ACQ 1/4", $realtime);
#100ns;
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES, 'h00000004);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES, 'h00000008);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SHOTS, 'h00000001);
val = (1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_CH1_OFFSET);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_EN, val);
$display("<%t> START ACQ 1b/4", $realtime);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CTL, 'h00000001); // FSM sta
#1us;
wait (acq_fsm_state == 1);
$display("<%t> END ACQ 1b/4", $realtime);
// TODO: check results (they are only displayed)
acc.read(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_POS, val);
$display("trig pos: %x", val);
acc.write(`VME_OFFSET + 16'h58, val);
for(i = 0; i < 8*2 + 4; i+=1) begin
acc.read(`VME_OFFSET + 16'h2000, val);
$display("%d: %08x", i, val);
end
$stop;
#200ns;
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SHOTS, 'h00000003); // #nshots: 3x multi-shot acq
......
hdl/top/svec_ref_design/svec_ref_fmc_adc_100Ms.vhd
View file @ 339ad9a0
......@@ -240,7 +240,7 @@ architecture arch of svec_ref_fmc_adc_100Ms is
constant c_WB_SLAVE_FMC1_ADC : integer := 2; -- FMC slot 2 ADC mezzanine
-- Convention metadata base address
constant c_METADATA_ADDR : t_wishbone_address := x"0000_2000";
constant c_METADATA_ADDR : t_wishbone_address := x"0000_4000";
------------------------------------------------------------------------------
-- Signals declaration
......@@ -309,6 +309,7 @@ begin -- architecture arch
inst_svec_base : entity work.svec_base_wr
generic map (
g_DECODE_AM => FALSE,
g_WITH_VIC => TRUE,
g_WITH_ONEWIRE => FALSE,
g_WITH_SPI => FALSE,
......@@ -475,7 +476,7 @@ begin -- architecture arch
generic map (
g_VENDOR_ID => x"0000_10DC",
g_DEVICE_ID => x"4144_4302", -- "ADC2"
g_VERSION => x"0500_0000",
g_VERSION => x"0500_0002",
g_CAPABILITIES => x"0000_0000",
g_COMMIT_ID => (others => '0'))
port map (
......
software/include/hw/fmc_adc_100Ms_channel_regs.h 0 → 100644
View file @ 339ad9a0
#ifndef __CHEBY__FMC_ADC_100MS_CHANNEL_REGS__H__
#define __CHEBY__FMC_ADC_100MS_CHANNEL_REGS__H__
#define FMC_ADC_100MS_CHANNEL_REGS_SIZE 24 /* 0x18 */
/* Channel control register */
#define FMC_ADC_100MS_CHANNEL_REGS_CTL 0x0UL
#define FMC_ADC_100MS_CHANNEL_REGS_CTL_SSR_MASK 0x7fUL
#define FMC_ADC_100MS_CHANNEL_REGS_CTL_SSR_SHIFT 0
/* Channel status register */
#define FMC_ADC_100MS_CHANNEL_REGS_STA 0x4UL
#define FMC_ADC_100MS_CHANNEL_REGS_STA_VAL_MASK 0xffffUL
#define FMC_ADC_100MS_CHANNEL_REGS_STA_VAL_SHIFT 0
/* Channel calibration register */
#define FMC_ADC_100MS_CHANNEL_REGS_CALIB 0x8UL
#define FMC_ADC_100MS_CHANNEL_REGS_CALIB_GAIN_MASK 0xffffUL
#define FMC_ADC_100MS_CHANNEL_REGS_CALIB_GAIN_SHIFT 0
#define FMC_ADC_100MS_CHANNEL_REGS_CALIB_OFFSET_MASK 0xffff0000UL
#define FMC_ADC_100MS_CHANNEL_REGS_CALIB_OFFSET_SHIFT 16
/* Channel saturation register */
#define FMC_ADC_100MS_CHANNEL_REGS_SAT 0xcUL
#define FMC_ADC_100MS_CHANNEL_REGS_SAT_VAL_MASK 0x7fffUL
#define FMC_ADC_100MS_CHANNEL_REGS_SAT_VAL_SHIFT 0
/* Channel trigger threshold configuration register */
#define FMC_ADC_100MS_CHANNEL_REGS_TRIG_THRES 0x10UL
#define FMC_ADC_100MS_CHANNEL_REGS_TRIG_THRES_VAL_MASK 0xffffUL
#define FMC_ADC_100MS_CHANNEL_REGS_TRIG_THRES_VAL_SHIFT 0
#define FMC_ADC_100MS_CHANNEL_REGS_TRIG_THRES_HYST_MASK 0xffff0000UL
#define FMC_ADC_100MS_CHANNEL_REGS_TRIG_THRES_HYST_SHIFT 16
/* Channel trigger delay */
#define FMC_ADC_100MS_CHANNEL_REGS_TRIG_DLY 0x14UL
struct fmc_adc_100ms_channel_regs {
/* [0x0]: REG (rw) Channel control register */
uint32_t ctl;
/* [0x4]: REG (ro) Channel status register */
uint32_t sta;
/* [0x8]: REG (rw) Channel calibration register */
uint32_t calib;
/* [0xc]: REG (rw) Channel saturation register */
uint32_t sat;
/* [0x10]: REG (rw) Channel trigger threshold configuration register */
uint32_t trig_thres;
/* [0x14]: REG (rw) Channel trigger delay */
uint32_t trig_dly;
};
#endif /* __CHEBY__FMC_ADC_100MS_CHANNEL_REGS__H__ */
software/include/hw/fmc_adc_100Ms_csr.h 0 → 100644
View file @ 339ad9a0
#ifndef __CHEBY__FMC_ADC_100MS_CSR__H__
#define __CHEBY__FMC_ADC_100MS_CSR__H__
#include "fmc_adc_100ms_channel_regs.h"
#define FMC_ADC_100MS_CSR_SIZE 512 /* 0x200 */
/* Control register */
#define FMC_ADC_100MS_CSR_CTL 0x0UL
#define FMC_ADC_100MS_CSR_CTL_FSM_CMD_MASK 0x3UL
#define FMC_ADC_100MS_CSR_CTL_FSM_CMD_SHIFT 0
#define FMC_ADC_100MS_CSR_CTL_FMC_CLK_OE 0x4UL
#define FMC_ADC_100MS_CSR_CTL_OFFSET_DAC_CLR_N 0x8UL
#define FMC_ADC_100MS_CSR_CTL_MAN_BITSLIP 0x10UL
#define FMC_ADC_100MS_CSR_CTL_TRIG_LED 0x40UL
#define FMC_ADC_100MS_CSR_CTL_ACQ_LED 0x80UL
#define FMC_ADC_100MS_CSR_CTL_CLEAR_TRIG_STAT 0x100UL
#define FMC_ADC_100MS_CSR_CTL_CALIB_APPLY 0x8000UL
/* Status register */
#define FMC_ADC_100MS_CSR_STA 0x4UL
#define FMC_ADC_100MS_CSR_STA_FSM_MASK 0x7UL
#define FMC_ADC_100MS_CSR_STA_FSM_SHIFT 0
#define FMC_ADC_100MS_CSR_STA_SERDES_PLL 0x8UL
#define FMC_ADC_100MS_CSR_STA_SERDES_SYNCED 0x10UL
#define FMC_ADC_100MS_CSR_STA_ACQ_CFG 0x20UL
#define FMC_ADC_100MS_CSR_STA_FMC_NR_MASK 0xc0UL
#define FMC_ADC_100MS_CSR_STA_FMC_NR_SHIFT 6
#define FMC_ADC_100MS_CSR_STA_CALIB_BUSY 0x8000UL
/* Trigger status */
#define FMC_ADC_100MS_CSR_TRIG_STAT 0x8UL
#define FMC_ADC_100MS_CSR_TRIG_STAT_EXT 0x1UL
#define FMC_ADC_100MS_CSR_TRIG_STAT_SW 0x2UL
#define FMC_ADC_100MS_CSR_TRIG_STAT_TIME 0x10UL
#define FMC_ADC_100MS_CSR_TRIG_STAT_CH1 0x100UL
#define FMC_ADC_100MS_CSR_TRIG_STAT_CH2 0x200UL
#define FMC_ADC_100MS_CSR_TRIG_STAT_CH3 0x400UL
#define FMC_ADC_100MS_CSR_TRIG_STAT_CH4 0x800UL
/* Trigger enable */
#define FMC_ADC_100MS_CSR_TRIG_EN 0xcUL
#define FMC_ADC_100MS_CSR_TRIG_EN_EXT 0x1UL
#define FMC_ADC_100MS_CSR_TRIG_EN_SW 0x2UL
#define FMC_ADC_100MS_CSR_TRIG_EN_TIME 0x10UL
#define FMC_ADC_100MS_CSR_TRIG_EN_AUX_TIME 0x20UL
#define FMC_ADC_100MS_CSR_TRIG_EN_CH1 0x100UL
#define FMC_ADC_100MS_CSR_TRIG_EN_CH2 0x200UL
#define FMC_ADC_100MS_CSR_TRIG_EN_CH3 0x400UL
#define FMC_ADC_100MS_CSR_TRIG_EN_CH4 0x800UL
/* Trigger polarity */
#define FMC_ADC_100MS_CSR_TRIG_POL 0x10UL
#define FMC_ADC_100MS_CSR_TRIG_POL_EXT 0x1UL
#define FMC_ADC_100MS_CSR_TRIG_POL_CH1 0x100UL
#define FMC_ADC_100MS_CSR_TRIG_POL_CH2 0x200UL
#define FMC_ADC_100MS_CSR_TRIG_POL_CH3 0x400UL
#define FMC_ADC_100MS_CSR_TRIG_POL_CH4 0x800UL
/* External trigger delay */
#define FMC_ADC_100MS_CSR_EXT_TRIG_DLY 0x14UL
/* Software trigger */
#define FMC_ADC_100MS_CSR_SW_TRIG 0x18UL
/* Number of shots */
#define FMC_ADC_100MS_CSR_SHOTS 0x1cUL
#define FMC_ADC_100MS_CSR_SHOTS_NBR_MASK 0xffffUL
#define FMC_ADC_100MS_CSR_SHOTS_NBR_SHIFT 0
#define FMC_ADC_100MS_CSR_SHOTS_REMAIN_MASK 0xffff0000UL
#define FMC_ADC_100MS_CSR_SHOTS_REMAIN_SHIFT 16
/* Multi-shot sample depth register */
#define FMC_ADC_100MS_CSR_MULTI_DEPTH 0x20UL
/* Trigger address register */
#define FMC_ADC_100MS_CSR_TRIG_POS 0x24UL
/* Sampling clock frequency */
#define FMC_ADC_100MS_CSR_FS_FREQ 0x28UL
/* Downsampling ratio */
#define FMC_ADC_100MS_CSR_DOWNSAMPLE 0x2cUL
/* Pre-trigger samples */
#define FMC_ADC_100MS_CSR_PRE_SAMPLES 0x30UL
/* Post-trigger samples */
#define FMC_ADC_100MS_CSR_POST_SAMPLES 0x34UL
/* Samples counter */
#define FMC_ADC_100MS_CSR_SAMPLES_CNT 0x38UL
/* Channel 1 registers */
#define FMC_ADC_100MS_CSR_FMC_ADC_CH1 0x80UL
#define FMC_ADC_100MS_CSR_FMC_ADC_CH1_SIZE 32 /* 0x20 */
/* Channel 2 registers */
#define FMC_ADC_100MS_CSR_FMC_ADC_CH2 0xc0UL
#define FMC_ADC_100MS_CSR_FMC_ADC_CH2_SIZE 32 /* 0x20 */
/* Channel 3 registers */
#define FMC_ADC_100MS_CSR_FMC_ADC_CH3 0x100UL
#define FMC_ADC_100MS_CSR_FMC_ADC_CH3_SIZE 32 /* 0x20 */
/* Channel 4 registers */
#define FMC_ADC_100MS_CSR_FMC_ADC_CH4 0x140UL
#define FMC_ADC_100MS_CSR_FMC_ADC_CH4_SIZE 32 /* 0x20 */
struct fmc_adc_100ms_csr {
/* [0x0]: REG (rw) Control register */
uint32_t ctl;
/* [0x4]: REG (ro) Status register */
uint32_t sta;
/* [0x8]: REG (ro) Trigger status */
uint32_t trig_stat;
/* [0xc]: REG (rw) Trigger enable */
uint32_t trig_en;
/* [0x10]: REG (rw) Trigger polarity */
uint32_t trig_pol;
/* [0x14]: REG (rw) External trigger delay */
uint32_t ext_trig_dly;
/* [0x18]: REG (wo) Software trigger */
uint32_t sw_trig;
/* [0x1c]: REG (rw) Number of shots */
uint32_t shots;
/* [0x20]: REG (ro) Multi-shot sample depth register */
uint32_t multi_depth;
/* [0x24]: REG (ro) Trigger address register */
uint32_t trig_pos;
/* [0x28]: REG (ro) Sampling clock frequency */
uint32_t fs_freq;
/* [0x2c]: REG (rw) Downsampling ratio */
uint32_t downsample;
/* [0x30]: REG (rw) Pre-trigger samples */
uint32_t pre_samples;
/* [0x34]: REG (rw) Post-trigger samples */
uint32_t post_samples;
/* [0x38]: REG (ro) Samples counter */
uint32_t samples_cnt;
/* padding to: 32 words */
uint32_t __padding_0[17];
/* [0x80]: SUBMAP Channel 1 registers */
struct fmc_adc_100ms_channel_regs fmc_adc_ch1;
/* padding to: 48 words */
uint32_t __padding_1[10];
/* [0xc0]: SUBMAP Channel 2 registers */
struct fmc_adc_100ms_channel_regs fmc_adc_ch2;
/* padding to: 64 words */
uint32_t __padding_2[10];
/* [0x100]: SUBMAP Channel 3 registers */
struct fmc_adc_100ms_channel_regs fmc_adc_ch3;
/* padding to: 80 words */
uint32_t __padding_3[10];
/* [0x140]: SUBMAP Channel 4 registers */
struct fmc_adc_100ms_channel_regs fmc_adc_ch4;
/* padding to: 80 words */
uint32_t __padding_4[42];
};
#endif /* __CHEBY__FMC_ADC_100MS_CSR__H__ */
software/include/hw/fmc_adc_aux_trigin.h 0 → 100644
View file @ 339ad9a0
#ifndef __CHEBY__AUX_TRIGIN__H__
#define __CHEBY__AUX_TRIGIN__H__
#define AUX_TRIGIN_SIZE 20 /* 0x14 */
/* Core version */
#define AUX_TRIGIN_VERSION 0x0UL
#define AUX_TRIGIN_VERSION_PRESET 0xadc10001UL
/* Control register */
#define AUX_TRIGIN_CTRL 0x4UL
#define AUX_TRIGIN_CTRL_ENABLE 0x1UL
/* Time (seconds) to trigger */
#define AUX_TRIGIN_SECONDS 0x8UL
/* Time (cycles) to trigger */
#define AUX_TRIGIN_CYCLES 0x10UL
struct aux_trigin {
/* [0x0]: REG (ro) Core version */
uint32_t version;
/* [0x4]: REG (rw) Control register */
uint32_t ctrl;
/* [0x8]: REG (rw) Time (seconds) to trigger */
uint64_t seconds;
/* [0x10]: REG (rw) Time (cycles) to trigger */
uint32_t cycles;
};
#endif /* __CHEBY__AUX_TRIGIN__H__ */
software/include/hw/fmc_adc_aux_trigout.h 0 → 100644
View file @ 339ad9a0
#ifndef __CHEBY__AUX_TRIGOUT__H__
#define __CHEBY__AUX_TRIGOUT__H__
#define AUX_TRIGOUT_SIZE 20 /* 0x14 */
/* Status register */
#define AUX_TRIGOUT_STATUS 0x0UL
#define AUX_TRIGOUT_WR_ENABLE 0x1UL
#define AUX_TRIGOUT_WR_LINK 0x2UL
#define AUX_TRIGOUT_WR_VALID 0x4UL
#define AUX_TRIGOUT_TS_PRESENT 0x100UL
/* Time (seconds) of the last event */
#define AUX_TRIGOUT_TS_MASK_SEC 0x8UL
#define AUX_TRIGOUT_TS_SEC_MASK 0xffffffffffULL
#define AUX_TRIGOUT_TS_SEC_SHIFT 0
#define AUX_TRIGOUT_CH1_MASK 0x1000000000000ULL
#define AUX_TRIGOUT_CH2_MASK 0x2000000000000ULL
#define AUX_TRIGOUT_CH3_MASK 0x4000000000000ULL
#define AUX_TRIGOUT_CH4_MASK 0x8000000000000ULL
#define AUX_TRIGOUT_EXT_MASK 0x100000000000000ULL
/* Cycles part of timestamp fifo. */
#define AUX_TRIGOUT_TS_CYCLES 0x10UL
#define AUX_TRIGOUT_CYCLES_MASK 0xfffffffUL
#define AUX_TRIGOUT_CYCLES_SHIFT 0
struct aux_trigout {
/* [0x0]: REG (ro) Status register */
uint32_t status;
/* padding to: 2 words */
uint32_t __padding_0[1];
/* [0x8]: REG (ro) Time (seconds) of the last event */
uint64_t ts_mask_sec;
/* [0x10]: REG (ro) Cycles part of timestamp fifo. */
uint32_t ts_cycles;
};
#endif /* __CHEBY__AUX_TRIGOUT__H__ */
software/include/hw/fmc_adc_eic_regs.h 0 → 100644
View file @ 339ad9a0
#ifndef __CHEBY__FMC_ADC_EIC_REGS__H__
#define __CHEBY__FMC_ADC_EIC_REGS__H__
#define FMC_ADC_EIC_REGS_SIZE 16 /* 0x10 */
/* Interrupt Disable Register */
#define FMC_ADC_EIC_REGS_IDR 0x0UL
/* Interrupt Enable Register */
#define FMC_ADC_EIC_REGS_IER 0x4UL
/* Interrupt Mask Register */
#define FMC_ADC_EIC_REGS_IMR 0x8UL
/* Interrupt Status Register */
#define FMC_ADC_EIC_REGS_ISR 0xcUL
struct fmc_adc_eic_regs {
/* [0x0]: REG (wo) Interrupt Disable Register */
uint32_t idr;
/* [0x4]: REG (wo) Interrupt Enable Register */
uint32_t ier;
/* [0x8]: REG (ro) Interrupt Mask Register */
uint32_t imr;
/* [0xc]: REG (rw) Interrupt Status Register */
uint32_t isr;
};
#endif /* __CHEBY__FMC_ADC_EIC_REGS__H__ */
software/include/hw/fmc_adc_mezzanine_mmap.h 0 → 100644
View file @ 339ad9a0
#ifndef __CHEBY__FMC_ADC_MEZZANINE_MMAP__H__
#define __CHEBY__FMC_ADC_MEZZANINE_MMAP__H__
#include "fmc_adc_eic_regs.h"
#include "fmc_adc_100ms_csr.h"
#include "timetag_core_regs.h"
#include "wb_ds182x_regs.h"
#define FMC_ADC_MEZZANINE_MMAP_SIZE 8192 /* 0x2000 = 8KB */
/* FMC ADC 100M CSR */
#define FMC_ADC_MEZZANINE_MMAP_FMC_ADC_100M_CSR 0x1000UL
#define FMC_ADC_MEZZANINE_MMAP_FMC_ADC_100M_CSR_SIZE 512 /* 0x200 */
/* FMC ADC Embedded Interrupt Controller */
#define FMC_ADC_MEZZANINE_MMAP_FMC_ADC_EIC 0x1500UL
#define FMC_ADC_MEZZANINE_MMAP_FMC_ADC_EIC_SIZE 16 /* 0x10 */
/* Si570 control I2C master */
#define FMC_ADC_MEZZANINE_MMAP_SI570_I2C_MASTER 0x1600UL
#define FMC_ADC_MEZZANINE_MMAP_SI570_I2C_MASTER_SIZE 256 /* 0x100 */
/* DS18B20 OneWire master */
#define FMC_ADC_MEZZANINE_MMAP_DS18B20_ONEWIRE_MASTER 0x1700UL
#define FMC_ADC_MEZZANINE_MMAP_DS18B20_ONEWIRE_MASTER_SIZE 16 /* 0x10 */
/* Mezzanine SPI master (ADC control + DAC offsets) */
#define FMC_ADC_MEZZANINE_MMAP_FMC_SPI_MASTER 0x1800UL
#define FMC_ADC_MEZZANINE_MMAP_FMC_SPI_MASTER_SIZE 32 /* 0x20 */
/* Timetag Core */
#define FMC_ADC_MEZZANINE_MMAP_TIMETAG_CORE 0x1900UL
#define FMC_ADC_MEZZANINE_MMAP_TIMETAG_CORE_SIZE 128 /* 0x80 */
struct fmc_adc_mezzanine_mmap {
/* padding to: 1024 words */
uint32_t __padding_0[1024];
/* [0x1000]: SUBMAP FMC ADC 100M CSR */
struct fmc_adc_100ms_csr fmc_adc_100m_csr;
/* padding to: 1344 words */
uint32_t __padding_1[192];
/* [0x1500]: SUBMAP FMC ADC Embedded Interrupt Controller */
struct fmc_adc_eic_regs fmc_adc_eic;
/* padding to: 1408 words */
uint32_t __padding_2[60];
/* [0x1600]: SUBMAP Si570 control I2C master */
uint32_t si570_i2c_master[64];
/* [0x1700]: SUBMAP DS18B20 OneWire master */
struct wb_ds182x_regs ds18b20_onewire_master;
/* padding to: 1536 words */
uint32_t __padding_3[60];
/* [0x1800]: SUBMAP Mezzanine SPI master (ADC control + DAC offsets) */
uint32_t fmc_spi_master[8];
/* padding to: 1600 words */
uint32_t __padding_4[56];
/* [0x1900]: SUBMAP Timetag Core */
struct timetag_core_regs timetag_core;
/* padding to: 1600 words */
uint32_t __padding_5[416];
};
#endif /* __CHEBY__FMC_ADC_MEZZANINE_MMAP__H__ */
software/include/hw/spec_ref_fmc_adc_100Ms_mmap.h 0 → 100644
View file @ 339ad9a0
#ifndef __CHEBY__SPEC_REF_FMC_ADC_100M_MMAP__H__
#define __CHEBY__SPEC_REF_FMC_ADC_100M_MMAP__H__
#include "fmc_adc_mezzanine_mmap.h"
#define SPEC_REF_FMC_ADC_100M_MMAP_SIZE 24576 /* 0x6000 = 24KB */
/* a ROM containing the application metadata */
#define SPEC_REF_FMC_ADC_100M_MMAP_METADATA 0x2000UL
#define SPEC_REF_FMC_ADC_100M_MMAP_METADATA_SIZE 64 /* 0x40 */
/* FMC ADC Mezzanine */
#define SPEC_REF_FMC_ADC_100M_MMAP_FMC_ADC_MEZZANINE 0x4000UL
#define SPEC_REF_FMC_ADC_100M_MMAP_FMC_ADC_MEZZANINE_SIZE 8192 /* 0x2000 = 8KB */
struct spec_ref_fmc_adc_100m_mmap {
/* padding to: 2048 words */
uint32_t __padding_0[2048];
/* [0x2000]: SUBMAP a ROM containing the application metadata */
uint32_t metadata[16];
/* padding to: 4096 words */
uint32_t __padding_1[2032];
/* [0x4000]: SUBMAP FMC ADC Mezzanine */
struct fmc_adc_mezzanine_mmap fmc_adc_mezzanine;
};
#endif /* __CHEBY__SPEC_REF_FMC_ADC_100M_MMAP__H__ */
software/include/hw/svec_ref_fmc_adc_100Ms_mmap.h 0 → 100644
View file @ 339ad9a0
#ifndef __CHEBY__SVEC_REF_FMC_ADC_100M_MMAP__H__
#define __CHEBY__SVEC_REF_FMC_ADC_100M_MMAP__H__
#include "fmc_adc_mezzanine_mmap.h"
#define SVEC_REF_FMC_ADC_100M_MMAP_SIZE 65536 /* 0x10000 = 64KB */
/* a ROM containing the application metadata */
#define SVEC_REF_FMC_ADC_100M_MMAP_METADATA 0x4000UL
#define SVEC_REF_FMC_ADC_100M_MMAP_METADATA_SIZE 64 /* 0x40 */
/* FMC ADC Mezzanine slot 1 */
#define SVEC_REF_FMC_ADC_100M_MMAP_FMC1_ADC_MEZZANINE 0x6000UL
#define SVEC_REF_FMC_ADC_100M_MMAP_FMC1_ADC_MEZZANINE_SIZE 8192 /* 0x2000 = 8KB */
/* FMC ADC Mezzanine slot 2 */
#define SVEC_REF_FMC_ADC_100M_MMAP_FMC2_ADC_MEZZANINE 0x8000UL
#define SVEC_REF_FMC_ADC_100M_MMAP_FMC2_ADC_MEZZANINE_SIZE 8192 /* 0x2000 = 8KB */
struct svec_ref_fmc_adc_100m_mmap {
/* padding to: 4096 words */
uint32_t __padding_0[4096];
/* [0x4000]: SUBMAP a ROM containing the application metadata */
uint32_t metadata[16];
/* padding to: 6144 words */
uint32_t __padding_1[2032];
/* [0x6000]: SUBMAP FMC ADC Mezzanine slot 1 */
struct fmc_adc_mezzanine_mmap fmc1_adc_mezzanine;
/* [0x8000]: SUBMAP FMC ADC Mezzanine slot 2 */
struct fmc_adc_mezzanine_mmap fmc2_adc_mezzanine;
/* padding to: 8192 words */
uint32_t __padding_2[6144];
};
#endif /* __CHEBY__SVEC_REF_FMC_ADC_100M_MMAP__H__ */
software/include/hw/timetag_core_regs.h 0 → 100644
View file @ 339ad9a0
#ifndef __CHEBY__TIMETAG_CORE_REGS__H__
#define __CHEBY__TIMETAG_CORE_REGS__H__
#define TIMETAG_CORE_REGS_SIZE 128 /* 0x80 */
/* Timetag seconds register (upper) */
#define TIMETAG_CORE_REGS_SECONDS_UPPER 0x0UL
#define TIMETAG_CORE_REGS_SECONDS_UPPER_MASK 0xffUL
#define TIMETAG_CORE_REGS_SECONDS_UPPER_SHIFT 0
/* Timetag seconds register (lower) */
#define TIMETAG_CORE_REGS_SECONDS_LOWER 0x4UL
/* Timetag coarse time register, system clock ticks (125MHz) */
#define TIMETAG_CORE_REGS_COARSE 0x8UL
#define TIMETAG_CORE_REGS_COARSE_MASK 0xfffffffUL
#define TIMETAG_CORE_REGS_COARSE_SHIFT 0
/* Time trigger seconds register (upper) */
#define TIMETAG_CORE_REGS_TIME_TRIG_SECONDS_UPPER 0xcUL
#define TIMETAG_CORE_REGS_TIME_TRIG_SECONDS_UPPER_MASK 0xffUL
#define TIMETAG_CORE_REGS_TIME_TRIG_SECONDS_UPPER_SHIFT 0
/* Time trigger seconds register (lower) */
#define TIMETAG_CORE_REGS_TIME_TRIG_SECONDS_LOWER 0x10UL
/* Time trigger coarse time register, system clock ticks (125MHz) */
#define TIMETAG_CORE_REGS_TIME_TRIG_COARSE 0x14UL
#define TIMETAG_CORE_REGS_TIME_TRIG_COARSE_MASK 0xfffffffUL
#define TIMETAG_CORE_REGS_TIME_TRIG_COARSE_SHIFT 0
/* Trigger time-tag seconds register (upper) */
#define TIMETAG_CORE_REGS_TRIG_TAG_SECONDS_UPPER 0x18UL
#define TIMETAG_CORE_REGS_TRIG_TAG_SECONDS_UPPER_MASK 0xffUL
#define TIMETAG_CORE_REGS_TRIG_TAG_SECONDS_UPPER_SHIFT 0
/* Trigger time-tag seconds register (lower) */
#define TIMETAG_CORE_REGS_TRIG_TAG_SECONDS_LOWER 0x1cUL
/* Trigger time-tag coarse time (system clock ticks 125MHz) register */
#define TIMETAG_CORE_REGS_TRIG_TAG_COARSE 0x20UL
#define TIMETAG_CORE_REGS_TRIG_TAG_COARSE_MASK 0xfffffffUL
#define TIMETAG_CORE_REGS_TRIG_TAG_COARSE_SHIFT 0
/* Acquisition start time-tag seconds register (upper) */
#define TIMETAG_CORE_REGS_ACQ_START_TAG_SECONDS_UPPER 0x24UL
#define TIMETAG_CORE_REGS_ACQ_START_TAG_SECONDS_UPPER_MASK 0xffUL
#define TIMETAG_CORE_REGS_ACQ_START_TAG_SECONDS_UPPER_SHIFT 0
/* Acquisition start time-tag seconds register (lower) */
#define TIMETAG_CORE_REGS_ACQ_START_TAG_SECONDS_LOWER 0x28UL
/* Acquisition start time-tag coarse time (system clock ticks 125MHz) register */
#define TIMETAG_CORE_REGS_ACQ_START_TAG_COARSE 0x2cUL
#define TIMETAG_CORE_REGS_ACQ_START_TAG_COARSE_MASK 0xfffffffUL
#define TIMETAG_CORE_REGS_ACQ_START_TAG_COARSE_SHIFT 0
/* Acquisition stop time-tag seconds register (upper) */
#define TIMETAG_CORE_REGS_ACQ_STOP_TAG_SECONDS_UPPER 0x30UL
#define TIMETAG_CORE_REGS_ACQ_STOP_TAG_SECONDS_UPPER_MASK 0xffUL
#define TIMETAG_CORE_REGS_ACQ_STOP_TAG_SECONDS_UPPER_SHIFT 0
/* Acquisition stop time-tag seconds register (lower) */
#define TIMETAG_CORE_REGS_ACQ_STOP_TAG_SECONDS_LOWER 0x34UL
/* Acquisition stop time-tag coarse time (system clock ticks 125MHz) register */
#define TIMETAG_CORE_REGS_ACQ_STOP_TAG_COARSE 0x38UL
#define TIMETAG_CORE_REGS_ACQ_STOP_TAG_COARSE_MASK 0xfffffffUL
#define TIMETAG_CORE_REGS_ACQ_STOP_TAG_COARSE_SHIFT 0
/* Acquisition end time-tag seconds register (upper) */
#define TIMETAG_CORE_REGS_ACQ_END_TAG_SECONDS_UPPER 0x3cUL
#define TIMETAG_CORE_REGS_ACQ_END_TAG_SECONDS_UPPER_MASK 0xffUL
#define TIMETAG_CORE_REGS_ACQ_END_TAG_SECONDS_UPPER_SHIFT 0
/* Acquisition end time-tag seconds register (lower) */
#define TIMETAG_CORE_REGS_ACQ_END_TAG_SECONDS_LOWER 0x40UL
/* Acquisition end time-tag coarse time (system clock ticks 125MHz) register */
#define TIMETAG_CORE_REGS_ACQ_END_TAG_COARSE 0x44UL
#define TIMETAG_CORE_REGS_ACQ_END_TAG_COARSE_MASK 0xfffffffUL
#define TIMETAG_CORE_REGS_ACQ_END_TAG_COARSE_SHIFT 0
struct timetag_core_regs {
/* [0x0]: REG (rw) Timetag seconds register (upper) */
uint32_t seconds_upper;
/* [0x4]: REG (rw) Timetag seconds register (lower) */
uint32_t seconds_lower;
/* [0x8]: REG (rw) Timetag coarse time register, system clock ticks (125MHz) */
uint32_t coarse;
/* [0xc]: REG (rw) Time trigger seconds register (upper) */
uint32_t time_trig_seconds_upper;
/* [0x10]: REG (rw) Time trigger seconds register (lower) */
uint32_t time_trig_seconds_lower;
/* [0x14]: REG (rw) Time trigger coarse time register, system clock ticks (125MHz) */
uint32_t time_trig_coarse;
/* [0x18]: REG (ro) Trigger time-tag seconds register (upper) */
uint32_t trig_tag_seconds_upper;
/* [0x1c]: REG (ro) Trigger time-tag seconds register (lower) */
uint32_t trig_tag_seconds_lower;
/* [0x20]: REG (ro) Trigger time-tag coarse time (system clock ticks 125MHz) register */
uint32_t trig_tag_coarse;
/* [0x24]: REG (ro) Acquisition start time-tag seconds register (upper) */
uint32_t acq_start_tag_seconds_upper;
/* [0x28]: REG (ro) Acquisition start time-tag seconds register (lower) */
uint32_t acq_start_tag_seconds_lower;
/* [0x2c]: REG (ro) Acquisition start time-tag coarse time (system clock ticks 125MHz) register */
uint32_t acq_start_tag_coarse;
/* [0x30]: REG (ro) Acquisition stop time-tag seconds register (upper) */
uint32_t acq_stop_tag_seconds_upper;
/* [0x34]: REG (ro) Acquisition stop time-tag seconds register (lower) */
uint32_t acq_stop_tag_seconds_lower;
/* [0x38]: REG (ro) Acquisition stop time-tag coarse time (system clock ticks 125MHz) register */
uint32_t acq_stop_tag_coarse;
/* [0x3c]: REG (ro) Acquisition end time-tag seconds register (upper) */
uint32_t acq_end_tag_seconds_upper;
/* [0x40]: REG (ro) Acquisition end time-tag seconds register (lower) */
uint32_t acq_end_tag_seconds_lower;
/* [0x44]: REG (ro) Acquisition end time-tag coarse time (system clock ticks 125MHz) register */
uint32_t acq_end_tag_coarse;
/* padding to: 17 words */
uint32_t __padding_0[14];
};
#endif /* __CHEBY__TIMETAG_CORE_REGS__H__ */
software/kernel/fa-core.c
View file @ 339ad9a0
......@@ -656,7 +656,8 @@ static void fa_sg_alloc_table_init(struct fa_dev *fa)
static struct fmc_adc_platform_data fmc_adc_pdata_default = {
.flags = 0,
.vme_ddr_offset = 0,
.vme_reg_offset = 0,
.vme_dma_offset = 0,
.calib_trig_time = 0,
.calib_trig_threshold = 0,
.calib_trig_internal = 0,
......
software/kernel/fa-dma.c
View file @ 339ad9a0
......@@ -214,8 +214,6 @@ static unsigned int zfad_block_n_pages(struct zio_block *block)
#ifdef CONFIG_FMC_ADC_SVEC
#define ADC_VME_DDR_ADDR 0x00
#define ADC_VME_DDR_DATA 0x04
#define SVEC_FUNC_NR 1 /* HARD coded in SVEC */
static inline struct vme_dev *fa_to_vme_dev(struct fa_dev *fa)
......@@ -233,9 +231,9 @@ static unsigned long fa_ddr_data_vme_addr(struct fa_dev *fa)
"Invalid VME function\n"))
return ~0; /* invalid address, we will see VME errors */
WARN(data->vme_ddr_offset == 0, "Invalid DDR DATA offset");
WARN(data->vme_dma_offset == 0, "Invalid DDR DMA offset");
addr = vdev->map[SVEC_FUNC_NR].vme_addrl;
addr += data->vme_ddr_offset + ADC_VME_DDR_DATA;
addr += data->vme_dma_offset;
return addr;
}
......@@ -251,7 +249,7 @@ static void *fa_ddr_addr_reg_off(struct fa_dev *fa)
return NULL; /* invalid address, we will see VME errors */
addr = vdev->map[SVEC_FUNC_NR].kernel_va;
addr += data->vme_ddr_offset + ADC_VME_DDR_ADDR;
addr += data->vme_reg_offset;
return addr;
}
......@@ -284,8 +282,7 @@ static void build_dma_desc(struct vme_dma *desc, unsigned long vme_addr,
desc->ctrl.vme_backoff_time = VME_DMA_BACKOFF_0;
vme->data_width = VME_D32;
vme->am = VME_A24_USER_DATA_SCT;
/*vme->am = VME_A24_USER_MBLT;*/
vme->am = VME_A24_USER_MBLT;
vme->addru = upper_32_bits(vme_addr);
vme->addrl = lower_32_bits(vme_addr);
......@@ -339,30 +336,27 @@ static int zfad_dma_context_init_svec(struct zio_cset *cset,
struct fa_dev *fa = cset->zdev->priv_d;
struct vme_dma *desc;
int err;
void *addr;
dev_dbg(&fa->pdev->dev, "SVEC build DMA context\n");
addr = fa_ddr_addr_reg_off(fa);
if (!addr) {
err = -ENODEV;
goto err_reg_addr;
}
desc = kmalloc(sizeof(struct vme_dma), GFP_ATOMIC);
if (!desc)
return -ENOMEM;
if (zfad_block == cset->interleave->priv_d) {
void *addr = fa_ddr_addr_reg_off(fa);
if (!addr) {
err = -ENODEV;
goto err_reg_addr;
}
/*
* Only for the first block:
* write the data address in the ddr_addr register: this
* address has been computed after ACQ_END by looking to the
* trigger position see fa-irq.c::irq_acq_end.
* Be careful: the SVEC HW version expects an address of 32bits word
* therefore mem-offset in byte is translated into 32bit word
*/
fa_iowrite(fa, zfad_block->sconfig.src_addr / 4, addr);
}
/*
* For the first block of each shot:
* write the start address to the ddr_reg register: this
* address has been computed after ACQ_END by looking to the
* trigger position see fa-irq.c::irq_acq_end.
*/
fa_iowrite(fa, zfad_block->sconfig.src_addr, addr);
zfad_block->dma_ctx = desc;
build_dma_desc(desc, fa_ddr_data_vme_addr(fa),
......
software/kernel/fmc-adc-100m14b4ch-svec-core.c
View file @ 339ad9a0
......@@ -23,15 +23,15 @@
*/
#define SVEC_BASE_REGS_CSR 0x40UL
#define SVEC_FPGA_CSR_DDR4_ADDR (SVEC_BASE_REGS_CSR + 0x18)
#define SVEC_FPGA_CSR_DDR4_DATA (SVEC_BASE_REGS_CSR + 0x1C)
#define SVEC_FPGA_CSR_DDR5_ADDR (SVEC_BASE_REGS_CSR + 0x20)
#define SVEC_FPGA_CSR_DDR5_DATA (SVEC_BASE_REGS_CSR + 0x24)
#define SVEC_FPGA_DDR4_DMA (0x2000)
#define SVEC_FPGA_CSR_DDR5_ADDR (SVEC_BASE_REGS_CSR + 0x1C)
#define SVEC_FPGA_DDR5_DMA (0x3000)
enum fa_svec_dev_offsets {
FA_SVEC_ADC1_MEM_START = 0x000002000,
FA_SVEC_ADC1_MEM_END = 0x00003FFF,
FA_SVEC_ADC1_MEM_START = 0x00002000,
FA_SVEC_ADC1_MEM_END = 0x00003FFF,
FA_SVEC_ADC2_MEM_START = 0x00004000,
FA_SVEC_ADC2_MEM_END = 0x000005FFF,
FA_SVEC_ADC2_MEM_END = 0x00005FFF,
};
static inline struct platform_device *platform_device_register_resndata_mask(
......@@ -59,7 +59,8 @@ static struct fmc_adc_platform_data fa_svec_adc_pdata[] = {
.flags = FMC_ADC_BIG_ENDIAN |
FMC_ADC_SVEC |
FMC_ADC_NOSQUASH_SCATTERLIST,
.vme_ddr_offset = SVEC_FPGA_CSR_DDR4_ADDR,
.vme_reg_offset = SVEC_FPGA_CSR_DDR4_ADDR,
.vme_dma_offset = SVEC_FPGA_DDR4_DMA,
.calib_trig_time = 0,
.calib_trig_threshold = 0,
.calib_trig_internal = 0,
......@@ -67,7 +68,8 @@ static struct fmc_adc_platform_data fa_svec_adc_pdata[] = {
.flags = FMC_ADC_BIG_ENDIAN |
FMC_ADC_SVEC |
FMC_ADC_NOSQUASH_SCATTERLIST,
.vme_ddr_offset = SVEC_FPGA_CSR_DDR5_ADDR,
.vme_reg_offset = SVEC_FPGA_CSR_DDR5_ADDR,
.vme_dma_offset = SVEC_FPGA_DDR5_DMA,
.calib_trig_time = 0,
.calib_trig_threshold = 0,
.calib_trig_internal = 0,
......
software/kernel/platform_data/fmc-adc-100m14b4cha.h
View file @ 339ad9a0
......@@ -19,7 +19,8 @@
struct fmc_adc_platform_data {
unsigned long flags;
unsigned long vme_ddr_offset;
unsigned long vme_reg_offset;
unsigned long vme_dma_offset;
uint8_t calib_trig_time;
uint8_t calib_trig_threshold;
uint8_t calib_trig_internal;
......
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