sw:drv: what for previous shot completion

With the MBLT implementation we can't anymore prepare the memory in
advance, and then execute a single DMA transfer for multiple shots.
Instead we have to handle sequentially each shot with a dedicated DMA
transfer.

The previous implementation was relying on the fact that the SVEC DDR
offset gets incremented automatically when fetching a word in single
transfer mode, and that there is no gap between two consecutive shots.
So the transition between a shot and the next one was handled
automatically at the FPGA level.

The data pre-fetch mechanism in the MBLT implementation increases the
throughput. To do this the VME slave core, fetches the next data in
DDR in advance, and this moves the DDR offset pointer. At the end of
a DMA transfer the DDR offset will not point to the last word, but
to some address after it (it depends on the pre-fetch size).

For example, a 16 bytes acquisition from DDR offset 0x0000 with
pre-fetch 4 bytes will shift the DDR offset register to 0x0014

    final DDR offset = initial DDR offset + length + pre-fetch-size
              0x0014 = 0x0000             + 0x0010 + 0x0004

This means that in our ADC acquisition we must set again the DDR
offset for the following shot (multishot mode), to the address
0x0010. Otherwise the each shot acquisition will be shifted by
pre-fetch-size number of bytes.
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>