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FMC ADC 100M 14b 4cha
Commit 19d130b1 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: major rework of SPEC reference design

parent 4adc0ef9
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gn4124-core @ 10cd74b0
Subproject commit 5066970c44f5031e2c74e55ba54bf0e9ee3dc82f
Subproject commit 10cd74b06a094c5b6c1a566676785e1814001404
wr-cores @ 0eaae143
Subproject commit 8ed042d82021206f5fda2081e98d358467fd15f2
Subproject commit 0eaae14384e368a940935d073ae9b03aa2b4e44c
hdl/syn/spec_ref_design_wr/syn_extra_steps.tcl
View file @ 19d130b1
......@@ -14,13 +14,19 @@ xilinx::project open $project_file
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
#xilinx::project set "Pack I/O Registers into IOBs" "Yes"
#xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save
xilinx::project close
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