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FMC ADC 100M 14b 4cha
Commit 0db56e03 authored by Federico Vaga's avatar Federico Vaga
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doc: let sphinx decide the best image format 

Signed-off-by: Federico Vaga's avatarFederico Vaga <federico.vaga@cern.ch>
parent ca691b87
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Showing with 14 additions and 14 deletions
doc/gateware/index.rst
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......@@ -94,7 +94,7 @@ the fmc-adc gateware architecture on the SPEC carrier. A crossbar that
is automatically generated by `cheby` is used to map the slaves in the
Wishbone address space.
.. figure:: ../fig/spec_fw_arch.svg
.. figure:: ../fig/spec_fw_arch.*
:alt: SPEC FMC-ADC gateware architecture
FMC-ADC gateware architecture on SPEC carrier.
......@@ -149,7 +149,7 @@ later in `DDR Memory Controller <#DDR-Memory-Controller>`__. A crossbar that
is automatically generated by `cheby` is used to map the slaves in the
Wishbone address space.
.. figure:: ../fig/svec_fw_arch.svg
.. figure:: ../fig/svec_fw_arch.*
:alt:
FMC-ADC gateware architecture on SVEC carrier.
......@@ -412,7 +412,7 @@ signal are synchronised to the system clock domain using a FIFO. The
configuration signals coming from registers in the system clock domain
are synchronised to the sampling clock within the Wishbone slave.
.. figure:: ../fig/adc_core_fs_clk.svg
.. figure:: ../fig/adc_core_fs_clk.*
:alt: ADC core diagram (sampling clock domain)
ADC core diagram (sampling clock domain).
......@@ -551,7 +551,7 @@ allows to insert a predefined number of sampling clock periods before
the trigger is forwarded to the acquisition state machine. the next
figure shows a simplified digram of the trigger unit.
.. figure:: ../fig/trigger_unit.svg
.. figure:: ../fig/trigger_unit.*
:alt: Trigger unit diagram
Trigger unit diagram.
......@@ -571,7 +571,7 @@ the threshold is set to 0. Note that the threshold is 16-bit signed
(two’s complement). This figure sketches the internal hardware trigger
threshold behavior.
.. figure:: ../fig/trig_hw_int.svg
.. figure:: ../fig/trig_hw_int.*
:alt: Internal hardware trigger threshold
Internal hardware trigger threshold.
......@@ -652,7 +652,7 @@ offset correction. When an input range is selected, the corresponding
gain/offset correction values must be loaded from the EEPROM to those
registers.
.. figure:: ../fig/offset_gain_corr.svg
.. figure:: ../fig/offset_gain_corr.*
:alt: ADC offset and gain correction block
ADC offset and gain correction block.
......@@ -660,7 +660,7 @@ registers.
The offset register takes a 16-bit signed value. The gain register takes
a 16-bit fixed point value. The fixed point format is as follow:
.. figure:: ../fig/adc_gain_format.svg
.. figure:: ../fig/adc_gain_format.*
:alt: ADC gain register format
ADC gain register format.
......@@ -731,7 +731,7 @@ allows to cope with the memory controller temporary unavailabilities
(due to DDR refresh cycles).
.. figure:: ../fig/adc_core_sys_clk.svg
.. figure:: ../fig/adc_core_sys_clk.*
:alt: Acquisition logic diagram (system clock domain)
Acquisition logic diagram (system clock domain).
......@@ -745,7 +745,7 @@ or 256MB.
This means that the maximum number of samples that can be stored is
128M (\ *2^{27}*16*).
.. figure:: ../fig/memory_samples.svg
.. figure:: ../fig/memory_samples.*
:alt: Illustration of samples storage in DDR memory
Illustration of samples storage in DDR memory.
......@@ -756,7 +756,7 @@ acquisition start command (``ACQ_START``). Commands are sent to the
state machine by writing in the ``FSM_CMD`` field of the control
register (the registers description can be found in :doc:`memory-map`).
.. figure:: ../fig/acq_fsm.svg
.. figure:: ../fig/acq_fsm.*
:alt: Acquisition state machine
Acquisition state machine.
......@@ -848,12 +848,12 @@ trigger moment.
The following two figures illustrate the use of the DDR memory as a
circular buffer. The acquisition state machine is also represented.
.. figure:: ../fig/memory_single-shot.svg
.. figure:: ../fig/memory_single-shot.*
:alt: Single-shot mode acquisition example
Single-shot mode acquisition example.
.. figure:: ../fig/memory_single-shot_overlap.svg
.. figure:: ../fig/memory_single-shot_overlap.*
:alt: Single-shot mode acquisition example (overlapping DDR memory)
Single-shot mode acquisition example (overlapping DDR memory).
......@@ -890,7 +890,7 @@ trigger time-tag of the first shot. The following figure shows the
shots organisation in the DDR memory.
.. figure:: ../fig/memory_multi-shot.svg
.. figure:: ../fig/memory_multi-shot.*
:alt: DDR memory usage in multi-shot mode acquisition.
DDR memory usage in multi-shot mode acquisition.
......
doc/software/tools.rst
View file @ 0db56e03
......@@ -102,7 +102,7 @@ the graphic appearance of Tk-8.4 (and earlier versions). If you prefer the
older one, run *wish8.4 tools/fau-config-if* instead of
``tools/fau-config-if`` (or set the previous version as default Tk interpreter).
.. figure:: ../fig/config-if.svg
.. figure:: ../fig/config-if.*
:alt: Two snapshots of fa-config-if
:align: center
......
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