Commit 04b11aaa authored by Dimitris Lampridis's avatar Dimitris Lampridis

hdl: reverse bit of soft reset register so that it is active high.

It is more natural to read a zero value from a register during normal operation / after reset. Also avoids the extra logic outside of the wbgen carrier_csr which was needed to accomodate the non-default value of '1'
parent 96548f64
......@@ -105,11 +105,11 @@ Controls software reset of the mezzanine including the ddr interface and the tim
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{FMC0_N}
@tab @code{X} @tab
@code{FMC0}
@tab @code{0} @tab
State of the reset line
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{fmc0_n} @tab write 0: FMC is held in reset@* write 1: Normal FMC operation (default)
@item @code{fmc0} @tab write 0: Normal FMC operation@* write 1: FMC is held in reset
@end multitable
......@@ -99,17 +99,17 @@ Controls software reset of the mezzanines including the ddr interface and the ti
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{FMC0_N}
@tab @code{X} @tab
@code{FMC0}
@tab @code{0} @tab
State of the FMC 1 reset line
@item @code{1}
@tab R/W @tab
@code{FMC1_N}
@tab @code{X} @tab
@code{FMC1}
@tab @code{0} @tab
State of the FMC 2 reset line
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{fmc0_n} @tab write 0: FMC is held in reset@* write 1: Normal FMC operation (default)
@item @code{fmc1_n} @tab write 0: FMC is held in reset@* write 1: Normal FMC operation (default)
@item @code{fmc0} @tab write 0: Normal FMC operation@* write 1: FMC is held in reset
@item @code{fmc1} @tab write 0: Normal FMC operation@* write 1: FMC is held in reset
@end multitable
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Wed Apr 23 10:05:23 2014
-- Created : Tue May 17 11:36:06 2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
......@@ -47,10 +47,8 @@ entity carrier_csr is
carrier_csr_ctrl_led_red_o : out std_logic;
-- Port for BIT field: 'DAC clear' in reg: 'Control'
carrier_csr_ctrl_dac_clr_n_o : out std_logic;
-- Ports for BIT field: 'State of the reset line' in reg: 'Reset Register'
carrier_csr_rst_fmc0_n_o : out std_logic;
carrier_csr_rst_fmc0_n_i : in std_logic;
carrier_csr_rst_fmc0_n_load_o : out std_logic
-- Port for BIT field: 'State of the reset line' in reg: 'Reset Register'
carrier_csr_rst_fmc0_o : out std_logic
);
end carrier_csr;
......@@ -59,6 +57,7 @@ architecture syn of carrier_csr is
signal carrier_csr_ctrl_led_green_int : std_logic ;
signal carrier_csr_ctrl_led_red_int : std_logic ;
signal carrier_csr_ctrl_dac_clr_n_int : std_logic ;
signal carrier_csr_rst_fmc0_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
......@@ -89,17 +88,15 @@ begin
carrier_csr_ctrl_led_green_int <= '0';
carrier_csr_ctrl_led_red_int <= '0';
carrier_csr_ctrl_dac_clr_n_int <= '0';
carrier_csr_rst_fmc0_n_load_o <= '0';
carrier_csr_rst_fmc0_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
carrier_csr_rst_fmc0_n_load_o <= '0';
ack_in_progress <= '0';
else
carrier_csr_rst_fmc0_n_load_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
......@@ -191,9 +188,9 @@ begin
ack_in_progress <= '1';
when "11" =>
if (wb_we_i = '1') then
carrier_csr_rst_fmc0_n_load_o <= '1';
carrier_csr_rst_fmc0_int <= wrdata_reg(0);
end if;
rddata_reg(0) <= carrier_csr_rst_fmc0_n_i;
rddata_reg(0) <= carrier_csr_rst_fmc0_int;
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
......@@ -254,7 +251,7 @@ begin
-- DAC clear
carrier_csr_ctrl_dac_clr_n_o <= carrier_csr_ctrl_dac_clr_n_int;
-- State of the reset line
carrier_csr_rst_fmc0_n_o <= wrdata_reg(0);
carrier_csr_rst_fmc0_o <= carrier_csr_rst_fmc0_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
......
......@@ -8,7 +8,7 @@
-- : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-02-24
-- Last update: 2016-05-13
-- Last update: 2016-05-17
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Top entity of FMC ADC 100Ms/s design for Simple PCIe FMC
......@@ -205,10 +205,7 @@ architecture rtl of spec_top_fmc_adc_100Ms is
carrier_csr_ctrl_led_green_o : out std_logic;
carrier_csr_ctrl_led_red_o : out std_logic;
carrier_csr_ctrl_dac_clr_n_o : out std_logic;
carrier_csr_rst_fmc0_n_o : out std_logic;
carrier_csr_rst_fmc0_n_i : in std_logic;
carrier_csr_rst_fmc0_n_load_o : out std_logic
);
carrier_csr_rst_fmc0_o : out std_logic);
end component carrier_csr;
component dma_eic
......@@ -347,21 +344,21 @@ architecture rtl of spec_top_fmc_adc_100Ms is
signal sys_clk_fb : std_logic;
signal sys_clk_pll_locked : std_logic;
signal clk_125m_pllref : std_logic;
-- DDR3 clock
signal ddr_clk : std_logic;
signal ddr_clk_buf : std_logic;
signal ddr_clk : std_logic;
signal ddr_clk_buf : std_logic;
-- Reset
signal powerup_reset_cnt : unsigned(7 downto 0) := "00000000";
signal powerup_rst_n : std_logic := '0';
signal sw_rst_fmc0_n : std_logic := '1';
signal sw_rst_fmc0_n_o : std_logic;
signal sw_rst_fmc0_n_i : std_logic;
signal sw_rst_fmc0_n_load : std_logic;
signal sys_rst_n : std_logic;
signal fmc0_rst_n : std_logic;
signal powerup_reset_cnt : unsigned(7 downto 0) := "00000000";
signal powerup_rst_n : std_logic := '0';
signal sys_rst_n : std_logic;
signal sw_rst_fmc0 : std_logic := '1';
signal fmc0_rst_n : std_logic;
-- prevent XST from changing the name of the signal, we want to use it in the UCF
attribute keep : string;
attribute keep of sw_rst_fmc0 : signal is "SOFT";
-- Wishbone buse(s) from crossbar master port(s)
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
......@@ -542,7 +539,7 @@ begin
end process;
sys_rst_n <= powerup_rst_n;
fmc0_rst_n <= powerup_rst_n and sw_rst_fmc0_n;
fmc0_rst_n <= powerup_rst_n and (not sw_rst_fmc0);
------------------------------------------------------------------------------
-- GN4124 interface
......@@ -717,9 +714,7 @@ begin
carrier_csr_ctrl_led_green_o => led_green,
carrier_csr_ctrl_led_red_o => led_red,
carrier_csr_ctrl_dac_clr_n_o => open,
carrier_csr_rst_fmc0_n_o => sw_rst_fmc0_n_o,
carrier_csr_rst_fmc0_n_i => sw_rst_fmc0_n_i,
carrier_csr_rst_fmc0_n_load_o => sw_rst_fmc0_n_load
carrier_csr_rst_fmc0_o => sw_rst_fmc0
);
-- Unused wishbone signals
......@@ -732,20 +727,6 @@ begin
led_red_o <= led_red;
led_green_o <= led_green;
-- external software reset register (to assign a non-zero default value)
p_sw_rst_fmc0 : process (sys_clk_125)
begin
if rising_edge(sys_clk_125) then
if sys_rst_n = '0' then
sw_rst_fmc0_n <= '1';
elsif sw_rst_fmc0_n_load = '1' then
sw_rst_fmc0_n <= sw_rst_fmc0_n_o;
end if;
end if;
end process p_sw_rst_fmc0;
sw_rst_fmc0_n_i <= sw_rst_fmc0_n;
------------------------------------------------------------------------------
-- Vectored interrupt controller (VIC)
------------------------------------------------------------------------------
......
......@@ -598,5 +598,5 @@ NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/mem
# Reset
NET "powerup_rst_n" TIG;
NET "sw_rst_fmc0_n" TIG;
NET "sw_rst_fmc0" TIG;
WBGEN2=~/projects/wbgen2/wbgen2
WBGEN2=$(shell which wbgen2)
RTL=../rtl/
TEX=../../../doc/manual/spec/
......
......@@ -3,7 +3,7 @@
* File : carrier_csr.h
* Author : auto-generated by wbgen2 from carrier_csr.wb
* Created : Wed Apr 23 10:05:23 2014
* Created : Tue May 17 11:36:06 2016
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
......@@ -79,7 +79,7 @@
/* definitions for register: Reset Register */
/* definitions for field: State of the reset line in reg: Reset Register */
#define CARRIER_CSR_RST_FMC0_N WBGEN2_GEN_MASK(0, 1)
#define CARRIER_CSR_RST_FMC0 WBGEN2_GEN_MASK(0, 1)
PACKED struct CARRIER_CSR_WB {
/* [0x0]: REG Carrier type and PCB version */
......
......@@ -429,41 +429,7 @@ carrier_csr_ctrl_dac_clr_n_o
</td>
<td class="td_pblock_right">
carrier_csr_rst_fmc0_n_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_rst_fmc0_n_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_rst_fmc0_n_load_o
carrier_csr_rst_fmc0_o
</td>
<td class="td_arrow_right">
&rarr;
......@@ -1525,15 +1491,15 @@ Controls software reset of the mezzanine including the ddr interface and the tim
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
FMC0_N
FMC0
</td>
</tr>
</table>
<ul>
<li><b>
FMC0_N
FMC0
</b>[<i>read/write</i>]: State of the reset line
<br>write 0: FMC is held in reset<br> write 1: Normal FMC operation (default)
<br>write 0: Normal FMC operation<br> write 1: FMC is held in reset
</ul>
......
......@@ -120,14 +120,13 @@ peripheral {
field {
name = "State of the reset line";
description = "write 0: FMC is held in reset\
write 1: Normal FMC operation (default)";
description = "write 0: Normal FMC operation\
write 1: FMC is held in reset";
type = BIT;
load = LOAD_EXT;
size = 1;
prefix = "fmc0_n";
access_bus = READ_WRITE;
access_dev = READ_WRITE;
prefix = "fmc0";
access_bus = WRITE;
access_dev = READ;
};
};
......
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Wed Apr 23 10:01:52 2014
-- Created : Tue May 17 11:35:37 2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
......@@ -45,20 +45,18 @@ entity carrier_csr is
carrier_csr_stat_ddr1_cal_done_i : in std_logic;
-- Port for std_logic_vector field: 'Front panel LED manual control' in reg: 'Control'
carrier_csr_ctrl_fp_leds_man_o : out std_logic_vector(15 downto 0);
-- Ports for BIT field: 'State of the FMC 1 reset line' in reg: 'Reset Register'
carrier_csr_rst_fmc0_n_o : out std_logic;
carrier_csr_rst_fmc0_n_i : in std_logic;
carrier_csr_rst_fmc0_n_load_o : out std_logic;
-- Ports for BIT field: 'State of the FMC 2 reset line' in reg: 'Reset Register'
carrier_csr_rst_fmc1_n_o : out std_logic;
carrier_csr_rst_fmc1_n_i : in std_logic;
carrier_csr_rst_fmc1_n_load_o : out std_logic
-- Port for BIT field: 'State of the FMC 1 reset line' in reg: 'Reset Register'
carrier_csr_rst_fmc0_o : out std_logic;
-- Port for BIT field: 'State of the FMC 2 reset line' in reg: 'Reset Register'
carrier_csr_rst_fmc1_o : out std_logic
);
end carrier_csr;
architecture syn of carrier_csr is
signal carrier_csr_ctrl_fp_leds_man_int : std_logic_vector(15 downto 0);
signal carrier_csr_rst_fmc0_int : std_logic ;
signal carrier_csr_rst_fmc1_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
......@@ -87,20 +85,16 @@ begin
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
carrier_csr_ctrl_fp_leds_man_int <= "0000000000000000";
carrier_csr_rst_fmc0_n_load_o <= '0';
carrier_csr_rst_fmc1_n_load_o <= '0';
carrier_csr_rst_fmc0_int <= '0';
carrier_csr_rst_fmc1_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
carrier_csr_rst_fmc0_n_load_o <= '0';
carrier_csr_rst_fmc1_n_load_o <= '0';
ack_in_progress <= '0';
else
carrier_csr_rst_fmc0_n_load_o <= '0';
carrier_csr_rst_fmc1_n_load_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
......@@ -175,11 +169,11 @@ begin
ack_in_progress <= '1';
when "11" =>
if (wb_we_i = '1') then
carrier_csr_rst_fmc0_n_load_o <= '1';
carrier_csr_rst_fmc1_n_load_o <= '1';
carrier_csr_rst_fmc0_int <= wrdata_reg(0);
carrier_csr_rst_fmc1_int <= wrdata_reg(1);
end if;
rddata_reg(0) <= carrier_csr_rst_fmc0_n_i;
rddata_reg(1) <= carrier_csr_rst_fmc1_n_i;
rddata_reg(0) <= carrier_csr_rst_fmc0_int;
rddata_reg(1) <= carrier_csr_rst_fmc1_int;
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
......@@ -236,9 +230,9 @@ begin
-- Front panel LED manual control
carrier_csr_ctrl_fp_leds_man_o <= carrier_csr_ctrl_fp_leds_man_int;
-- State of the FMC 1 reset line
carrier_csr_rst_fmc0_n_o <= wrdata_reg(0);
carrier_csr_rst_fmc0_o <= carrier_csr_rst_fmc0_int;
-- State of the FMC 2 reset line
carrier_csr_rst_fmc1_n_o <= wrdata_reg(1);
carrier_csr_rst_fmc1_o <= carrier_csr_rst_fmc1_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
......
......@@ -8,7 +8,7 @@
-- : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2013-07-04
-- Last update: 2016-05-13
-- Last update: 2016-05-17
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Top entity of FMC ADC 100Ms/s design for Simple VME FMC
......@@ -283,12 +283,8 @@ architecture rtl of svec_top_fmc_adc_100Ms is
carrier_csr_stat_ddr0_cal_done_i : in std_logic;
carrier_csr_stat_ddr1_cal_done_i : in std_logic;
carrier_csr_ctrl_fp_leds_man_o : out std_logic_vector(15 downto 0);
carrier_csr_rst_fmc0_n_o : out std_logic;
carrier_csr_rst_fmc0_n_i : in std_logic;
carrier_csr_rst_fmc0_n_load_o : out std_logic;
carrier_csr_rst_fmc1_n_o : out std_logic;
carrier_csr_rst_fmc1_n_i : in std_logic;
carrier_csr_rst_fmc1_n_load_o : out std_logic
carrier_csr_rst_fmc0_o : out std_logic;
carrier_csr_rst_fmc1_o : out std_logic
);
end component carrier_csr;
......@@ -449,24 +445,22 @@ architecture rtl of svec_top_fmc_adc_100Ms is
signal ddr_clk_buf : std_logic;
-- Reset
signal powerup_reset_cnt : unsigned(7 downto 0) := "00000000";
signal powerup_rst_n : std_logic := '0';
signal sys_rst_n : std_logic;
signal ddr_rst_n : std_logic;
signal sw_rst_fmc0_n : std_logic := '1';
signal sw_rst_fmc0_n_o : std_logic;
signal sw_rst_fmc0_n_i : std_logic;
signal sw_rst_fmc0_n_load : std_logic;
signal sw_rst_fmc1_n : std_logic := '1';
signal sw_rst_fmc1_n_o : std_logic;
signal sw_rst_fmc1_n_i : std_logic;
signal sw_rst_fmc1_n_load : std_logic;
signal ddr_sw_rst_fmc0_n : std_logic;
signal ddr_sw_rst_fmc1_n : std_logic;
signal fmc0_rst_n : std_logic;
signal fmc1_rst_n : std_logic;
signal fmc0_ddr_rst_n : std_logic;
signal fmc1_ddr_rst_n : std_logic;
signal powerup_reset_cnt : unsigned(7 downto 0) := "00000000";
signal powerup_rst_n : std_logic := '0';
signal sys_rst_n : std_logic;
signal ddr_rst_n : std_logic;
signal sw_rst_fmc0 : std_logic := '0';
signal sw_rst_fmc1 : std_logic := '0';
signal ddr_sw_rst_fmc0 : std_logic;
signal ddr_sw_rst_fmc1 : std_logic;
signal fmc0_rst_n : std_logic;
signal fmc1_rst_n : std_logic;
signal fmc0_ddr_rst_n : std_logic;
signal fmc1_ddr_rst_n : std_logic;
-- prevent XST from changing the name of the signal, we want to use it in the UCF
attribute keep : string;
attribute keep of sw_rst_fmc0 : signal is "SOFT";
attribute keep of sw_rst_fmc1 : signal is "SOFT";
-- VME
signal vme_data_b_out : std_logic_vector(31 downto 0);
......@@ -599,15 +593,15 @@ begin
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 8, -- 1GHz
CLKFBOUT_MULT => 8, -- 1GHz
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 8, -- 125MHz
CLKOUT0_DIVIDE => 8, -- 125MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 16,-- 62.5MHz
CLKOUT1_DIVIDE => 16, -- 62.5MHz
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 3, -- 333MHz
CLKOUT2_DIVIDE => 3, -- 333MHz
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 8.0,
......@@ -685,8 +679,8 @@ begin
port map (
clk_i => ddr_clk,
rst_n_i => '1',
data_i => sw_rst_fmc0_n,
synced_o => ddr_sw_rst_fmc0_n
data_i => sw_rst_fmc0,
synced_o => ddr_sw_rst_fmc0
);
-- FMC 1 reset synchronisation to DDR clock domain
......@@ -694,14 +688,14 @@ begin
port map (
clk_i => ddr_clk,
rst_n_i => '1',
data_i => sw_rst_fmc1_n,
synced_o => ddr_sw_rst_fmc1_n
data_i => sw_rst_fmc1,
synced_o => ddr_sw_rst_fmc1
);
fmc0_rst_n <= sys_rst_n and sw_rst_fmc0_n;
fmc1_rst_n <= sys_rst_n and sw_rst_fmc1_n;
fmc0_ddr_rst_n <= ddr_rst_n and ddr_sw_rst_fmc0_n;
fmc1_ddr_rst_n <= ddr_rst_n and ddr_sw_rst_fmc1_n;
fmc0_rst_n <= sys_rst_n and (not sw_rst_fmc0);
fmc1_rst_n <= sys_rst_n and (not sw_rst_fmc1);
fmc0_ddr_rst_n <= ddr_rst_n and (not ddr_sw_rst_fmc0);
fmc1_ddr_rst_n <= ddr_rst_n and (not ddr_sw_rst_fmc1);
------------------------------------------------------------------------------
-- VME interface
......@@ -887,12 +881,8 @@ begin
carrier_csr_stat_ddr0_cal_done_i => ddr0_calib_done,
carrier_csr_stat_ddr1_cal_done_i => ddr1_calib_done,
carrier_csr_ctrl_fp_leds_man_o => led_state_man,
carrier_csr_rst_fmc0_n_o => sw_rst_fmc0_n_o,
carrier_csr_rst_fmc0_n_i => sw_rst_fmc0_n_i,
carrier_csr_rst_fmc0_n_load_o => sw_rst_fmc0_n_load,
carrier_csr_rst_fmc1_n_o => sw_rst_fmc1_n_o,
carrier_csr_rst_fmc1_n_i => sw_rst_fmc1_n_i,
carrier_csr_rst_fmc1_n_load_o => sw_rst_fmc1_n_load
carrier_csr_rst_fmc0_o => sw_rst_fmc0,
carrier_csr_rst_fmc1_o => sw_rst_fmc1
);
-- Unused wishbone signals
......@@ -901,33 +891,6 @@ begin
cnx_master_in(c_WB_SLAVE_SVEC_CSR).stall <= '0';
cnx_master_in(c_WB_SLAVE_SVEC_CSR).int <= '0';
-- external software reset registers (to assign a non-zero default value)
p_sw_rst_fmc0 : process (sys_clk_125)
begin
if rising_edge(sys_clk_125) then
if sys_rst_n = '0' then
sw_rst_fmc0_n <= '1';
elsif sw_rst_fmc0_n_load = '1' then
sw_rst_fmc0_n <= sw_rst_fmc0_n_o;
end if;
end if;
end process p_sw_rst_fmc0;
sw_rst_fmc0_n_i <= sw_rst_fmc0_n;
p_sw_rst_fmc1 : process (sys_clk_125)
begin
if rising_edge(sys_clk_125) then
if sys_rst_n = '0' then
sw_rst_fmc1_n <= '1';
elsif sw_rst_fmc1_n_load = '1' then
sw_rst_fmc1_n <= sw_rst_fmc1_n_o;
end if;
end if;
end process p_sw_rst_fmc1;
sw_rst_fmc1_n_i <= sw_rst_fmc1_n;
------------------------------------------------------------------------------
-- Vectored interrupt controller (VIC)
------------------------------------------------------------------------------
......
......@@ -953,8 +953,8 @@ NET "cmp_sync_ddr_rst/sync2" TIG;
NET "cmp_sync_fmc0_rst/sync2" TIG;
NET "cmp_sync_fmc1_rst/sync2" TIG;
NET "powerup_rst_n" TIG;
NET "sw_rst_fmc0_n" TIG;
NET "sw_rst_fmc1_n" TIG;
NET "sw_rst_fmc0" TIG;
NET "sw_rst_fmc1" TIG;
......
WBGEN2=~/projects/wbgen2/wbgen2
WBGEN2=$(shell which wbgen2)
RTL=../rtl/
TEX=../../../doc/manual//svec/
......
......@@ -3,7 +3,7 @@
* File : carrier_csr.h
* Author : auto-generated by wbgen2 from carrier_csr.wb
* Created : Wed Apr 23 10:01:52 2014
* Created : Tue May 17 11:35:37 2016
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
......@@ -79,10 +79,10 @@
/* definitions for register: Reset Register */
/* definitions for field: State of the FMC 1 reset line in reg: Reset Register */
#define CARRIER_CSR_RST_FMC0_N WBGEN2_GEN_MASK(0, 1)
#define CARRIER_CSR_RST_FMC0 WBGEN2_GEN_MASK(0, 1)
/* definitions for field: State of the FMC 2 reset line in reg: Reset Register */
#define CARRIER_CSR_RST_FMC1_N WBGEN2_GEN_MASK(1, 1)
#define CARRIER_CSR_RST_FMC1 WBGEN2_GEN_MASK(1, 1)
PACKED struct CARRIER_CSR_WB {
/* [0x0]: REG Carrier type and PCB version */
......
......@@ -412,7 +412,7 @@ carrier_csr_ctrl_fp_leds_man_o[15:0]
</td>
<td class="td_pblock_right">
carrier_csr_rst_fmc0_n_o
carrier_csr_rst_fmc0_o
</td>
<td class="td_arrow_right">
&rarr;
......@@ -429,75 +429,7 @@ carrier_csr_rst_fmc0_n_o
</td>
<td class="td_pblock_right">
carrier_csr_rst_fmc0_n_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_rst_fmc0_n_load_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_rst_fmc1_n_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_rst_fmc1_n_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_rst_fmc1_n_load_o
carrier_csr_rst_fmc1_o
</td>
<td class="td_arrow_right">
&rarr;
......@@ -1552,22 +1484,22 @@ Controls software reset of the mezzanines including the ddr interface and the ti
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
FMC1_N
FMC1
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
FMC0_N
FMC0
</td>
</tr>
</table>
<ul>
<li><b>
FMC0_N
FMC0
</b>[<i>read/write</i>]: State of the FMC 1 reset line
<br>write 0: FMC is held in reset<br> write 1: Normal FMC operation (default)
<br>write 0: Normal FMC operation<br> write 1: FMC is held in reset
<li><b>
FMC1_N
FMC1
</b>[<i>read/write</i>]: State of the FMC 2 reset line
<br>write 0: FMC is held in reset<br> write 1: Normal FMC operation (default)
<br>write 0: Normal FMC operation<br> write 1: FMC is held in reset
</ul>
......
......@@ -112,27 +112,25 @@ peripheral {
field {
name = "State of the FMC 1 reset line";
description = "write 0: FMC is held in reset\
write 1: Normal FMC operation (default)";
description = "write 0: Normal FMC operation\
write 1: FMC is held in reset";
type = BIT;
load = LOAD_EXT;
size = 1;
prefix = "fmc0_n";
access_bus = READ_WRITE;
access_dev = READ_WRITE;
prefix = "fmc0";
access_bus = WRITE;
access_dev = READ;
};
field {
name = "State of the FMC 2 reset line";
description = "write 0: FMC is held in reset\
write 1: Normal FMC operation (default)";
description = "write 0: Normal FMC operation\
write 1: FMC is held in reset";
type = BIT;
load = LOAD_EXT;
size = 1;
prefix = "fmc1_n";
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
prefix = "fmc1";
access_bus = WRITE;
access_dev = READ;
};
};
};
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