-- SPDX-FileCopyrightText: 2020 CERN (home.cern)
--
-- SPDX-License-Identifier: CC-BY-SA-4.0 OR CERN-OHL-W-2.0+ OR GPL-2.0-or-later

-- Do not edit; this file was generated by Cheby using these options:
--  -i fmc_adc_eic_regs.cheby --gen-hdl=fmc_adc_eic_regs.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;

package fmc_adc_eic_regs_pkg is
  type t_fmc_adc_eic_regs_master_out is record
    idr              : std_logic_vector(31 downto 0);
    idr_wr           : std_logic;
    ier              : std_logic_vector(31 downto 0);
    ier_wr           : std_logic;
    isr              : std_logic_vector(31 downto 0);
    isr_wr           : std_logic;
  end record t_fmc_adc_eic_regs_master_out;
  subtype t_fmc_adc_eic_regs_slave_in is t_fmc_adc_eic_regs_master_out;

  type t_fmc_adc_eic_regs_slave_out is record
    imr              : std_logic_vector(31 downto 0);
    isr              : std_logic_vector(31 downto 0);
  end record t_fmc_adc_eic_regs_slave_out;
  subtype t_fmc_adc_eic_regs_master_in is t_fmc_adc_eic_regs_slave_out;
end fmc_adc_eic_regs_pkg;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.fmc_adc_eic_regs_pkg.all;

entity fmc_adc_eic_regs is
  port (
    rst_n_i              : in    std_logic;
    clk_i                : in    std_logic;
    wb_i                 : in    t_wishbone_slave_in;
    wb_o                 : out   t_wishbone_slave_out;

    -- Wires and registers
    fmc_adc_eic_regs_i   : in    t_fmc_adc_eic_regs_master_in;
    fmc_adc_eic_regs_o   : out   t_fmc_adc_eic_regs_master_out
  );
end fmc_adc_eic_regs;

architecture syn of fmc_adc_eic_regs is
  signal rd_int                         : std_logic;
  signal wr_int                         : std_logic;
  signal rd_ack_int                     : std_logic;
  signal wr_ack_int                     : std_logic;
  signal wb_en                          : std_logic;
  signal ack_int                        : std_logic;
  signal wb_rip                         : std_logic;
  signal wb_wip                         : std_logic;
  signal reg_rdat_int                   : std_logic_vector(31 downto 0);
  signal rd_ack1_int                    : std_logic;
begin

  -- WB decode signals
  wb_en <= wb_i.cyc and wb_i.stb;

  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        wb_rip <= '0';
      else
        wb_rip <= (wb_rip or (wb_en and not wb_i.we)) and not rd_ack_int;
      end if;
    end if;
  end process;
  rd_int <= (wb_en and not wb_i.we) and not wb_rip;

  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        wb_wip <= '0';
      else
        wb_wip <= (wb_wip or (wb_en and wb_i.we)) and not wr_ack_int;
      end if;
    end if;
  end process;
  wr_int <= (wb_en and wb_i.we) and not wb_wip;

  ack_int <= rd_ack_int or wr_ack_int;
  wb_o.ack <= ack_int;
  wb_o.stall <= not ack_int and wb_en;
  wb_o.rty <= '0';
  wb_o.err <= '0';

  -- Assign outputs

  -- Process for write requests.
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        wr_ack_int <= '0';
        fmc_adc_eic_regs_o.idr_wr <= '0';
        fmc_adc_eic_regs_o.ier_wr <= '0';
        fmc_adc_eic_regs_o.isr_wr <= '0';
      else
        wr_ack_int <= '0';
        fmc_adc_eic_regs_o.idr_wr <= '0';
        fmc_adc_eic_regs_o.ier_wr <= '0';
        fmc_adc_eic_regs_o.isr_wr <= '0';
        case wb_i.adr(3 downto 2) is
        when "00" => 
          -- Register idr
          fmc_adc_eic_regs_o.idr_wr <= wr_int;
          if wr_int = '1' then
            fmc_adc_eic_regs_o.idr <= wb_i.dat;
          end if;
          wr_ack_int <= wr_int;
        when "01" => 
          -- Register ier
          fmc_adc_eic_regs_o.ier_wr <= wr_int;
          if wr_int = '1' then
            fmc_adc_eic_regs_o.ier <= wb_i.dat;
          end if;
          wr_ack_int <= wr_int;
        when "10" => 
          -- Register imr
        when "11" => 
          -- Register isr
          fmc_adc_eic_regs_o.isr_wr <= wr_int;
          if wr_int = '1' then
            fmc_adc_eic_regs_o.isr <= wb_i.dat;
          end if;
          wr_ack_int <= wr_int;
        when others =>
          wr_ack_int <= wr_int;
        end case;
      end if;
    end if;
  end process;

  -- Process for registers read.
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        rd_ack1_int <= '0';
      else
        reg_rdat_int <= (others => 'X');
        case wb_i.adr(3 downto 2) is
        when "00" => 
          -- idr
          rd_ack1_int <= rd_int;
        when "01" => 
          -- ier
          rd_ack1_int <= rd_int;
        when "10" => 
          -- imr
          reg_rdat_int <= fmc_adc_eic_regs_i.imr;
          rd_ack1_int <= rd_int;
        when "11" => 
          -- isr
          reg_rdat_int <= fmc_adc_eic_regs_i.isr;
          rd_ack1_int <= rd_int;
        when others =>
          reg_rdat_int <= (others => 'X');
          rd_ack1_int <= rd_int;
        end case;
      end if;
    end if;
  end process;

  -- Process for read requests.
  process (wb_i.adr, reg_rdat_int, rd_ack1_int, rd_int) begin
    -- By default ack read requests
    wb_o.dat <= (others => '0');
    case wb_i.adr(3 downto 2) is
    when "00" => 
      -- idr
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "01" => 
      -- ier
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "10" => 
      -- imr
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "11" => 
      -- isr
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when others =>
      rd_ack_int <= rd_int;
    end case;
  end process;
end syn;
