-- SPDX-FileCopyrightText: 2020 CERN (home.cern)
--
-- SPDX-License-Identifier: CC-BY-SA-4.0 OR CERN-OHL-W-2.0+ OR GPL-2.0-or-later

-- Do not edit; this file was generated by Cheby using these options:
--  -i timetag_core_regs.cheby --gen-hdl=timetag_core_regs.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;

package timetag_core_regs_pkg is
  type t_timetag_core_master_out is record
    seconds_upper    : std_logic_vector(7 downto 0);
    seconds_upper_wr : std_logic;
    seconds_lower    : std_logic_vector(31 downto 0);
    seconds_lower_wr : std_logic;
    coarse           : std_logic_vector(27 downto 0);
    coarse_wr        : std_logic;
    time_trig_seconds_upper : std_logic_vector(7 downto 0);
    time_trig_seconds_lower : std_logic_vector(31 downto 0);
    time_trig_coarse : std_logic_vector(27 downto 0);
  end record t_timetag_core_master_out;
  subtype t_timetag_core_slave_in is t_timetag_core_master_out;

  type t_timetag_core_slave_out is record
    seconds_upper    : std_logic_vector(7 downto 0);
    seconds_lower    : std_logic_vector(31 downto 0);
    coarse           : std_logic_vector(27 downto 0);
    trig_tag_seconds_upper : std_logic_vector(7 downto 0);
    trig_tag_seconds_lower : std_logic_vector(31 downto 0);
    trig_tag_coarse  : std_logic_vector(27 downto 0);
    acq_start_tag_seconds_upper : std_logic_vector(7 downto 0);
    acq_start_tag_seconds_lower : std_logic_vector(31 downto 0);
    acq_start_tag_coarse : std_logic_vector(27 downto 0);
    acq_stop_tag_seconds_upper : std_logic_vector(7 downto 0);
    acq_stop_tag_seconds_lower : std_logic_vector(31 downto 0);
    acq_stop_tag_coarse : std_logic_vector(27 downto 0);
    acq_end_tag_seconds_upper : std_logic_vector(7 downto 0);
    acq_end_tag_seconds_lower : std_logic_vector(31 downto 0);
    acq_end_tag_coarse : std_logic_vector(27 downto 0);
  end record t_timetag_core_slave_out;
  subtype t_timetag_core_master_in is t_timetag_core_slave_out;
end timetag_core_regs_pkg;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.timetag_core_regs_pkg.all;

entity timetag_core_regs is
  port (
    rst_n_i              : in    std_logic;
    clk_i                : in    std_logic;
    wb_i                 : in    t_wishbone_slave_in;
    wb_o                 : out   t_wishbone_slave_out;

    -- Wires and registers
    timetag_core_i       : in    t_timetag_core_master_in;
    timetag_core_o       : out   t_timetag_core_master_out
  );
end timetag_core_regs;

architecture syn of timetag_core_regs is
  signal rd_int                         : std_logic;
  signal wr_int                         : std_logic;
  signal rd_ack_int                     : std_logic;
  signal wr_ack_int                     : std_logic;
  signal wb_en                          : std_logic;
  signal ack_int                        : std_logic;
  signal wb_rip                         : std_logic;
  signal wb_wip                         : std_logic;
  signal time_trig_seconds_upper_reg    : std_logic_vector(7 downto 0);
  signal time_trig_seconds_lower_reg    : std_logic_vector(31 downto 0);
  signal time_trig_coarse_reg           : std_logic_vector(27 downto 0);
  signal reg_rdat_int                   : std_logic_vector(31 downto 0);
  signal rd_ack1_int                    : std_logic;
begin

  -- WB decode signals
  wb_en <= wb_i.cyc and wb_i.stb;

  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        wb_rip <= '0';
      else
        wb_rip <= (wb_rip or (wb_en and not wb_i.we)) and not rd_ack_int;
      end if;
    end if;
  end process;
  rd_int <= (wb_en and not wb_i.we) and not wb_rip;

  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        wb_wip <= '0';
      else
        wb_wip <= (wb_wip or (wb_en and wb_i.we)) and not wr_ack_int;
      end if;
    end if;
  end process;
  wr_int <= (wb_en and wb_i.we) and not wb_wip;

  ack_int <= rd_ack_int or wr_ack_int;
  wb_o.ack <= ack_int;
  wb_o.stall <= not ack_int and wb_en;
  wb_o.rty <= '0';
  wb_o.err <= '0';

  -- Assign outputs
  timetag_core_o.time_trig_seconds_upper <= time_trig_seconds_upper_reg;
  timetag_core_o.time_trig_seconds_lower <= time_trig_seconds_lower_reg;
  timetag_core_o.time_trig_coarse <= time_trig_coarse_reg;

  -- Process for write requests.
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        wr_ack_int <= '0';
        timetag_core_o.seconds_upper_wr <= '0';
        timetag_core_o.seconds_lower_wr <= '0';
        timetag_core_o.coarse_wr <= '0';
        time_trig_seconds_upper_reg <= "00000000";
        time_trig_seconds_lower_reg <= "00000000000000000000000000000000";
        time_trig_coarse_reg <= "0000000000000000000000000000";
      else
        wr_ack_int <= '0';
        timetag_core_o.seconds_upper_wr <= '0';
        timetag_core_o.seconds_lower_wr <= '0';
        timetag_core_o.coarse_wr <= '0';
        case wb_i.adr(6 downto 2) is
        when "00000" => 
          -- Register seconds_upper
          timetag_core_o.seconds_upper_wr <= wr_int;
          if wr_int = '1' then
            timetag_core_o.seconds_upper <= wb_i.dat(7 downto 0);
          end if;
          wr_ack_int <= wr_int;
        when "00001" => 
          -- Register seconds_lower
          timetag_core_o.seconds_lower_wr <= wr_int;
          if wr_int = '1' then
            timetag_core_o.seconds_lower <= wb_i.dat;
          end if;
          wr_ack_int <= wr_int;
        when "00010" => 
          -- Register coarse
          timetag_core_o.coarse_wr <= wr_int;
          if wr_int = '1' then
            timetag_core_o.coarse <= wb_i.dat(27 downto 0);
          end if;
          wr_ack_int <= wr_int;
        when "00011" => 
          -- Register time_trig_seconds_upper
          if wr_int = '1' then
            time_trig_seconds_upper_reg <= wb_i.dat(7 downto 0);
          end if;
          wr_ack_int <= wr_int;
        when "00100" => 
          -- Register time_trig_seconds_lower
          if wr_int = '1' then
            time_trig_seconds_lower_reg <= wb_i.dat;
          end if;
          wr_ack_int <= wr_int;
        when "00101" => 
          -- Register time_trig_coarse
          if wr_int = '1' then
            time_trig_coarse_reg <= wb_i.dat(27 downto 0);
          end if;
          wr_ack_int <= wr_int;
        when "00110" => 
          -- Register trig_tag_seconds_upper
        when "00111" => 
          -- Register trig_tag_seconds_lower
        when "01000" => 
          -- Register trig_tag_coarse
        when "01001" => 
          -- Register acq_start_tag_seconds_upper
        when "01010" => 
          -- Register acq_start_tag_seconds_lower
        when "01011" => 
          -- Register acq_start_tag_coarse
        when "01100" => 
          -- Register acq_stop_tag_seconds_upper
        when "01101" => 
          -- Register acq_stop_tag_seconds_lower
        when "01110" => 
          -- Register acq_stop_tag_coarse
        when "01111" => 
          -- Register acq_end_tag_seconds_upper
        when "10000" => 
          -- Register acq_end_tag_seconds_lower
        when "10001" => 
          -- Register acq_end_tag_coarse
        when others =>
          wr_ack_int <= wr_int;
        end case;
      end if;
    end if;
  end process;

  -- Process for registers read.
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        rd_ack1_int <= '0';
      else
        reg_rdat_int <= (others => 'X');
        case wb_i.adr(6 downto 2) is
        when "00000" => 
          -- seconds_upper
          reg_rdat_int(7 downto 0) <= timetag_core_i.seconds_upper;
          rd_ack1_int <= rd_int;
        when "00001" => 
          -- seconds_lower
          reg_rdat_int <= timetag_core_i.seconds_lower;
          rd_ack1_int <= rd_int;
        when "00010" => 
          -- coarse
          reg_rdat_int(27 downto 0) <= timetag_core_i.coarse;
          rd_ack1_int <= rd_int;
        when "00011" => 
          -- time_trig_seconds_upper
          reg_rdat_int(7 downto 0) <= time_trig_seconds_upper_reg;
          rd_ack1_int <= rd_int;
        when "00100" => 
          -- time_trig_seconds_lower
          reg_rdat_int <= time_trig_seconds_lower_reg;
          rd_ack1_int <= rd_int;
        when "00101" => 
          -- time_trig_coarse
          reg_rdat_int(27 downto 0) <= time_trig_coarse_reg;
          rd_ack1_int <= rd_int;
        when "00110" => 
          -- trig_tag_seconds_upper
          reg_rdat_int(7 downto 0) <= timetag_core_i.trig_tag_seconds_upper;
          rd_ack1_int <= rd_int;
        when "00111" => 
          -- trig_tag_seconds_lower
          reg_rdat_int <= timetag_core_i.trig_tag_seconds_lower;
          rd_ack1_int <= rd_int;
        when "01000" => 
          -- trig_tag_coarse
          reg_rdat_int(27 downto 0) <= timetag_core_i.trig_tag_coarse;
          rd_ack1_int <= rd_int;
        when "01001" => 
          -- acq_start_tag_seconds_upper
          reg_rdat_int(7 downto 0) <= timetag_core_i.acq_start_tag_seconds_upper;
          rd_ack1_int <= rd_int;
        when "01010" => 
          -- acq_start_tag_seconds_lower
          reg_rdat_int <= timetag_core_i.acq_start_tag_seconds_lower;
          rd_ack1_int <= rd_int;
        when "01011" => 
          -- acq_start_tag_coarse
          reg_rdat_int(27 downto 0) <= timetag_core_i.acq_start_tag_coarse;
          rd_ack1_int <= rd_int;
        when "01100" => 
          -- acq_stop_tag_seconds_upper
          reg_rdat_int(7 downto 0) <= timetag_core_i.acq_stop_tag_seconds_upper;
          rd_ack1_int <= rd_int;
        when "01101" => 
          -- acq_stop_tag_seconds_lower
          reg_rdat_int <= timetag_core_i.acq_stop_tag_seconds_lower;
          rd_ack1_int <= rd_int;
        when "01110" => 
          -- acq_stop_tag_coarse
          reg_rdat_int(27 downto 0) <= timetag_core_i.acq_stop_tag_coarse;
          rd_ack1_int <= rd_int;
        when "01111" => 
          -- acq_end_tag_seconds_upper
          reg_rdat_int(7 downto 0) <= timetag_core_i.acq_end_tag_seconds_upper;
          rd_ack1_int <= rd_int;
        when "10000" => 
          -- acq_end_tag_seconds_lower
          reg_rdat_int <= timetag_core_i.acq_end_tag_seconds_lower;
          rd_ack1_int <= rd_int;
        when "10001" => 
          -- acq_end_tag_coarse
          reg_rdat_int(27 downto 0) <= timetag_core_i.acq_end_tag_coarse;
          rd_ack1_int <= rd_int;
        when others =>
          reg_rdat_int <= (others => 'X');
          rd_ack1_int <= rd_int;
        end case;
      end if;
    end if;
  end process;

  -- Process for read requests.
  process (wb_i.adr, reg_rdat_int, rd_ack1_int, rd_int) begin
    -- By default ack read requests
    wb_o.dat <= (others => '0');
    case wb_i.adr(6 downto 2) is
    when "00000" => 
      -- seconds_upper
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "00001" => 
      -- seconds_lower
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "00010" => 
      -- coarse
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "00011" => 
      -- time_trig_seconds_upper
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "00100" => 
      -- time_trig_seconds_lower
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "00101" => 
      -- time_trig_coarse
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "00110" => 
      -- trig_tag_seconds_upper
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "00111" => 
      -- trig_tag_seconds_lower
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "01000" => 
      -- trig_tag_coarse
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "01001" => 
      -- acq_start_tag_seconds_upper
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "01010" => 
      -- acq_start_tag_seconds_lower
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "01011" => 
      -- acq_start_tag_coarse
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "01100" => 
      -- acq_stop_tag_seconds_upper
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "01101" => 
      -- acq_stop_tag_seconds_lower
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "01110" => 
      -- acq_stop_tag_coarse
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "01111" => 
      -- acq_end_tag_seconds_upper
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "10000" => 
      -- acq_end_tag_seconds_lower
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "10001" => 
      -- acq_end_tag_coarse
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when others =>
      rd_ack_int <= rd_int;
    end case;
  end process;
end syn;
