-- SPDX-FileCopyrightText: 2020 CERN (home.cern)
--
-- SPDX-License-Identifier: CC-BY-SA-4.0 OR CERN-OHL-W-2.0+ OR GPL-2.0-or-later

-- Do not edit; this file was generated by Cheby using these options:
--  -i fmc_adc_100Ms_csr.cheby --gen-hdl=fmc_adc_100Ms_csr.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;

package fmc_adc_100ms_csr_pkg is
  type t_fmc_adc_100ms_csr_master_out is record
    ctl_fsm_cmd      : std_logic_vector(1 downto 0);
    ctl_fmc_clk_oe   : std_logic;
    ctl_offset_dac_clr_n : std_logic;
    ctl_man_bitslip  : std_logic;
    ctl_trig_led     : std_logic;
    ctl_acq_led      : std_logic;
    ctl_clear_trig_stat : std_logic;
    ctl_calib_apply  : std_logic;
    ctl_wr           : std_logic;
    trig_en_ext      : std_logic;
    trig_en_sw       : std_logic;
    trig_en_time     : std_logic;
    trig_en_aux_time : std_logic;
    trig_en_ch1      : std_logic;
    trig_en_ch2      : std_logic;
    trig_en_ch3      : std_logic;
    trig_en_ch4      : std_logic;
    trig_pol_ext     : std_logic;
    trig_pol_ch1     : std_logic;
    trig_pol_ch2     : std_logic;
    trig_pol_ch3     : std_logic;
    trig_pol_ch4     : std_logic;
    ext_trig_dly     : std_logic_vector(31 downto 0);
    sw_trig          : std_logic_vector(31 downto 0);
    sw_trig_wr       : std_logic;
    shots_nbr        : std_logic_vector(15 downto 0);
    shots_remain     : std_logic_vector(15 downto 0);
    downsample       : std_logic_vector(31 downto 0);
    pre_samples      : std_logic_vector(31 downto 0);
    post_samples     : std_logic_vector(31 downto 0);
  end record t_fmc_adc_100ms_csr_master_out;
  subtype t_fmc_adc_100ms_csr_slave_in is t_fmc_adc_100ms_csr_master_out;

  type t_fmc_adc_100ms_csr_slave_out is record
    ctl_fsm_cmd      : std_logic_vector(1 downto 0);
    ctl_man_bitslip  : std_logic;
    ctl_clear_trig_stat : std_logic;
    ctl_calib_apply  : std_logic;
    sta_fsm          : std_logic_vector(2 downto 0);
    sta_serdes_pll   : std_logic;
    sta_serdes_synced : std_logic;
    sta_acq_cfg      : std_logic;
    sta_fmc_nr       : std_logic_vector(1 downto 0);
    sta_calib_busy   : std_logic;
    trig_stat_ext    : std_logic;
    trig_stat_sw     : std_logic;
    trig_stat_time   : std_logic;
    trig_stat_ch1    : std_logic;
    trig_stat_ch2    : std_logic;
    trig_stat_ch3    : std_logic;
    trig_stat_ch4    : std_logic;
    trig_en_sw       : std_logic;
    trig_en_aux_time : std_logic;
    shots_remain     : std_logic_vector(15 downto 0);
    multi_depth      : std_logic_vector(31 downto 0);
    trig_pos         : std_logic_vector(31 downto 0);
    fs_freq          : std_logic_vector(31 downto 0);
    samples_cnt      : std_logic_vector(31 downto 0);
  end record t_fmc_adc_100ms_csr_slave_out;
  subtype t_fmc_adc_100ms_csr_master_in is t_fmc_adc_100ms_csr_slave_out;
end fmc_adc_100ms_csr_pkg;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.fmc_adc_100ms_csr_pkg.all;

entity fmc_adc_100ms_csr is
  port (
    rst_n_i              : in    std_logic;
    clk_i                : in    std_logic;
    wb_i                 : in    t_wishbone_slave_in;
    wb_o                 : out   t_wishbone_slave_out;

    -- Wires and registers
    fmc_adc_100ms_csr_i  : in    t_fmc_adc_100ms_csr_master_in;
    fmc_adc_100ms_csr_o  : out   t_fmc_adc_100ms_csr_master_out;

    -- Channel 1 registers
    fmc_adc_ch1_i        : in    t_wishbone_master_in;
    fmc_adc_ch1_o        : out   t_wishbone_master_out;

    -- Channel 2 registers
    fmc_adc_ch2_i        : in    t_wishbone_master_in;
    fmc_adc_ch2_o        : out   t_wishbone_master_out;

    -- Channel 3 registers
    fmc_adc_ch3_i        : in    t_wishbone_master_in;
    fmc_adc_ch3_o        : out   t_wishbone_master_out;

    -- Channel 4 registers
    fmc_adc_ch4_i        : in    t_wishbone_master_in;
    fmc_adc_ch4_o        : out   t_wishbone_master_out
  );
end fmc_adc_100ms_csr;

architecture syn of fmc_adc_100ms_csr is
  signal rd_int                         : std_logic;
  signal wr_int                         : std_logic;
  signal rd_ack_int                     : std_logic;
  signal wr_ack_int                     : std_logic;
  signal wb_en                          : std_logic;
  signal ack_int                        : std_logic;
  signal wb_rip                         : std_logic;
  signal wb_wip                         : std_logic;
  signal ctl_fmc_clk_oe_reg             : std_logic;
  signal ctl_offset_dac_clr_n_reg       : std_logic;
  signal ctl_trig_led_reg               : std_logic;
  signal ctl_acq_led_reg                : std_logic;
  signal trig_en_ext_reg                : std_logic;
  signal trig_en_time_reg               : std_logic;
  signal trig_en_ch1_reg                : std_logic;
  signal trig_en_ch2_reg                : std_logic;
  signal trig_en_ch3_reg                : std_logic;
  signal trig_en_ch4_reg                : std_logic;
  signal trig_pol_ext_reg               : std_logic;
  signal trig_pol_ch1_reg               : std_logic;
  signal trig_pol_ch2_reg               : std_logic;
  signal trig_pol_ch3_reg               : std_logic;
  signal trig_pol_ch4_reg               : std_logic;
  signal ext_trig_dly_reg               : std_logic_vector(31 downto 0);
  signal shots_nbr_reg                  : std_logic_vector(15 downto 0);
  signal downsample_reg                 : std_logic_vector(31 downto 0);
  signal pre_samples_reg                : std_logic_vector(31 downto 0);
  signal post_samples_reg               : std_logic_vector(31 downto 0);
  signal fmc_adc_ch1_re                 : std_logic;
  signal fmc_adc_ch1_wt                 : std_logic;
  signal fmc_adc_ch1_rt                 : std_logic;
  signal fmc_adc_ch1_tr                 : std_logic;
  signal fmc_adc_ch1_wack               : std_logic;
  signal fmc_adc_ch1_rack               : std_logic;
  signal fmc_adc_ch2_re                 : std_logic;
  signal fmc_adc_ch2_wt                 : std_logic;
  signal fmc_adc_ch2_rt                 : std_logic;
  signal fmc_adc_ch2_tr                 : std_logic;
  signal fmc_adc_ch2_wack               : std_logic;
  signal fmc_adc_ch2_rack               : std_logic;
  signal fmc_adc_ch3_re                 : std_logic;
  signal fmc_adc_ch3_wt                 : std_logic;
  signal fmc_adc_ch3_rt                 : std_logic;
  signal fmc_adc_ch3_tr                 : std_logic;
  signal fmc_adc_ch3_wack               : std_logic;
  signal fmc_adc_ch3_rack               : std_logic;
  signal fmc_adc_ch4_re                 : std_logic;
  signal fmc_adc_ch4_wt                 : std_logic;
  signal fmc_adc_ch4_rt                 : std_logic;
  signal fmc_adc_ch4_tr                 : std_logic;
  signal fmc_adc_ch4_wack               : std_logic;
  signal fmc_adc_ch4_rack               : std_logic;
  signal reg_rdat_int                   : std_logic_vector(31 downto 0);
  signal rd_ack1_int                    : std_logic;
begin

  -- WB decode signals
  wb_en <= wb_i.cyc and wb_i.stb;

  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        wb_rip <= '0';
      else
        wb_rip <= (wb_rip or (wb_en and not wb_i.we)) and not rd_ack_int;
      end if;
    end if;
  end process;
  rd_int <= (wb_en and not wb_i.we) and not wb_rip;

  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        wb_wip <= '0';
      else
        wb_wip <= (wb_wip or (wb_en and wb_i.we)) and not wr_ack_int;
      end if;
    end if;
  end process;
  wr_int <= (wb_en and wb_i.we) and not wb_wip;

  ack_int <= rd_ack_int or wr_ack_int;
  wb_o.ack <= ack_int;
  wb_o.stall <= not ack_int and wb_en;
  wb_o.rty <= '0';
  wb_o.err <= '0';

  -- Assign outputs
  fmc_adc_100ms_csr_o.ctl_fmc_clk_oe <= ctl_fmc_clk_oe_reg;
  fmc_adc_100ms_csr_o.ctl_offset_dac_clr_n <= ctl_offset_dac_clr_n_reg;
  fmc_adc_100ms_csr_o.ctl_trig_led <= ctl_trig_led_reg;
  fmc_adc_100ms_csr_o.ctl_acq_led <= ctl_acq_led_reg;
  fmc_adc_100ms_csr_o.trig_en_ext <= trig_en_ext_reg;
  fmc_adc_100ms_csr_o.trig_en_time <= trig_en_time_reg;
  fmc_adc_100ms_csr_o.trig_en_ch1 <= trig_en_ch1_reg;
  fmc_adc_100ms_csr_o.trig_en_ch2 <= trig_en_ch2_reg;
  fmc_adc_100ms_csr_o.trig_en_ch3 <= trig_en_ch3_reg;
  fmc_adc_100ms_csr_o.trig_en_ch4 <= trig_en_ch4_reg;
  fmc_adc_100ms_csr_o.trig_pol_ext <= trig_pol_ext_reg;
  fmc_adc_100ms_csr_o.trig_pol_ch1 <= trig_pol_ch1_reg;
  fmc_adc_100ms_csr_o.trig_pol_ch2 <= trig_pol_ch2_reg;
  fmc_adc_100ms_csr_o.trig_pol_ch3 <= trig_pol_ch3_reg;
  fmc_adc_100ms_csr_o.trig_pol_ch4 <= trig_pol_ch4_reg;
  fmc_adc_100ms_csr_o.ext_trig_dly <= ext_trig_dly_reg;
  fmc_adc_100ms_csr_o.shots_nbr <= shots_nbr_reg;
  fmc_adc_100ms_csr_o.downsample <= downsample_reg;
  fmc_adc_100ms_csr_o.pre_samples <= pre_samples_reg;
  fmc_adc_100ms_csr_o.post_samples <= post_samples_reg;

  -- Assignments for submap fmc_adc_ch1
  fmc_adc_ch1_tr <= fmc_adc_ch1_wt or fmc_adc_ch1_rt;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        fmc_adc_ch1_rt <= '0';
      else
        fmc_adc_ch1_rt <= (fmc_adc_ch1_rt or fmc_adc_ch1_re) and not fmc_adc_ch1_rack;
      end if;
    end if;
  end process;
  fmc_adc_ch1_o.cyc <= fmc_adc_ch1_tr;
  fmc_adc_ch1_o.stb <= fmc_adc_ch1_tr;
  fmc_adc_ch1_wack <= fmc_adc_ch1_i.ack and fmc_adc_ch1_wt;
  fmc_adc_ch1_rack <= fmc_adc_ch1_i.ack and fmc_adc_ch1_rt;
  fmc_adc_ch1_o.adr <= ((26 downto 0 => '0') & wb_i.adr(4 downto 2)) & (1 downto 0 => '0');
  fmc_adc_ch1_o.sel <= (others => '1');
  fmc_adc_ch1_o.we <= fmc_adc_ch1_wt;
  fmc_adc_ch1_o.dat <= wb_i.dat;

  -- Assignments for submap fmc_adc_ch2
  fmc_adc_ch2_tr <= fmc_adc_ch2_wt or fmc_adc_ch2_rt;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        fmc_adc_ch2_rt <= '0';
      else
        fmc_adc_ch2_rt <= (fmc_adc_ch2_rt or fmc_adc_ch2_re) and not fmc_adc_ch2_rack;
      end if;
    end if;
  end process;
  fmc_adc_ch2_o.cyc <= fmc_adc_ch2_tr;
  fmc_adc_ch2_o.stb <= fmc_adc_ch2_tr;
  fmc_adc_ch2_wack <= fmc_adc_ch2_i.ack and fmc_adc_ch2_wt;
  fmc_adc_ch2_rack <= fmc_adc_ch2_i.ack and fmc_adc_ch2_rt;
  fmc_adc_ch2_o.adr <= ((26 downto 0 => '0') & wb_i.adr(4 downto 2)) & (1 downto 0 => '0');
  fmc_adc_ch2_o.sel <= (others => '1');
  fmc_adc_ch2_o.we <= fmc_adc_ch2_wt;
  fmc_adc_ch2_o.dat <= wb_i.dat;

  -- Assignments for submap fmc_adc_ch3
  fmc_adc_ch3_tr <= fmc_adc_ch3_wt or fmc_adc_ch3_rt;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        fmc_adc_ch3_rt <= '0';
      else
        fmc_adc_ch3_rt <= (fmc_adc_ch3_rt or fmc_adc_ch3_re) and not fmc_adc_ch3_rack;
      end if;
    end if;
  end process;
  fmc_adc_ch3_o.cyc <= fmc_adc_ch3_tr;
  fmc_adc_ch3_o.stb <= fmc_adc_ch3_tr;
  fmc_adc_ch3_wack <= fmc_adc_ch3_i.ack and fmc_adc_ch3_wt;
  fmc_adc_ch3_rack <= fmc_adc_ch3_i.ack and fmc_adc_ch3_rt;
  fmc_adc_ch3_o.adr <= ((26 downto 0 => '0') & wb_i.adr(4 downto 2)) & (1 downto 0 => '0');
  fmc_adc_ch3_o.sel <= (others => '1');
  fmc_adc_ch3_o.we <= fmc_adc_ch3_wt;
  fmc_adc_ch3_o.dat <= wb_i.dat;

  -- Assignments for submap fmc_adc_ch4
  fmc_adc_ch4_tr <= fmc_adc_ch4_wt or fmc_adc_ch4_rt;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        fmc_adc_ch4_rt <= '0';
      else
        fmc_adc_ch4_rt <= (fmc_adc_ch4_rt or fmc_adc_ch4_re) and not fmc_adc_ch4_rack;
      end if;
    end if;
  end process;
  fmc_adc_ch4_o.cyc <= fmc_adc_ch4_tr;
  fmc_adc_ch4_o.stb <= fmc_adc_ch4_tr;
  fmc_adc_ch4_wack <= fmc_adc_ch4_i.ack and fmc_adc_ch4_wt;
  fmc_adc_ch4_rack <= fmc_adc_ch4_i.ack and fmc_adc_ch4_rt;
  fmc_adc_ch4_o.adr <= ((26 downto 0 => '0') & wb_i.adr(4 downto 2)) & (1 downto 0 => '0');
  fmc_adc_ch4_o.sel <= (others => '1');
  fmc_adc_ch4_o.we <= fmc_adc_ch4_wt;
  fmc_adc_ch4_o.dat <= wb_i.dat;

  -- Process for write requests.
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        wr_ack_int <= '0';
        fmc_adc_100ms_csr_o.ctl_wr <= '0';
        ctl_fmc_clk_oe_reg <= '0';
        ctl_offset_dac_clr_n_reg <= '0';
        ctl_trig_led_reg <= '0';
        ctl_acq_led_reg <= '0';
        trig_en_ext_reg <= '0';
        trig_en_time_reg <= '0';
        trig_en_ch1_reg <= '0';
        trig_en_ch2_reg <= '0';
        trig_en_ch3_reg <= '0';
        trig_en_ch4_reg <= '0';
        trig_pol_ext_reg <= '0';
        trig_pol_ch1_reg <= '0';
        trig_pol_ch2_reg <= '0';
        trig_pol_ch3_reg <= '0';
        trig_pol_ch4_reg <= '0';
        ext_trig_dly_reg <= "00000000000000000000000000000000";
        fmc_adc_100ms_csr_o.sw_trig_wr <= '0';
        shots_nbr_reg <= "0000000000000000";
        downsample_reg <= "00000000000000000000000000000000";
        pre_samples_reg <= "00000000000000000000000000000000";
        post_samples_reg <= "00000000000000000000000000000000";
        fmc_adc_ch1_wt <= '0';
        fmc_adc_ch2_wt <= '0';
        fmc_adc_ch3_wt <= '0';
        fmc_adc_ch4_wt <= '0';
      else
        wr_ack_int <= '0';
        fmc_adc_100ms_csr_o.ctl_wr <= '0';
        fmc_adc_100ms_csr_o.sw_trig_wr <= '0';
        fmc_adc_ch1_wt <= '0';
        fmc_adc_ch2_wt <= '0';
        fmc_adc_ch3_wt <= '0';
        fmc_adc_ch4_wt <= '0';
        case wb_i.adr(8 downto 5) is
        when "0000" => 
          case wb_i.adr(4 downto 2) is
          when "000" => 
            -- Register ctl
            fmc_adc_100ms_csr_o.ctl_wr <= wr_int;
            if wr_int = '1' then
              fmc_adc_100ms_csr_o.ctl_fsm_cmd <= wb_i.dat(1 downto 0);
              ctl_fmc_clk_oe_reg <= wb_i.dat(2);
              ctl_offset_dac_clr_n_reg <= wb_i.dat(3);
              fmc_adc_100ms_csr_o.ctl_man_bitslip <= wb_i.dat(4);
              ctl_trig_led_reg <= wb_i.dat(6);
              ctl_acq_led_reg <= wb_i.dat(7);
              fmc_adc_100ms_csr_o.ctl_clear_trig_stat <= wb_i.dat(8);
              fmc_adc_100ms_csr_o.ctl_calib_apply <= wb_i.dat(15);
            end if;
            wr_ack_int <= wr_int;
          when "001" => 
            -- Register sta
          when "010" => 
            -- Register trig_stat
          when "011" => 
            -- Register trig_en
            if wr_int = '1' then
              trig_en_ext_reg <= wb_i.dat(0);
              fmc_adc_100ms_csr_o.trig_en_sw <= wb_i.dat(1);
              trig_en_time_reg <= wb_i.dat(4);
              fmc_adc_100ms_csr_o.trig_en_aux_time <= wb_i.dat(5);
              trig_en_ch1_reg <= wb_i.dat(8);
              trig_en_ch2_reg <= wb_i.dat(9);
              trig_en_ch3_reg <= wb_i.dat(10);
              trig_en_ch4_reg <= wb_i.dat(11);
            end if;
            wr_ack_int <= wr_int;
          when "100" => 
            -- Register trig_pol
            if wr_int = '1' then
              trig_pol_ext_reg <= wb_i.dat(0);
              trig_pol_ch1_reg <= wb_i.dat(8);
              trig_pol_ch2_reg <= wb_i.dat(9);
              trig_pol_ch3_reg <= wb_i.dat(10);
              trig_pol_ch4_reg <= wb_i.dat(11);
            end if;
            wr_ack_int <= wr_int;
          when "101" => 
            -- Register ext_trig_dly
            if wr_int = '1' then
              ext_trig_dly_reg <= wb_i.dat;
            end if;
            wr_ack_int <= wr_int;
          when "110" => 
            -- Register sw_trig
            fmc_adc_100ms_csr_o.sw_trig_wr <= wr_int;
            if wr_int = '1' then
              fmc_adc_100ms_csr_o.sw_trig <= wb_i.dat;
            end if;
            wr_ack_int <= wr_int;
          when "111" => 
            -- Register shots
            if wr_int = '1' then
              shots_nbr_reg <= wb_i.dat(15 downto 0);
              fmc_adc_100ms_csr_o.shots_remain <= wb_i.dat(31 downto 16);
            end if;
            wr_ack_int <= wr_int;
          when others =>
            wr_ack_int <= wr_int;
          end case;
        when "0001" => 
          case wb_i.adr(4 downto 2) is
          when "000" => 
            -- Register multi_depth
          when "001" => 
            -- Register trig_pos
          when "010" => 
            -- Register fs_freq
          when "011" => 
            -- Register downsample
            if wr_int = '1' then
              downsample_reg <= wb_i.dat;
            end if;
            wr_ack_int <= wr_int;
          when "100" => 
            -- Register pre_samples
            if wr_int = '1' then
              pre_samples_reg <= wb_i.dat;
            end if;
            wr_ack_int <= wr_int;
          when "101" => 
            -- Register post_samples
            if wr_int = '1' then
              post_samples_reg <= wb_i.dat;
            end if;
            wr_ack_int <= wr_int;
          when "110" => 
            -- Register samples_cnt
          when others =>
            wr_ack_int <= wr_int;
          end case;
        when "0100" => 
          -- Submap fmc_adc_ch1
          fmc_adc_ch1_wt <= (fmc_adc_ch1_wt or wr_int) and not fmc_adc_ch1_wack;
          wr_ack_int <= fmc_adc_ch1_wack;
        when "0110" => 
          -- Submap fmc_adc_ch2
          fmc_adc_ch2_wt <= (fmc_adc_ch2_wt or wr_int) and not fmc_adc_ch2_wack;
          wr_ack_int <= fmc_adc_ch2_wack;
        when "1000" => 
          -- Submap fmc_adc_ch3
          fmc_adc_ch3_wt <= (fmc_adc_ch3_wt or wr_int) and not fmc_adc_ch3_wack;
          wr_ack_int <= fmc_adc_ch3_wack;
        when "1010" => 
          -- Submap fmc_adc_ch4
          fmc_adc_ch4_wt <= (fmc_adc_ch4_wt or wr_int) and not fmc_adc_ch4_wack;
          wr_ack_int <= fmc_adc_ch4_wack;
        when others =>
          wr_ack_int <= wr_int;
        end case;
      end if;
    end if;
  end process;

  -- Process for registers read.
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        rd_ack1_int <= '0';
      else
        reg_rdat_int <= (others => 'X');
        case wb_i.adr(8 downto 5) is
        when "0000" => 
          case wb_i.adr(4 downto 2) is
          when "000" => 
            -- ctl
            reg_rdat_int(1 downto 0) <= fmc_adc_100ms_csr_i.ctl_fsm_cmd;
            reg_rdat_int(2) <= ctl_fmc_clk_oe_reg;
            reg_rdat_int(3) <= ctl_offset_dac_clr_n_reg;
            reg_rdat_int(4) <= fmc_adc_100ms_csr_i.ctl_man_bitslip;
            reg_rdat_int(6) <= ctl_trig_led_reg;
            reg_rdat_int(7) <= ctl_acq_led_reg;
            reg_rdat_int(8) <= fmc_adc_100ms_csr_i.ctl_clear_trig_stat;
            reg_rdat_int(15) <= fmc_adc_100ms_csr_i.ctl_calib_apply;
            rd_ack1_int <= rd_int;
          when "001" => 
            -- sta
            reg_rdat_int(2 downto 0) <= fmc_adc_100ms_csr_i.sta_fsm;
            reg_rdat_int(3) <= fmc_adc_100ms_csr_i.sta_serdes_pll;
            reg_rdat_int(4) <= fmc_adc_100ms_csr_i.sta_serdes_synced;
            reg_rdat_int(5) <= fmc_adc_100ms_csr_i.sta_acq_cfg;
            reg_rdat_int(7 downto 6) <= fmc_adc_100ms_csr_i.sta_fmc_nr;
            reg_rdat_int(15) <= fmc_adc_100ms_csr_i.sta_calib_busy;
            rd_ack1_int <= rd_int;
          when "010" => 
            -- trig_stat
            reg_rdat_int(0) <= fmc_adc_100ms_csr_i.trig_stat_ext;
            reg_rdat_int(1) <= fmc_adc_100ms_csr_i.trig_stat_sw;
            reg_rdat_int(4) <= fmc_adc_100ms_csr_i.trig_stat_time;
            reg_rdat_int(8) <= fmc_adc_100ms_csr_i.trig_stat_ch1;
            reg_rdat_int(9) <= fmc_adc_100ms_csr_i.trig_stat_ch2;
            reg_rdat_int(10) <= fmc_adc_100ms_csr_i.trig_stat_ch3;
            reg_rdat_int(11) <= fmc_adc_100ms_csr_i.trig_stat_ch4;
            rd_ack1_int <= rd_int;
          when "011" => 
            -- trig_en
            reg_rdat_int(0) <= trig_en_ext_reg;
            reg_rdat_int(1) <= fmc_adc_100ms_csr_i.trig_en_sw;
            reg_rdat_int(4) <= trig_en_time_reg;
            reg_rdat_int(5) <= fmc_adc_100ms_csr_i.trig_en_aux_time;
            reg_rdat_int(8) <= trig_en_ch1_reg;
            reg_rdat_int(9) <= trig_en_ch2_reg;
            reg_rdat_int(10) <= trig_en_ch3_reg;
            reg_rdat_int(11) <= trig_en_ch4_reg;
            rd_ack1_int <= rd_int;
          when "100" => 
            -- trig_pol
            reg_rdat_int(0) <= trig_pol_ext_reg;
            reg_rdat_int(8) <= trig_pol_ch1_reg;
            reg_rdat_int(9) <= trig_pol_ch2_reg;
            reg_rdat_int(10) <= trig_pol_ch3_reg;
            reg_rdat_int(11) <= trig_pol_ch4_reg;
            rd_ack1_int <= rd_int;
          when "101" => 
            -- ext_trig_dly
            reg_rdat_int <= ext_trig_dly_reg;
            rd_ack1_int <= rd_int;
          when "110" => 
            -- sw_trig
            rd_ack1_int <= rd_int;
          when "111" => 
            -- shots
            reg_rdat_int(15 downto 0) <= shots_nbr_reg;
            reg_rdat_int(31 downto 16) <= fmc_adc_100ms_csr_i.shots_remain;
            rd_ack1_int <= rd_int;
          when others =>
            reg_rdat_int <= (others => 'X');
            rd_ack1_int <= rd_int;
          end case;
        when "0001" => 
          case wb_i.adr(4 downto 2) is
          when "000" => 
            -- multi_depth
            reg_rdat_int <= fmc_adc_100ms_csr_i.multi_depth;
            rd_ack1_int <= rd_int;
          when "001" => 
            -- trig_pos
            reg_rdat_int <= fmc_adc_100ms_csr_i.trig_pos;
            rd_ack1_int <= rd_int;
          when "010" => 
            -- fs_freq
            reg_rdat_int <= fmc_adc_100ms_csr_i.fs_freq;
            rd_ack1_int <= rd_int;
          when "011" => 
            -- downsample
            reg_rdat_int <= downsample_reg;
            rd_ack1_int <= rd_int;
          when "100" => 
            -- pre_samples
            reg_rdat_int <= pre_samples_reg;
            rd_ack1_int <= rd_int;
          when "101" => 
            -- post_samples
            reg_rdat_int <= post_samples_reg;
            rd_ack1_int <= rd_int;
          when "110" => 
            -- samples_cnt
            reg_rdat_int <= fmc_adc_100ms_csr_i.samples_cnt;
            rd_ack1_int <= rd_int;
          when others =>
            reg_rdat_int <= (others => 'X');
            rd_ack1_int <= rd_int;
          end case;
        when "0100" => 
        when "0110" => 
        when "1000" => 
        when "1010" => 
        when others =>
          reg_rdat_int <= (others => 'X');
          rd_ack1_int <= rd_int;
        end case;
      end if;
    end if;
  end process;

  -- Process for read requests.
  process (wb_i.adr, reg_rdat_int, rd_ack1_int, rd_int, rd_int, fmc_adc_ch1_i.dat, fmc_adc_ch1_rack, fmc_adc_ch1_rt, rd_int, fmc_adc_ch2_i.dat, fmc_adc_ch2_rack, fmc_adc_ch2_rt, rd_int, fmc_adc_ch3_i.dat, fmc_adc_ch3_rack, fmc_adc_ch3_rt, rd_int, fmc_adc_ch4_i.dat, fmc_adc_ch4_rack, fmc_adc_ch4_rt) begin
    -- By default ack read requests
    wb_o.dat <= (others => '0');
    fmc_adc_ch1_re <= '0';
    fmc_adc_ch2_re <= '0';
    fmc_adc_ch3_re <= '0';
    fmc_adc_ch4_re <= '0';
    case wb_i.adr(8 downto 5) is
    when "0000" => 
      case wb_i.adr(4 downto 2) is
      when "000" => 
        -- ctl
        wb_o.dat <= reg_rdat_int;
        rd_ack_int <= rd_ack1_int;
      when "001" => 
        -- sta
        wb_o.dat <= reg_rdat_int;
        rd_ack_int <= rd_ack1_int;
      when "010" => 
        -- trig_stat
        wb_o.dat <= reg_rdat_int;
        rd_ack_int <= rd_ack1_int;
      when "011" => 
        -- trig_en
        wb_o.dat <= reg_rdat_int;
        rd_ack_int <= rd_ack1_int;
      when "100" => 
        -- trig_pol
        wb_o.dat <= reg_rdat_int;
        rd_ack_int <= rd_ack1_int;
      when "101" => 
        -- ext_trig_dly
        wb_o.dat <= reg_rdat_int;
        rd_ack_int <= rd_ack1_int;
      when "110" => 
        -- sw_trig
        wb_o.dat <= reg_rdat_int;
        rd_ack_int <= rd_ack1_int;
      when "111" => 
        -- shots
        wb_o.dat <= reg_rdat_int;
        rd_ack_int <= rd_ack1_int;
      when others =>
        rd_ack_int <= rd_int;
      end case;
    when "0001" => 
      case wb_i.adr(4 downto 2) is
      when "000" => 
        -- multi_depth
        wb_o.dat <= reg_rdat_int;
        rd_ack_int <= rd_ack1_int;
      when "001" => 
        -- trig_pos
        wb_o.dat <= reg_rdat_int;
        rd_ack_int <= rd_ack1_int;
      when "010" => 
        -- fs_freq
        wb_o.dat <= reg_rdat_int;
        rd_ack_int <= rd_ack1_int;
      when "011" => 
        -- downsample
        wb_o.dat <= reg_rdat_int;
        rd_ack_int <= rd_ack1_int;
      when "100" => 
        -- pre_samples
        wb_o.dat <= reg_rdat_int;
        rd_ack_int <= rd_ack1_int;
      when "101" => 
        -- post_samples
        wb_o.dat <= reg_rdat_int;
        rd_ack_int <= rd_ack1_int;
      when "110" => 
        -- samples_cnt
        wb_o.dat <= reg_rdat_int;
        rd_ack_int <= rd_ack1_int;
      when others =>
        rd_ack_int <= rd_int;
      end case;
    when "0100" => 
      -- Submap fmc_adc_ch1
      fmc_adc_ch1_re <= rd_int;
      wb_o.dat <= fmc_adc_ch1_i.dat;
      rd_ack_int <= fmc_adc_ch1_rack;
    when "0110" => 
      -- Submap fmc_adc_ch2
      fmc_adc_ch2_re <= rd_int;
      wb_o.dat <= fmc_adc_ch2_i.dat;
      rd_ack_int <= fmc_adc_ch2_rack;
    when "1000" => 
      -- Submap fmc_adc_ch3
      fmc_adc_ch3_re <= rd_int;
      wb_o.dat <= fmc_adc_ch3_i.dat;
      rd_ack_int <= fmc_adc_ch3_rack;
    when "1010" => 
      -- Submap fmc_adc_ch4
      fmc_adc_ch4_re <= rd_int;
      wb_o.dat <= fmc_adc_ch4_i.dat;
      rd_ack_int <= fmc_adc_ch4_rack;
    when others =>
      rd_ack_int <= rd_int;
    end case;
  end process;
end syn;
