# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC-BY-SA-4.0 OR CERN-OHL-W-2.0+ OR GPL-2.0-or-later

memory-map:
  bus: wb-32-be
  name: aux_trigout
  description: FMC ADC aux trigger out registers
  x-hdl:
    busgroup: True
    reg-prefix: False
  children:
  - reg:
     name: status
     description: Status register
     access: ro
     width: 32
     children:
       - field:
          name: wr_enable
          description: Set when WR is enabled
          range: 0
       - field:
          name: wr_link
          description: WR link status
          range: 1
       - field:
          name: wr_valid
          description: Set when WR time is valid
          range: 2
       - field:
          name: ts_present
          description: Set when the timestamp fifo is not empty
          range: 8
  - reg:
     name: ts_mask_sec
     description: Time (seconds) of the last event
     width: 64
     access: ro
     children:
       - field:
          name: ts_sec
          description: Seconds part of the timestamp
          range: 39-0
       - field:
          name: ch1_mask
          description: Set if channel 1 triggered
          range: 48
       - field:
          name: ch2_mask
          description: Set if channel 2 triggered
          range: 49
       - field:
          name: ch3_mask
          description: Set if channel 3 triggered
          range: 50
       - field:
          name: ch4_mask
          description: Set if channel 4 triggered
          range: 51
       - field:
          name: ext_mask
          description: Set if external trigger
          range: 56
  - reg:
     name: ts_cycles
     description: Cycles part of timestamp fifo.
     comment: Reading this register discards the entry
     width: 32
     access: ro
     x-hdl:
       read-strobe: True
     children:
       - field:
          name: cycles
          description: Cycles
          range: 27-0
