# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC-BY-SA-4.0 OR CERN-OHL-W-2.0+ OR GPL-2.0-or-later

memory-map:
  bus: wb-32-be
  name: fmc_adc_100ms_channel_regs
  description: FMC ADC 100MS/s channel configuration registers
  comment: |
    Wishbone slave for FMC ADC 100MS/s CSR
  x-hdl:
    busgroup: True
    iogroup: fmc_adc_100ms_ch
  children:
  - reg:
      name: ctl
      address: 0x00000000
      width: 32
      access: rw
      description: Channel control register
      children:
      - field:
          name: ssr
          range: 6-0
          description: Solid state relays control for channel
          comment: |
            Controls input voltage range, termination and DC offset error calibration
            0x23: 100mV range
            0x11: 1V range
            0x45: 10V range
            0x00: Open input
            0x42: 100mV range calibration
            0x40: 1V range calibration
            0x44: 10V range calibration
            Bit3 is indepandant of the others and enables the 50ohms termination.
  - reg:
      name: sta
      address: 0x00000004
      width: 32
      access: ro
      description: Channel status register
      children:
      - field:
          name: val
          range: 15-0
          description: Channel current ADC value
          comment: |
            Current ADC raw value. The format depends on ADC configuration; Upon reset, the ADC is
            configured for "offset binary". The FMC-ADC driver when loaded, will change this to
            binary two\'s complement.
  - reg:
      name: calib
      address: 0x00000008
      width: 32
      access: rw
      description: Channel calibration register
      children:
      - field:
          name: gain
          range: 15-0
          description: Gain calibration for channel
          comment: |
            Gain applied to all data coming from the ADC.
            Fixed point format:
            Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
      - field:
          name: offset
          range: 31-16
          description: Offset calibration for channel
          comment: |
            Offset applied to all data coming from the ADC. The format is binary two\'s complement.
  - reg:
      name: sat
      address: 0x0000000c
      width: 32
      access: rw
      description: Channel saturation register
      children:
      - field:
          name: val
          range: 14-0
          description: Saturation value for channel
          comment: |
            Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
  - reg:
      name: trig_thres
      address: 0x00000010
      width: 32
      access: rw
      description: Channel trigger threshold configuration register
      children:
      - field:
          name: val
          range: 15-0
          description: Threshold for internal trigger
          comment: |
            Treated as binary two\'s complement and compared to raw ADC data.
      - field:
          name: hyst
          range: 31-16
          description: Internal trigger threshold hysteresis
          comment: |
            Configures the internal trigger threshold hysteresis.
            The value is always unsigned, and the gateware will subtract/add it based on the configured trigger polarity.
  - reg:
      name: trig_dly
      address: 0x00000014
      width: 32
      access: rw
      description: Channel trigger delay
      comment: |
        Delay to apply on the trigger in sampling clock period.
        The default clock frequency is 100MHz (period = 10ns).
