-- SPDX-FileCopyrightText: 2020 CERN (home.cern)
--
-- SPDX-License-Identifier: CC-BY-SA-4.0 OR CERN-OHL-W-2.0+ OR GPL-2.0-or-later

-- Do not edit; this file was generated by Cheby using these options:
--  -i fmc_adc_eic_regs.cheby --gen-hdl=fmc_adc_eic_regs.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;

package fmc_adc_eic_regs_pkg is
  type t_fmc_adc_eic_regs_master_out is record
    idr              : std_logic_vector(31 downto 0);
    idr_wr           : std_logic;
    ier              : std_logic_vector(31 downto 0);
    ier_wr           : std_logic;
    isr              : std_logic_vector(31 downto 0);
    isr_wr           : std_logic;
  end record t_fmc_adc_eic_regs_master_out;
  subtype t_fmc_adc_eic_regs_slave_in is t_fmc_adc_eic_regs_master_out;

  type t_fmc_adc_eic_regs_slave_out is record
    imr              : std_logic_vector(31 downto 0);
    isr              : std_logic_vector(31 downto 0);
  end record t_fmc_adc_eic_regs_slave_out;
  subtype t_fmc_adc_eic_regs_master_in is t_fmc_adc_eic_regs_slave_out;
end fmc_adc_eic_regs_pkg;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.fmc_adc_eic_regs_pkg.all;

entity fmc_adc_eic_regs is
  port (
    rst_n_i              : in    std_logic;
    clk_i                : in    std_logic;
    wb_i                 : in    t_wishbone_slave_in;
    wb_o                 : out   t_wishbone_slave_out;
    -- Wires and registers
    fmc_adc_eic_regs_i   : in    t_fmc_adc_eic_regs_master_in;
    fmc_adc_eic_regs_o   : out   t_fmc_adc_eic_regs_master_out
  );
end fmc_adc_eic_regs;

architecture syn of fmc_adc_eic_regs is
  signal adr_int                        : std_logic_vector(3 downto 2);
  signal rd_req_int                     : std_logic;
  signal wr_req_int                     : std_logic;
  signal rd_ack_int                     : std_logic;
  signal wr_ack_int                     : std_logic;
  signal wb_en                          : std_logic;
  signal ack_int                        : std_logic;
  signal wb_rip                         : std_logic;
  signal wb_wip                         : std_logic;
  signal idr_wreq                       : std_logic;
  signal ier_wreq                       : std_logic;
  signal isr_wreq                       : std_logic;
  signal rd_ack_d0                      : std_logic;
  signal rd_dat_d0                      : std_logic_vector(31 downto 0);
  signal wr_req_d0                      : std_logic;
  signal wr_adr_d0                      : std_logic_vector(3 downto 2);
  signal wr_dat_d0                      : std_logic_vector(31 downto 0);
  signal wr_sel_d0                      : std_logic_vector(3 downto 0);
begin

  -- WB decode signals
  adr_int <= wb_i.adr(3 downto 2);
  wb_en <= wb_i.cyc and wb_i.stb;

  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        wb_rip <= '0';
      else
        wb_rip <= (wb_rip or (wb_en and not wb_i.we)) and not rd_ack_int;
      end if;
    end if;
  end process;
  rd_req_int <= (wb_en and not wb_i.we) and not wb_rip;

  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        wb_wip <= '0';
      else
        wb_wip <= (wb_wip or (wb_en and wb_i.we)) and not wr_ack_int;
      end if;
    end if;
  end process;
  wr_req_int <= (wb_en and wb_i.we) and not wb_wip;

  ack_int <= rd_ack_int or wr_ack_int;
  wb_o.ack <= ack_int;
  wb_o.stall <= not ack_int and wb_en;
  wb_o.rty <= '0';
  wb_o.err <= '0';

  -- pipelining for wr-in+rd-out
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        rd_ack_int <= '0';
        wr_req_d0 <= '0';
      else
        rd_ack_int <= rd_ack_d0;
        wb_o.dat <= rd_dat_d0;
        wr_req_d0 <= wr_req_int;
        wr_adr_d0 <= adr_int;
        wr_dat_d0 <= wb_i.dat;
        wr_sel_d0 <= wb_i.sel;
      end if;
    end if;
  end process;

  -- Register idr
  fmc_adc_eic_regs_o.idr <= wr_dat_d0;
  fmc_adc_eic_regs_o.idr_wr <= idr_wreq;

  -- Register ier
  fmc_adc_eic_regs_o.ier <= wr_dat_d0;
  fmc_adc_eic_regs_o.ier_wr <= ier_wreq;

  -- Register imr

  -- Register isr
  fmc_adc_eic_regs_o.isr <= wr_dat_d0;
  fmc_adc_eic_regs_o.isr_wr <= isr_wreq;

  -- Process for write requests.
  process (wr_adr_d0, wr_req_d0) begin
    idr_wreq <= '0';
    ier_wreq <= '0';
    isr_wreq <= '0';
    case wr_adr_d0(3 downto 2) is
    when "00" =>
      -- Reg idr
      idr_wreq <= wr_req_d0;
      wr_ack_int <= wr_req_d0;
    when "01" =>
      -- Reg ier
      ier_wreq <= wr_req_d0;
      wr_ack_int <= wr_req_d0;
    when "10" =>
      -- Reg imr
      wr_ack_int <= wr_req_d0;
    when "11" =>
      -- Reg isr
      isr_wreq <= wr_req_d0;
      wr_ack_int <= wr_req_d0;
    when others =>
      wr_ack_int <= wr_req_d0;
    end case;
  end process;

  -- Process for read requests.
  process (adr_int, rd_req_int, fmc_adc_eic_regs_i.imr, fmc_adc_eic_regs_i.isr) begin
    -- By default ack read requests
    rd_dat_d0 <= (others => 'X');
    case adr_int(3 downto 2) is
    when "00" =>
      -- Reg idr
      rd_ack_d0 <= rd_req_int;
    when "01" =>
      -- Reg ier
      rd_ack_d0 <= rd_req_int;
    when "10" =>
      -- Reg imr
      rd_ack_d0 <= rd_req_int;
      rd_dat_d0 <= fmc_adc_eic_regs_i.imr;
    when "11" =>
      -- Reg isr
      rd_ack_d0 <= rd_req_int;
      rd_dat_d0 <= fmc_adc_eic_regs_i.isr;
    when others =>
      rd_ack_d0 <= rd_req_int;
    end case;
  end process;
end syn;
